tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s

   1 ;/*****************************************************************************
   2 ; * @file:    startup_LPC8xx.s
   3 ; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
   4 ; *           for the NXP LPC8xx Device Series
   5 ; * @version: V1.0
   6 ; * @date:    16. Aug. 2012
   7 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
   8 ; *
   9 ; * Copyright (C) 2012 ARM Limited. All rights reserved.
  10 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
  11 ; * processor based microcontrollers.  This file can be freely distributed
  12 ; * within development tools that are supporting such ARM based processors.
  13 ; *
  14 ; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  15 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  16 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  17 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  18 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  19 ; *
  20 ; *****************************************************************************/
  21
  22
  23 ; <h> Stack Configuration
  24 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
  25 ; </h>
  26
  27                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
  28                 EXPORT  __initial_sp
  29
  30 __initial_sp            EQU     0x10002000
  31
  32
  33 ; <h> Heap Configuration
  34 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
  35 ; </h>
  36
  37 Heap_Size       EQU     0x00000000
  38
  39                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
  40                 EXPORT  __heap_base
  41                 EXPORT  __heap_limit
  42
  43 __heap_base
  44 Heap_Mem        SPACE   Heap_Size
  45 __heap_limit
  46
  47                 PRESERVE8
  48                 THUMB
  49
  50
  51 ; Vector Table Mapped to Address 0 at Reset
  52
  53                 AREA    RESET, DATA, READONLY
  54                 EXPORT  __Vectors
  55
  56 __Vectors       DCD     __initial_sp              ; Top of Stack
  57                 DCD     Reset_Handler             ; Reset Handler
  58                 DCD     NMI_Handler               ; NMI Handler
  59                 DCD     HardFault_Handler         ; Hard Fault Handler
  60                 DCD     0                         ; Reserved
  61                 DCD     0                         ; Reserved
  62                 DCD     0                         ; Reserved
  63                 DCD     0                         ; Reserved
  64                 DCD     0                         ; Reserved
  65                 DCD     0                         ; Reserved
  66                 DCD     0                         ; Reserved
  67                 DCD     SVC_Handler               ; SVCall Handler
  68                 DCD     0                         ; Reserved
  69                 DCD     0                         ; Reserved
  70                 DCD     PendSV_Handler            ; PendSV Handler
  71                 DCD     SysTick_Handler           ; SysTick Handler
  72
  73                 ; External Interrupts
  74                 DCD     SPI0_IRQHandler             ; SPI0 controller
  75                 DCD     SPI1_IRQHandler             ; SPI1 controller
  76                 DCD     0                           ; Reserved
  77                 DCD     UART0_IRQHandler            ; UART0
  78                 DCD     UART1_IRQHandler            ; UART1
  79                 DCD     UART2_IRQHandler            ; UART2
  80                 DCD     0                           ; Reserved
  81                 DCD     I2C1_IRQHandler             ; I2C1 controller
  82                 DCD     I2C0_IRQHandler             ; I2C0 controller
  83                 DCD     SCT_IRQHandler              ; Smart Counter Timer
  84                 DCD     MRT_IRQHandler              ; Multi-Rate Timer
  85                 DCD     CMP_IRQHandler              ; Comparator
  86                 DCD     WDT_IRQHandler              ; PIO1 (0:11)
  87                 DCD     BOD_IRQHandler              ; Brown Out Detect
  88                 DCD     Flash_IRQHandler            ; Flash interrupt
  89                 DCD     WKT_IRQHandler              ; Wakeup timer
  90                 DCD     ADC_SEQA_IRQHandler         ; ADC sequence A completion
  91                 DCD     ADC_SEQB_IRQHandler         ; ADC sequence B completion
  92                 DCD     ADC_THCMP_IRQHandler        ; ADC threshold compare
  93                 DCD     ADC_OVR_IRQHandler          ; ADC overrun
  94                 DCD     DMA__RQHandler              ; DMA interrupt
  95                 DCD     I2C2_IRQHandler             ; I2C2 controller
  96                 DCD     I2C3_IRQHandler             ; I2C3 controller
  97                 DCD     0                           ; Reserved
  98                 DCD     PININT0_IRQHandler          ; PIO INT0
  99                 DCD     PININT1_IRQHandler          ; PIO INT1
 100                 DCD     PININT2_IRQHandler          ; PIO INT2
 101                 DCD     PININT3_IRQHandler          ; PIO INT3
 102                 DCD     PININT4_IRQHandler          ; PIO INT4
 103                 DCD     PININT5_IRQHandler          ; PIO INT5
 104                 DCD     PININT6_IRQHandler          ; PIO INT6
 105                 DCD     PININT7_IRQHandler          ; PIO INT7
 106
 107
 108                 IF      :LNOT::DEF:NO_CRP
 109                 AREA    |.ARM.__at_0x02FC|, CODE, READONLY
 110 CRP_Key         DCD     0xFFFFFFFF
 111                 ENDIF
 112
 113
 114                 AREA    |.text|, CODE, READONLY
 115
 116 ; Reset Handler
 117
 118 Reset_Handler   PROC
 119                 EXPORT  Reset_Handler             [WEAK]
 120                 IMPORT  SystemInit
 121                 IMPORT  __main
 122                 LDR     R0, =SystemInit
 123                 BLX     R0
 124                 LDR     R0, =__main
 125                 BX      R0
 126                 ENDP
 127
 128
 129 ; Dummy Exception Handlers (infinite loops which can be modified)
 130
 131 HardFault_Handler\
 132                 PROC
 133                 EXPORT  HardFault_Handler         [WEAK]
 134                 B       .
 135                 ENDP
 136 SVC_Handler     PROC
 137                 EXPORT  SVC_Handler               [WEAK]
 138                 B       .
 139                 ENDP
 140 PendSV_Handler  PROC
 141                 EXPORT  PendSV_Handler            [WEAK]
 142                 B       .
 143                 ENDP
 144 SysTick_Handler PROC
 145                 EXPORT  SysTick_Handler           [WEAK]
 146                 B       .
 147                 ENDP
 148
 149 Default_Handler PROC
 150
 151                 EXPORT  NMI_Handler               [WEAK]
 152                 EXPORT  SPI0_IRQHandler           [WEAK]
 153                 EXPORT  SPI1_IRQHandler           [WEAK]
 154                 EXPORT  UART0_IRQHandler          [WEAK]
 155                 EXPORT  UART1_IRQHandler          [WEAK]
 156                 EXPORT  UART2_IRQHandler          [WEAK]
 157                 EXPORT  I2C1_IRQHandler           [WEAK]
 158                 EXPORT  I2C0_IRQHandler           [WEAK]
 159                 EXPORT  SCT_IRQHandler            [WEAK]
 160                 EXPORT  MRT_IRQHandler            [WEAK]
 161                 EXPORT  CMP_IRQHandler            [WEAK]
 162                 EXPORT  WDT_IRQHandler            [WEAK]
 163                 EXPORT  BOD_IRQHandler            [WEAK]
 164                 EXPORT  Flash_IRQHandler          [WEAK]
 165                 EXPORT  WKT_IRQHandler            [WEAK]
 166                 EXPORT  ADC_SEQA_IRQHandler       [WEAK]
 167                 EXPORT  ADC_SEQB_IRQHandler       [WEAK]
 168                 EXPORT  ADC_THCMP_IRQHandler      [WEAK]
 169                 EXPORT  ADC_OVR_IRQHandler        [WEAK]
 170                 EXPORT  DMA__RQHandler            [WEAK]
 171                 EXPORT  I2C2_IRQHandler           [WEAK]
 172                 EXPORT  I2C3_IRQHandler           [WEAK]
 173                 EXPORT  PININT0_IRQHandler        [WEAK]
 174                 EXPORT  PININT1_IRQHandler        [WEAK]
 175                 EXPORT  PININT2_IRQHandler        [WEAK]
 176                 EXPORT  PININT3_IRQHandler        [WEAK]
 177                 EXPORT  PININT4_IRQHandler        [WEAK]
 178                 EXPORT  PININT5_IRQHandler        [WEAK]
 179                 EXPORT  PININT6_IRQHandler        [WEAK]
 180                 EXPORT  PININT7_IRQHandler        [WEAK]
 181
 182 NMI_Handler
 183 SPI0_IRQHandler
 184 SPI1_IRQHandler
 185 UART0_IRQHandler
 186 UART1_IRQHandler
 187 UART2_IRQHandler
 188 I2C1_IRQHandler
 189 I2C0_IRQHandler
 190 SCT_IRQHandler
 191 MRT_IRQHandler
 192 CMP_IRQHandler
 193 WDT_IRQHandler
 194 BOD_IRQHandler
 195 Flash_IRQHandler
 196 WKT_IRQHandler
 197 ADC_SEQA_IRQHandler
 198 ADC_SEQB_IRQHandler
 199 ADC_THCMP_IRQHandler
 200 ADC_OVR_IRQHandler
 201 DMA__RQHandler
 202 I2C2_IRQHandler
 203 I2C3_IRQHandler
 204 PININT0_IRQHandler
 205 PININT1_IRQHandler
 206 PININT2_IRQHandler
 207 PININT3_IRQHandler
 208 PININT4_IRQHandler
 209 PININT5_IRQHandler
 210 PININT6_IRQHandler
 211 PININT7_IRQHandler
 212
 213                 B       .
 214
 215                 ENDP
 216
 217                 ALIGN
 218                 END