tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/system_LPC23xx.c

   1 /* mbed Microcontroller Library
   2  * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
   3  *
   4  * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
   5  */
   6
   7 #include <stdint.h>
   8 #include "LPC23xx.h"
   9
  10 #define CLOCK_SETUP           1
  11 #define SCS_Val               0x00000020
  12 #define CLKSRCSEL_Val         0x00000001
  13
  14 #define PLL0_SETUP            1
  15 #define PLL0CFG_Val           0x00000013
  16 #define CCLKCFG_Val           0x00000007
  17 #define USBCLKCFG_Val         0x00000009
  18 #define PCLKSEL0_Val          0x00000000
  19 #define PCLKSEL1_Val          0x00000000
  20 #define PCONP_Val             0x042887DE
  21 #define CLKOUTCFG_Val         0x00000000
  22 #define MAMCR_Val             0x00000001  // there is a bug in the MAM so it should never be fully enabled (only disabled or partially enabled)
  23 #define MAMTIM_Val            0x00000004
  24
  25 /*----------------------------------------------------------------------------
  26   DEFINES
  27  *----------------------------------------------------------------------------*/
  28
  29 #define XTAL        (12000000UL)        /* Oscillator frequency               */
  30 #define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
  31 #define RTC_CLK     (   32000UL)        /* RTC oscillator frequency           */
  32 #define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */
  33
  34 /* F_cco0 = (2 * M * F_in) / N  */
  35 #define __M               (((PLL0CFG_Val      ) & 0x7FFF) + 1)
  36 #define __N               (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
  37 #define __FCCO(__F_IN)    ((2 * __M * __F_IN) / __N)
  38 #define __CCLK_DIV        (((CCLKCFG_Val      ) & 0x00FF) + 1)
  39
  40 /* Determine core clock frequency according to settings */
  41  #if (PLL0_SETUP)
  42     #if   ((CLKSRCSEL_Val & 0x03) == 1)
  43         #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
  44     #elif ((CLKSRCSEL_Val & 0x03) == 2)
  45         #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
  46     #else
  47         #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
  48     #endif
  49  #endif
  50
  51
  52 /*----------------------------------------------------------------------------
  53   Clock Variable definitions
  54  *----------------------------------------------------------------------------*/
  55 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
  56
  57 /*----------------------------------------------------------------------------
  58   Clock functions
  59  *----------------------------------------------------------------------------*/
  60 void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
  61 {
  62   /* Determine clock frequency according to clock register values             */
  63   if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
  64     switch (LPC_SC->CLKSRCSEL & 0x03) {
  65       case 0:                                /* Int. RC oscillator => PLL0    */
  66       case 3:                                /* Reserved, default to Int. RC  */
  67         SystemCoreClock = (IRC_OSC *
  68                           (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
  69                           (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1))   /
  70                           ((LPC_SC->CCLKCFG & 0xFF)+ 1));
  71         break;
  72       case 1:                                /* Main oscillator => PLL0       */
  73         SystemCoreClock = (OSC_CLK *
  74                           (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
  75                           (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1))   /
  76                           ((LPC_SC->CCLKCFG & 0xFF)+ 1));
  77         break;
  78       case 2:                                /* RTC oscillator => PLL0        */
  79         SystemCoreClock = (RTC_CLK *
  80                           (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
  81                           (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1))   /
  82                           ((LPC_SC->CCLKCFG & 0xFF)+ 1));
  83         break;
  84     }
  85   } else {
  86     switch (LPC_SC->CLKSRCSEL & 0x03) {
  87       case 0:                                /* Int. RC oscillator => PLL0    */
  88       case 3:                                /* Reserved, default to Int. RC  */
  89         SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
  90         break;
  91       case 1:                                /* Main oscillator => PLL0       */
  92         SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
  93         break;
  94       case 2:                                /* RTC oscillator => PLL0        */
  95         SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
  96         break;
  97     }
  98   }
  99 }
 100
 101 /**
 102  * Initialize the system
 103  *
 104  * @param  none
 105  * @return none
 106  *
 107  * @brief  Setup the microcontroller system.
 108  *         Initialize the System and update the SystemFrequency variable.
 109  */
 110 void SystemInit (void)
 111 {
 112 #if (CLOCK_SETUP)                       /* Clock Setup                        */
 113   LPC_SC->SCS       = SCS_Val;
 114   if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */
 115     while ((LPC_SC->SCS & (1 << 6)) == 0);  /* Wait for Oscillator to be ready    */
 116   }
 117
 118   LPC_SC->CCLKCFG   = CCLKCFG_Val;          /* Setup Clock Divider                */
 119
 120 #if (PLL0_SETUP)
 121   LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;        /* Select Clock Source for PLL0       */
 122   LPC_SC->PLL0CFG   = PLL0CFG_Val;
 123   LPC_SC->PLL0CON   = 0x01;                 /* PLL0 Enable                        */
 124   LPC_SC->PLL0FEED  = 0xAA;
 125   LPC_SC->PLL0FEED  = 0x55;
 126   while (!(LPC_SC->PLL0STAT & (1 << 26)));  /* Wait for PLOCK0                    */
 127
 128   LPC_SC->PLL0CON   = 0x03;                 /* PLL0 Enable & Connect              */
 129   LPC_SC->PLL0FEED  = 0xAA;
 130   LPC_SC->PLL0FEED  = 0x55;
 131 #endif
 132
 133   LPC_SC->USBCLKCFG = USBCLKCFG_Val;        /* Setup USB Clock Divider            */
 134 #endif
 135
 136   LPC_SC->PCLKSEL0  = PCLKSEL0_Val;         /* Peripheral Clock Selection         */
 137   LPC_SC->PCLKSEL1  = PCLKSEL1_Val;
 138
 139   LPC_SC->PCONP     = PCONP_Val;            /* Power Control for Peripherals      */
 140
 141   // Setup MAM
 142   LPC_SC->MAMTIM      = MAMTIM_Val;
 143   LPC_SC->MAMCR       = MAMCR_Val;
 144 }