tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_IAR/TARGET_LPC11U24_301/startup_LPC11xx.s

   1 /**************************************************
   2  *
   3  * Part one of the system initialization code, contains low-level
   4  * initialization, plain thumb variant.
   5  *
   6  * Copyright 2012 IAR Systems. All rights reserved.
   7  *
   8  * $Revision: 28 $
   9  *
  10  **************************************************/
  11
  12 ;
  13 ; The modules in this file are included in the libraries, and may be replaced
  14 ; by any user-defined modules that define the PUBLIC symbol _program_start or
  15 ; a user defined start symbol.
  16 ; To override the cstartup defined in the library, simply add your modified
  17 ; version to the workbench project.
  18 ;
  19 ; The vector table is normally located at address 0.
  20 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
  21 ; The name "__vector_table" has special meaning for C-SPY:
  22 ; it is where the SP start value is found, and the NVIC vector
  23 ; table register (VTOR) is initialized to this address if != 0.
  24 ;
  25 ; Cortex-M version
  26 ;
  27
  28         MODULE  ?cstartup
  29
  30         ;; Forward declaration of sections.
  31         SECTION CSTACK:DATA:NOROOT(3)
  32
  33         SECTION .intvec:CODE:NOROOT(2)
  34
  35         EXTERN  __iar_program_start
  36         EXTERN  SystemInit
  37
  38         PUBLIC  __vector_table
  39         PUBLIC  __vector_table_0x1c
  40         DATA
  41
  42
  43 __vector_table
  44                 DCD     sfe(CSTACK)               ; Top of Stack
  45                 DCD     Reset_Handler       ; Reset Handler
  46                 DCD     NMI_Handler               ; NMI Handler
  47                 DCD     HardFault_Handler         ; Hard Fault Handler
  48                 DCD     MemManage_Handler         ; MPU Fault Handler
  49                 DCD     BusFault_Handler          ; Bus Fault Handler
  50                 DCD     UsageFault_Handler        ; Usage Fault Handler
  51 __vector_table_0x1c
  52                 DCD     0                         ; Reserved
  53                 DCD     0                         ; Reserved
  54                 DCD     0                         ; Reserved
  55                 DCD     0                         ; Reserved
  56                 DCD     SVC_Handler               ; SVCall Handler
  57                 DCD     DebugMon_Handler          ; Debug Monitor Handler
  58                 DCD     0                         ; Reserved
  59                 DCD     PendSV_Handler            ; PendSV Handler
  60                 DCD     SysTick_Handler           ; SysTick Handler
  61
  62                 ; External Interrupts
  63                 DCD     FLEX_INT0_IRQHandler      ; All GPIO pin can be routed to FLEX_INTx
  64                 DCD     FLEX_INT1_IRQHandler
  65                 DCD     FLEX_INT2_IRQHandler
  66                 DCD     FLEX_INT3_IRQHandler
  67                 DCD     FLEX_INT4_IRQHandler
  68                 DCD     FLEX_INT5_IRQHandler
  69                 DCD     FLEX_INT6_IRQHandler
  70                 DCD     FLEX_INT7_IRQHandler
  71                 DCD     GINT0_IRQHandler
  72                 DCD     GINT1_IRQHandler          ; PIO0 (0:7)
  73                 DCD     Reserved_IRQHandler       ; Reserved
  74                 DCD     Reserved_IRQHandler
  75                 DCD     Reserved_IRQHandler
  76                 DCD     Reserved_IRQHandler
  77                 DCD     SSP1_IRQHandler           ; SSP1
  78                 DCD     I2C_IRQHandler            ; I2C
  79                 DCD     TIMER16_0_IRQHandler      ; 16-bit Timer0
  80                 DCD     TIMER16_1_IRQHandler      ; 16-bit Timer1
  81                 DCD     TIMER32_0_IRQHandler      ; 32-bit Timer0
  82                 DCD     TIMER32_1_IRQHandler      ; 32-bit Timer1
  83                 DCD     SSP0_IRQHandler           ; SSP0
  84                 DCD     UART_IRQHandler           ; UART
  85                 DCD     USB_IRQHandler            ; USB IRQ
  86                 DCD     USB_FIQHandler            ; USB FIQ
  87                 DCD     ADC_IRQHandler            ; A/D Converter
  88                 DCD     WDT_IRQHandler            ; Watchdog timer
  89                 DCD     BOD_IRQHandler            ; Brown Out Detect
  90                 DCD     FMC_IRQHandler            ; IP2111 Flash Memory Controller
  91                 DCD     Reserved_IRQHandler       ; Reserved
  92                 DCD     Reserved_IRQHandler       ; Reserved
  93                 DCD     USBWakeup_IRQHandler      ; USB wake up
  94                 DCD     Reserved_IRQHandler       ; Reserved
  95
  96         ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
  97
  98
  99                 DCD     0xFFFFFFFF                ; Datafill
 100                 DCD     0xFFFFFFFF                ; Datafill
 101                 DCD     0xFFFFFFFF                ; Datafill
 102                 DCD     0xFFFFFFFF                ; Datafill
 103                 DCD     0xFFFFFFFF                ; Datafill
 104                 DCD     0xFFFFFFFF                ; Datafill
 105                 DCD     0xFFFFFFFF                ; Datafill
 106                 DCD     0xFFFFFFFF                ; Datafill
 107                 DCD     0xFFFFFFFF                ; Datafill
 108                 DCD     0xFFFFFFFF                ; Datafill
 109
 110                 DCD     0xFFFFFFFF                ; Datafill
 111                 DCD     0xFFFFFFFF                ; Datafill
 112                 DCD     0xFFFFFFFF                ; Datafill
 113                 DCD     0xFFFFFFFF                ; Datafill
 114                 DCD     0xFFFFFFFF                ; Datafill
 115                 DCD     0xFFFFFFFF                ; Datafill
 116                 DCD     0xFFFFFFFF                ; Datafill
 117                 DCD     0xFFFFFFFF                ; Datafill
 118                 DCD     0xFFFFFFFF                ; Datafill
 119                 DCD     0xFFFFFFFF                ; Datafill
 120
 121                 DCD     0xFFFFFFFF                ; Datafill
 122                 DCD     0xFFFFFFFF                ; Datafill
 123                 DCD     0xFFFFFFFF                ; Datafill
 124                 DCD     0xFFFFFFFF                ; Datafill
 125                 DCD     0xFFFFFFFF                ; Datafill
 126                 DCD     0xFFFFFFFF                ; Datafill
 127                 DCD     0xFFFFFFFF                ; Datafill
 128                 DCD     0xFFFFFFFF                ; Datafill
 129                 DCD     0xFFFFFFFF                ; Datafill
 130                 DCD     0xFFFFFFFF                ; Datafill
 131
 132                 DCD     0xFFFFFFFF                ; Datafill
 133                 DCD     0xFFFFFFFF                ; Datafill
 134                 DCD     0xFFFFFFFF                ; Datafill
 135                 DCD     0xFFFFFFFF                ; Datafill
 136                 DCD     0xFFFFFFFF                ; Datafill
 137                 DCD     0xFFFFFFFF                ; Datafill
 138                 DCD     0xFFFFFFFF                ; Datafill
 139                 DCD     0xFFFFFFFF                ; Datafill
 140                 DCD     0xFFFFFFFF                ; Datafill
 141                 DCD     0xFFFFFFFF                ; Datafill
 142
 143                 DCD     0xFFFFFFFF                ; Datafill
 144                 DCD     0xFFFFFFFF                ; Datafill
 145                 DCD     0xFFFFFFFF                ; Datafill
 146                 DCD     0xFFFFFFFF                ; Datafill
 147                 DCD     0xFFFFFFFF                ; Datafill
 148                 DCD     0xFFFFFFFF                ; Datafill
 149                 DCD     0xFFFFFFFF                ; Datafill
 150                 DCD     0xFFFFFFFF                ; Datafill
 151                 DCD     0xFFFFFFFF                ; Datafill
 152                 DCD     0xFFFFFFFF                ; Datafill
 153
 154                 DCD     0xFFFFFFFF                ; Datafill
 155                 DCD     0xFFFFFFFF                ; Datafill
 156                 DCD     0xFFFFFFFF                ; Datafill
 157                 DCD     0xFFFFFFFF                ; Datafill
 158                 DCD     0xFFFFFFFF                ; Datafill
 159                 DCD     0xFFFFFFFF                ; Datafill
 160                 DCD     0xFFFFFFFF                ; Datafill
 161                 DCD     0xFFFFFFFF                ; Datafill
 162                 DCD     0xFFFFFFFF                ; Datafill
 163                 DCD     0xFFFFFFFF                ; Datafill
 164
 165                 DCD     0xFFFFFFFF                ; Datafill
 166                 DCD     0xFFFFFFFF                ; Datafill
 167                 DCD     0xFFFFFFFF                ; Datafill
 168                 DCD     0xFFFFFFFF                ; Datafill
 169                 DCD     0xFFFFFFFF                ; Datafill
 170                 DCD     0xFFFFFFFF                ; Datafill
 171                 DCD     0xFFFFFFFF                ; Datafill
 172                 DCD     0xFFFFFFFF                ; Datafill
 173                 DCD     0xFFFFFFFF                ; Datafill
 174                 DCD     0xFFFFFFFF                ; Datafill
 175
 176                 DCD     0xFFFFFFFF                ; Datafill
 177                 DCD     0xFFFFFFFF                ; Datafill
 178                 DCD     0xFFFFFFFF                ; Datafill
 179                 DCD     0xFFFFFFFF                ; Datafill
 180                 DCD     0xFFFFFFFF                ; Datafill
 181                 DCD     0xFFFFFFFF                ; Datafill
 182                 DCD     0xFFFFFFFF                ; Datafill
 183                 DCD     0xFFFFFFFF                ; Datafill
 184                 DCD     0xFFFFFFFF                ; Datafill
 185                 DCD     0xFFFFFFFF                ; Datafill
 186 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 187 ;;
 188 ;; Default interrupt handlers.
 189 ;;
 190         THUMB
 191         PUBWEAK Reset_Handler
 192         SECTION .text:CODE:NOROOT:REORDER(2)
 193 Reset_Handler
 194         LDR     R0, =SystemInit
 195         BLX     R0
 196         LDR     R0, =__iar_program_start
 197         BX      R0
 198
 199         PUBWEAK NMI_Handler
 200         PUBWEAK HardFault_Handler
 201         PUBWEAK MemManage_Handler
 202         PUBWEAK BusFault_Handler
 203         PUBWEAK UsageFault_Handler
 204         PUBWEAK SVC_Handler
 205         PUBWEAK DebugMon_Handler
 206         PUBWEAK PendSV_Handler
 207         PUBWEAK SysTick_Handler
 208         PUBWEAK FLEX_INT0_IRQHandler
 209         PUBWEAK FLEX_INT1_IRQHandler
 210         PUBWEAK FLEX_INT2_IRQHandler
 211         PUBWEAK FLEX_INT3_IRQHandler
 212         PUBWEAK FLEX_INT4_IRQHandler
 213         PUBWEAK FLEX_INT5_IRQHandler
 214         PUBWEAK FLEX_INT6_IRQHandler
 215         PUBWEAK FLEX_INT7_IRQHandler
 216         PUBWEAK GINT0_IRQHandler
 217         PUBWEAK GINT1_IRQHandler
 218         PUBWEAK SSP1_IRQHandler
 219         PUBWEAK I2C_IRQHandler
 220         PUBWEAK TIMER16_0_IRQHandler
 221         PUBWEAK TIMER16_1_IRQHandler
 222         PUBWEAK TIMER32_0_IRQHandler
 223         PUBWEAK TIMER32_1_IRQHandler
 224         PUBWEAK SSP0_IRQHandler
 225         PUBWEAK UART_IRQHandler
 226         PUBWEAK USB_IRQHandler
 227         PUBWEAK USB_FIQHandler
 228         PUBWEAK ADC_IRQHandler
 229         PUBWEAK WDT_IRQHandler
 230         PUBWEAK BOD_IRQHandler
 231         PUBWEAK FMC_IRQHandler
 232         PUBWEAK USBWakeup_IRQHandler
 233         PUBWEAK Reserved_IRQHandler
 234
 235       SECTION .text:CODE:REORDER:NOROOT(1)
 236       THUMB
 237 NMI_Handler:
 238         B .
 239 HardFault_Handler:
 240         B .
 241 MemManage_Handler:
 242         B .
 243 BusFault_Handler:
 244         B .
 245 UsageFault_Handler:
 246         B .
 247 SVC_Handler:
 248         B .
 249 DebugMon_Handler:
 250         B .
 251 PendSV_Handler:
 252         B .
 253 SysTick_Handler:
 254         B .
 255 FLEX_INT0_IRQHandler:
 256         B .
 257 FLEX_INT1_IRQHandler:
 258         B .
 259 FLEX_INT2_IRQHandler:
 260         B .
 261 FLEX_INT3_IRQHandler:
 262         B .
 263 FLEX_INT4_IRQHandler:
 264         B .
 265 FLEX_INT5_IRQHandler:
 266         B .
 267 FLEX_INT6_IRQHandler:
 268         B .
 269 FLEX_INT7_IRQHandler:
 270         B .
 271 GINT0_IRQHandler:
 272         B .
 273 GINT1_IRQHandler:
 274         B .
 275 SSP1_IRQHandler:
 276         B .
 277 I2C_IRQHandler:
 278         B .
 279 TIMER16_0_IRQHandler:
 280         B .
 281 TIMER16_1_IRQHandler:
 282         B .
 283 TIMER32_0_IRQHandler:
 284         B .
 285 TIMER32_1_IRQHandler:
 286         B .
 287 SSP0_IRQHandler:
 288         B .
 289 UART_IRQHandler:
 290         B .
 291 USB_IRQHandler:
 292         B .
 293 USB_FIQHandler:
 294         B .
 295 ADC_IRQHandler:
 296         B .
 297 WDT_IRQHandler:
 298         B .
 299 BOD_IRQHandler:
 300         B .
 301 FMC_IRQHandler:
 302         B .
 303 USBWakeup_IRQHandler:
 304         B .
 305 Reserved_IRQHandler:
 306         B .
 307 Default_Handler:
 308         B .
 309
 310         SECTION .crp:CODE:ROOT(2)
 311         DATA
 312 /* Code Read Protection
 313 NO_ISP  0x4E697370 -  Prevents sampling of pin PIO0_1 for entering ISP mode
 314 CRP1    0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
 315                    - Copy RAM to flash command can not write to Sector 0.
 316                    - Erase command can erase Sector 0 only when all sectors
 317                      are selected for erase.
 318                    - Compare command is disabled.
 319                    - Read Memory command is disabled.
 320 CRP2    0x87654321 - Read Memory is disabled.
 321                    - Write to RAM is disabled.
 322                    - "Go" command is disabled.
 323                    - Copy RAM to flash is disabled.
 324                    - Compare is disabled.
 325 CRP3    0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
 326                      by pulling PIO0_1 LOW is disabled if a valid user code is
 327                      present in flash sector 0.
 328 Caution: If CRP3 is selected, no future factory testing can be
 329 performed on the device.
 330 */
 331         DCD     0xFFFFFFFF
 332
 333         END