2 /****************************************************************************************************//**
5 * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
9 * @date 22. October 2013
11 * @note Generated with SVDConv V2.81a
12 * from CMSIS SVD File 'LPC11U6x.svd' Version 0.4,
15 *******************************************************************************************************/
19 /** @addtogroup (null)
23 /** @addtogroup LPC11U6x
35 /* ------------------------- Interrupt Number Definition ------------------------ */
38 /* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
39 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
40 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
41 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
45 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
48 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
49 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
50 /* --------------------- LPC11U6x Specific Interrupt Numbers -------------------- */
51 PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
52 PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
53 PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
54 PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
55 PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
56 PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
57 PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
58 PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
59 GINT0_IRQn = 8, /*!< 8 GINT0 */
60 GINT1_IRQn = 9, /*!< 9 GINT1 */
61 I2C1_IRQn = 10, /*!< 10 I2C1 */
62 USART1_4_IRQn = 11, /*!< 11 USART1_4 */
63 USART2_3_IRQn = 12, /*!< 12 USART2_3 */
64 SCT0_1_IRQn = 13, /*!< 13 SCT0_1 */
65 SSP1_IRQn = 14, /*!< 14 SSP1 */
66 I2C0_IRQn = 15, /*!< 15 I2C0 */
67 CT16B0_IRQn = 16, /*!< 16 CT16B0 */
68 CT16B1_IRQn = 17, /*!< 17 CT16B1 */
69 CT32B0_IRQn = 18, /*!< 18 CT32B0 */
70 CT32B1_IRQn = 19, /*!< 19 CT32B1 */
71 SSP0_IRQn = 20, /*!< 20 SSP0 */
72 USART0_IRQn = 21, /*!< 21 USART0 */
73 USB_IRQn = 22, /*!< 22 USB */
74 USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
75 ADC_A_IRQn = 24, /*!< 24 ADC_A */
76 RTC_IRQn = 25, /*!< 25 RTC */
77 BOD_WDT_IRQn = 26, /*!< 26 BOD_WDT */
78 FLASH_IRQn = 27, /*!< 27 FLASH */
79 DMA_IRQn = 28, /*!< 28 DMA */
80 ADC_B_IRQn = 29, /*!< 29 ADC_B */
81 USBWAKEUP_IRQn = 30 /*!< 30 USBWAKEUP */
85 /** @addtogroup Configuration_of_CMSIS
90 /* ================================================================================ */
91 /* ================ Processor and Core Peripheral Section ================ */
92 /* ================================================================================ */
94 /* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
95 #define __CM0PLUS_REV 0x0000 /*!< Cortex-M0PLUS Core Revision */
96 #define __MPU_PRESENT 0 /*!< MPU present or not */
97 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
98 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
99 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
100 /** @} */ /* End of group Configuration_of_CMSIS */
102 #include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */
103 #include "system_LPC11U6x.h" /*!< LPC11U6x System */
106 /* ================================================================================ */
107 /* ================ Device Specific Peripheral Section ================ */
108 /* ================================================================================ */
111 /** @addtogroup Device_Peripheral_Registers
116 /* ------------------- Start of section using anonymous unions ------------------ */
117 #if defined(__CC_ARM)
120 #elif defined(__ICCARM__)
121 #pragma language=extended
122 #elif defined(__GNUC__)
123 /* anonymous unions are enabled by default */
124 #elif defined(__TMS470__)
125 /* anonymous unions are enabled by default */
126 #elif defined(__TASKING__)
129 #warning Not supported compiler type
134 /* ================================================================================ */
135 /* ================ I2C0 ================ */
136 /* ================================================================================ */
140 * @brief I2C-bus controller (I2C0)
143 typedef struct { /*!< I2C0 Structure */
144 __IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of
145 this register, the corresponding bit in the I2C control register
146 is set. Writing a zero has no effect on the corresponding bit
147 in the I2C control register. */
148 __I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides
149 detailed status codes that allow software to determine the next
151 __IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data
152 to be transmitted is written to this register. During master
153 or slave receive mode, data that has been received may be read
154 from this register. */
155 __IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address
156 for operation of the I2C interface in slave mode, and is not
157 used in master mode. The least significant bit determines whether
158 a slave responds to the General Call address. */
159 __IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high
160 time of the I2C clock. */
161 __IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time
162 of the I2C clock. I2nSCLL and I2nSCLH together determine the
163 clock frequency generated by an I2C master and certain times
164 used in slave mode. */
165 __O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of
166 this register, the corresponding bit in the I2C control register
167 is cleared. Writing a zero has no effect on the corresponding
168 bit in the I2C control register. */
169 __IO uint32_t MMCTRL; /*!< Monitor mode control register. */
170 __IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address
171 for operation of the I2C interface in slave mode, and is not
172 used in master mode. The least significant bit determines whether
173 a slave responds to the General Call address. */
174 __IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address
175 for operation of the I2C interface in slave mode, and is not
176 used in master mode. The least significant bit determines whether
177 a slave responds to the General Call address. */
178 __IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address
179 for operation of the I2C interface in slave mode, and is not
180 used in master mode. The least significant bit determines whether
181 a slave responds to the General Call address. */
182 __I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the I2DAT
183 shift register will be transferred to the DATA_BUFFER automatically
184 after every nine bits (8 bits of data plus ACK or NACK) has
185 been received on the bus. */
186 __IO uint32_t MASK0; /*!< I2C Slave address mask register. This mask register is associated
187 with I2ADR0 to determine an address match. The mask register
188 has no effect when comparing to the General Call address (0000000). */
189 __IO uint32_t MASK1; /*!< I2C Slave address mask register. This mask register is associated
190 with I2ADR0 to determine an address match. The mask register
191 has no effect when comparing to the General Call address (0000000). */
192 __IO uint32_t MASK2; /*!< I2C Slave address mask register. This mask register is associated
193 with I2ADR0 to determine an address match. The mask register
194 has no effect when comparing to the General Call address (0000000). */
195 __IO uint32_t MASK3; /*!< I2C Slave address mask register. This mask register is associated
196 with I2ADR0 to determine an address match. The mask register
197 has no effect when comparing to the General Call address (0000000). */
201 /* ================================================================================ */
202 /* ================ WWDT ================ */
203 /* ================================================================================ */
207 * @brief Windowed Watchdog Timer (WWDT) (WWDT)
210 typedef struct { /*!< WWDT Structure */
211 __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
212 and status of the Watchdog Timer. */
213 __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
214 the time-out value. */
215 __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
216 to this register reloads the Watchdog timer with the value contained
218 __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
219 the current value of the Watchdog timer. */
220 __IO uint32_t CLKSEL; /*!< Watchdog clock select register. */
221 __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */
222 __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */
226 /* ================================================================================ */
227 /* ================ USART0 ================ */
228 /* ================================================================================ */
232 * @brief USART0 (USART0)
235 typedef struct { /*!< USART0 Structure */
238 __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor
239 value. The full divisor is used to generate a baud rate from
240 the fractional rate divider. (DLAB=1) */
241 __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted
242 is written here. (DLAB=0) */
243 __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character
244 to be read. (DLAB=0) */
248 __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable
249 bits for the 7 potential USART interrupts. (DLAB=0) */
250 __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor
251 value. The full divisor is used to generate a baud rate from
252 the fractional rate divider. (DLAB=1) */
256 __O uint32_t FCR; /*!< FIFO Control Register. Controls USART FIFO usage and modes. */
257 __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
259 __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting
260 and break generation. */
261 __IO uint32_t MCR; /*!< Modem Control Register. */
262 __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive
263 status, including line errors. */
264 __I uint32_t MSR; /*!< Modem Status Register. */
265 __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
266 __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud
268 __IO uint32_t ICR; /*!< IrDA Control Register. Enables and configures the IrDA (remote
270 __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the
271 baud rate divider. */
272 __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during
274 __IO uint32_t TER; /*!< Transmit Enable Register. Turns off USART transmitter for use
275 with software flow control. */
276 __I uint32_t RESERVED0[3];
277 __IO uint32_t HDEN; /*!< Half duplex enable register. */
278 __I uint32_t RESERVED1;
279 __IO uint32_t SCICTRL; /*!< Smart Card Interface Control register. Enables and configures
280 the Smart Card Interface feature. */
281 __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various
282 aspects of RS-485/EIA-485 modes. */
283 __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value
284 for RS-485/EIA-485 mode. */
285 __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
286 __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. */
290 /* ================================================================================ */
291 /* ================ CT16B0 ================ */
292 /* ================================================================================ */
296 * @brief 16-bit counter/timers CT16B0 (CT16B0)
299 typedef struct { /*!< CT16B0 Structure */
300 __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
301 The IR can be read to identify which of eight possible interrupt
302 sources are pending. */
303 __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
304 Counter functions. The Timer Counter can be disabled or reset
306 __IO uint32_t TC; /*!< Timer Counter. The 16-bit TC is incremented every PR+1 cycles
307 of PCLK. The TC is controlled through the TCR. */
308 __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
309 to this value, the next clock increments the TC and clears the
311 __IO uint32_t PC; /*!< Prescale Counter. The 16-bit PC is a counter which is incremented
312 to the value stored in PR. When the value in PR is reached,
313 the TC is incremented and the PC is cleared. The PC is observable
314 and controllable through the bus interface. */
315 __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
316 is generated and if the TC is reset when a Match occurs. */
317 __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
318 TC, stop both the TC and PC, and/or generate an interrupt every
319 time MR0 matches the TC. */
320 __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
321 TC, stop both the TC and PC, and/or generate an interrupt every
322 time MR0 matches the TC. */
323 __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
324 TC, stop both the TC and PC, and/or generate an interrupt every
325 time MR0 matches the TC. */
326 __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
327 TC, stop both the TC and PC, and/or generate an interrupt every
328 time MR0 matches the TC. */
329 __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
330 capture inputs are used to load the Capture Registers and whether
331 or not an interrupt is generated when a capture takes place. */
332 __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
333 is an event on the CAP input. */
334 __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
335 is an event on the CAP input. */
336 __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
337 is an event on the CAP input. */
338 __I uint32_t RESERVED0;
339 __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
340 and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
341 __I uint32_t RESERVED1[12];
342 __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
343 mode, and in Counter mode selects the signal and edge(s) for
345 __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
346 match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
350 /* ================================================================================ */
351 /* ================ CT32B0 ================ */
352 /* ================================================================================ */
356 * @brief 32-bit counter/timers CT32B0 (CT32B0)
359 typedef struct { /*!< CT32B0 Structure */
360 __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
361 The IR can be read to identify which of eight possible interrupt
362 sources are pending. */
363 __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
364 Counter functions. The Timer Counter can be disabled or reset
366 __IO uint32_t TC; /*!< Timer Counter. The 32-bit TC is incremented every PR+1 cycles
367 of PCLK. The TC is controlled through the TCR. */
368 __IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
369 to this value, the next clock increments the TC and clears the
371 __IO uint32_t PC; /*!< Prescale Counter. The 32-bit PC is a counter which is incremented
372 to the value stored in PR. When the value in PR is reached,
373 the TC is incremented and the PC is cleared. The PC is observable
374 and controllable through the bus interface. */
375 __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
376 is generated and if the TC is reset when a Match occurs. */
377 __IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
378 TC, stop both the TC and PC, and/or generate an interrupt every
379 time MR0 matches the TC. */
380 __IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
381 TC, stop both the TC and PC, and/or generate an interrupt every
382 time MR0 matches the TC. */
383 __IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
384 TC, stop both the TC and PC, and/or generate an interrupt every
385 time MR0 matches the TC. */
386 __IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
387 TC, stop both the TC and PC, and/or generate an interrupt every
388 time MR0 matches the TC. */
389 __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
390 capture inputs are used to load the Capture Registers and whether
391 or not an interrupt is generated when a capture takes place. */
392 __I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
393 is an event on the CAP input. */
394 __I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
395 is an event on the CAP input. */
396 __I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
397 is an event on the CAP input. */
398 __I uint32_t RESERVED0;
399 __IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
400 and the external match pins CT32Bn_MAT[3:0]. */
401 __I uint32_t RESERVED1[12];
402 __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
403 mode, and in Counter mode selects the signal and edge(s) for
405 __IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
406 match pins CT32Bn_MAT[3:0]. */
410 /* ================================================================================ */
411 /* ================ ADC ================ */
412 /* ================================================================================ */
416 * @brief Product name title=Kylin UM Chapter title=Kylin12-bit Analog-to-Digital Converter (ADC) Modification date=5/13/2013 Major revision=0 Minor revision=1 (ADC)
419 typedef struct { /*!< ADC Structure */
420 __IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
421 bits for each sequence and the A/D power-down bit. */
422 __I uint32_t RESERVED0;
423 __IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
424 and channel selection for conversion sequence-A. Also specifies
425 interrupt mode for sequence-A. */
426 __IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
427 and channel selection for conversion sequence-B. Also specifies
428 interrupt mode for sequence-B. */
429 __IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
430 the result of the most recent A/D conversion performed under
432 __IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
433 the result of the most recent A/D conversion performed under
435 __I uint32_t RESERVED1[2];
436 __I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
437 of the most recent conversion completed on channel 0. */
438 __IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
439 level for automatic threshold comparison for any channels linked
440 to threshold pair 0. */
441 __IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
442 level for automatic threshold comparison for any channels linked
443 to threshold pair 1. */
444 __IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
445 level for automatic threshold comparison for any channels linked
446 to threshold pair 0. */
447 __IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
448 level for automatic threshold comparison for any channels linked
449 to threshold pair 1. */
450 __I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
451 threshold compare registers are to be used for each channel */
452 __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
453 bits that enable the sequence-A, sequence-B, threshold compare
454 and data overrun interrupts to be generated. */
455 __I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
456 and the individual component overrun and threshold-compare flags.
457 (The overrun bits replicate information stored in the result
459 __IO uint32_t TRM; /*!< ADC trim register. */
463 /* ================================================================================ */
464 /* ================ RTC ================ */
465 /* ================================================================================ */
469 * @brief Real-Time Clock (RTC) (RTC)
472 typedef struct { /*!< RTC Structure */
473 __IO uint32_t CTRL; /*!< RTC control register */
474 __IO uint32_t MATCH; /*!< RTC match register */
475 __IO uint32_t COUNT; /*!< RTC counter register */
476 __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */
480 /* ================================================================================ */
481 /* ================ DMATRIGMUX ================ */
482 /* ================================================================================ */
486 * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMATRIGMUX)
489 typedef struct { /*!< DMATRIGMUX Structure */
490 __IO uint32_t DMA_ITRIG_PINMUX[16]; /*!< Trigger input select register for DMA channel 0. */
491 } LPC_DMATRIGMUX_Type;
494 /* ================================================================================ */
495 /* ================ PMU ================ */
496 /* ================================================================================ */
500 * @brief Product name title=Kylin UM Chapter title=KylinPower Management Unit (PMU) Modification date=5/13/2013 Major revision=0 Minor revision=1 (PMU)
503 typedef struct { /*!< PMU Structure */
504 __IO uint32_t PCON; /*!< Power control register */
505 __IO uint32_t GPREG0; /*!< General purpose register 0 */
506 __IO uint32_t GPREG1; /*!< General purpose register 0 */
507 __IO uint32_t GPREG2; /*!< General purpose register 0 */
508 __IO uint32_t GPREG3; /*!< General purpose register 0 */
509 __IO uint32_t DPDCTRL; /*!< Deep power down control register */
513 /* ================================================================================ */
514 /* ================ FLASHCTRL ================ */
515 /* ================================================================================ */
519 * @brief Flash controller (FLASHCTRL)
522 typedef struct { /*!< FLASHCTRL Structure */
523 __I uint32_t RESERVED0[4];
524 __IO uint32_t FLASHCFG; /*!< Flash configuration register */
525 __I uint32_t RESERVED1[3];
526 __IO uint32_t FMSSTART; /*!< Signature start address register */
527 __IO uint32_t FMSSTOP; /*!< Signature stop-address register */
528 __I uint32_t RESERVED2;
529 __I uint32_t FMSW0; /*!< Signature Word */
530 } LPC_FLASHCTRL_Type;
533 /* ================================================================================ */
534 /* ================ SSP0 ================ */
535 /* ================================================================================ */
539 * @brief SSP/SPI (SSP0)
542 typedef struct { /*!< SSP0 Structure */
543 __IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type,
545 __IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */
546 __IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty
548 __I uint32_t SR; /*!< Status Register */
549 __IO uint32_t CPSR; /*!< Clock Prescale Register */
550 __IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */
551 __I uint32_t RIS; /*!< Raw Interrupt Status Register */
552 __I uint32_t MIS; /*!< Masked Interrupt Status Register */
553 __O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */
557 /* ================================================================================ */
558 /* ================ IOCON ================ */
559 /* ================================================================================ */
563 * @brief Product name title=Kylin UM Chapter title=KylinI/O control (IOCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (IOCON)
566 typedef struct { /*!< IOCON Structure */
567 __IO uint32_t PIO0_0; /*!< I/O configuration for port PIO0 */
568 __IO uint32_t PIO0_1; /*!< I/O configuration for port PIO0 */
569 __IO uint32_t PIO0_2; /*!< I/O configuration for port PIO0 */
570 __IO uint32_t PIO0_3; /*!< I/O configuration for port PIO0 */
571 __IO uint32_t PIO0_4; /*!< I/O configuration for port PIO0 */
572 __IO uint32_t PIO0_5; /*!< I/O configuration for port PIO0 */
573 __IO uint32_t PIO0_6; /*!< I/O configuration for port PIO0 */
574 __IO uint32_t PIO0_7; /*!< I/O configuration for port PIO0 */
575 __IO uint32_t PIO0_8; /*!< I/O configuration for port PIO0 */
576 __IO uint32_t PIO0_9; /*!< I/O configuration for port PIO0 */
577 __IO uint32_t PIO0_10; /*!< I/O configuration for port PIO0 */
578 __IO uint32_t PIO0_11; /*!< I/O configuration for port PIO0 */
579 __IO uint32_t PIO0_12; /*!< I/O configuration for port PIO0 */
580 __IO uint32_t PIO0_13; /*!< I/O configuration for port PIO0 */
581 __IO uint32_t PIO0_14; /*!< I/O configuration for port PIO0 */
582 __IO uint32_t PIO0_15; /*!< I/O configuration for port PIO0 */
583 __IO uint32_t PIO0_16; /*!< I/O configuration for port PIO0 */
584 __IO uint32_t PIO0_17; /*!< I/O configuration for port PIO0 */
585 __IO uint32_t PIO0_18; /*!< I/O configuration for port PIO0 */
586 __IO uint32_t PIO0_19; /*!< I/O configuration for port PIO0 */
587 __IO uint32_t PIO0_20; /*!< I/O configuration for port PIO0 */
588 __IO uint32_t PIO0_21; /*!< I/O configuration for port PIO0 */
589 __IO uint32_t PIO0_22; /*!< I/O configuration for port PIO0 */
590 __IO uint32_t PIO0_23; /*!< I/O configuration for port PIO0 */
591 __IO uint32_t PIO1_0; /*!< I/O configuration for port PIO1 */
592 __IO uint32_t PIO1_1; /*!< I/O configuration for port PIO1 */
593 __IO uint32_t PIO1_2; /*!< I/O configuration for port PIO1 */
594 __IO uint32_t PIO1_3; /*!< I/O configuration for port PIO1 */
595 __IO uint32_t PIO1_4; /*!< I/O configuration for port PIO1 */
596 __IO uint32_t PIO1_5; /*!< I/O configuration for port PIO1 */
597 __IO uint32_t PIO1_6; /*!< I/O configuration for port PIO1 */
598 __IO uint32_t PIO1_7; /*!< I/O configuration for port PIO1 */
599 __IO uint32_t PIO1_8; /*!< I/O configuration for port PIO1 */
600 __IO uint32_t PIO1_9; /*!< I/O configuration for port PIO1 */
601 __IO uint32_t PIO1_10; /*!< I/O configuration for port PIO1 */
602 __IO uint32_t PIO1_11; /*!< I/O configuration for port PIO1 */
603 __IO uint32_t PIO1_12; /*!< I/O configuration for port PIO1 */
604 __IO uint32_t PIO1_13; /*!< I/O configuration for port PIO1 */
605 __IO uint32_t PIO1_14; /*!< I/O configuration for port PIO1 */
606 __IO uint32_t PIO1_15; /*!< I/O configuration for port PIO1 */
607 __IO uint32_t PIO1_16; /*!< I/O configuration for port PIO1 */
608 __IO uint32_t PIO1_17; /*!< I/O configuration for port PIO1 */
609 __IO uint32_t PIO1_18; /*!< I/O configuration for port PIO1 */
610 __IO uint32_t PIO1_19; /*!< I/O configuration for port PIO1 */
611 __IO uint32_t PIO1_20; /*!< I/O configuration for port PIO1 */
612 __IO uint32_t PIO1_21; /*!< I/O configuration for port PIO1 */
613 __IO uint32_t PIO1_22; /*!< I/O configuration for port PIO1 */
614 __IO uint32_t PIO1_23; /*!< I/O configuration for port PIO1 */
615 __IO uint32_t PIO1_24; /*!< I/O configuration for port PIO1 */
616 __IO uint32_t PIO1_25; /*!< I/O configuration for port PIO1 */
617 __IO uint32_t PIO1_26; /*!< I/O configuration for port PIO1 */
618 __IO uint32_t PIO1_27; /*!< I/O configuration for port PIO1 */
619 __IO uint32_t PIO1_28; /*!< I/O configuration for port PIO1 */
620 __IO uint32_t PIO1_29; /*!< I/O configuration for port PIO1 */
621 __IO uint32_t PIO1_30; /*!< I/O configuration for port PIO1 */
622 __IO uint32_t PIO1_31; /*!< I/O configuration for port PIO1 */
623 __I uint32_t RESERVED0[4];
624 __IO uint32_t PIO2_0; /*!< I/O configuration for port PIO2 */
625 __IO uint32_t PIO2_1; /*!< I/O configuration for port PIO2 */
626 __I uint32_t RESERVED1;
627 __IO uint32_t PIO2_2; /*!< I/O configuration for port PIO2 */
628 __IO uint32_t PIO2_3; /*!< I/O configuration for port PIO2 */
629 __IO uint32_t PIO2_4; /*!< I/O configuration for port PIO2 */
630 __IO uint32_t PIO2_5; /*!< I/O configuration for port PIO2 */
631 __IO uint32_t PIO2_6; /*!< I/O configuration for port PIO2 */
632 __IO uint32_t PIO2_7; /*!< I/O configuration for port PIO2 */
633 __IO uint32_t PIO2_8; /*!< I/O configuration for port PIO2 */
634 __IO uint32_t PIO2_9; /*!< I/O configuration for port PIO2 */
635 __IO uint32_t PIO2_10; /*!< I/O configuration for port PIO2 */
636 __IO uint32_t PIO2_11; /*!< I/O configuration for port PIO2 */
637 __IO uint32_t PIO2_12; /*!< I/O configuration for port PIO2 */
638 __IO uint32_t PIO2_13; /*!< I/O configuration for port PIO2 */
639 __IO uint32_t PIO2_14; /*!< I/O configuration for port PIO2 */
640 __IO uint32_t PIO2_15; /*!< I/O configuration for port PIO2 */
641 __IO uint32_t PIO2_16; /*!< I/O configuration for port PIO2 */
642 __IO uint32_t PIO2_17; /*!< I/O configuration for port PIO2 */
643 __IO uint32_t PIO2_18; /*!< I/O configuration for port PIO2 */
644 __IO uint32_t PIO2_19; /*!< I/O configuration for port PIO2 */
645 __IO uint32_t PIO2_20; /*!< I/O configuration for port PIO2 */
646 __IO uint32_t PIO2_21; /*!< I/O configuration for port PIO2 */
647 __IO uint32_t PIO2_22; /*!< I/O configuration for port PIO2 */
648 __IO uint32_t PIO2_23; /*!< I/O configuration for port PIO2 */
652 /* ================================================================================ */
653 /* ================ SYSCON ================ */
654 /* ================================================================================ */
658 * @brief Product name title=Kylin UM Chapter title=KylinSystem configuration (SYSCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (SYSCON)
661 typedef struct { /*!< SYSCON Structure */
662 __IO uint32_t SYSMEMREMAP; /*!< System memory remap */
663 __IO uint32_t PRESETCTRL; /*!< Peripheral reset control */
664 __IO uint32_t SYSPLLCTRL; /*!< System PLL control */
665 __I uint32_t SYSPLLSTAT; /*!< System PLL status */
666 __IO uint32_t USBPLLCTRL; /*!< USB PLL control */
667 __I uint32_t USBPLLSTAT; /*!< USB PLL status */
668 __I uint32_t RESERVED0;
669 __IO uint32_t RTCOSCCTRL; /*!< RTC oscillator 32 kHz output control */
670 __IO uint32_t SYSOSCCTRL; /*!< System oscillator control */
671 __IO uint32_t WDTOSCCTRL; /*!< Watchdog oscillator control */
672 __I uint32_t RESERVED1[2];
673 __IO uint32_t SYSRSTSTAT; /*!< System reset status register */
674 __I uint32_t RESERVED2[3];
675 __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select */
676 __IO uint32_t SYSPLLCLKUEN; /*!< System PLL clock source update enable */
677 __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select */
678 __IO uint32_t USBPLLCLKUEN; /*!< USB PLL clock source update enable */
679 __I uint32_t RESERVED3[8];
680 __IO uint32_t MAINCLKSEL; /*!< Main clock source select */
681 __IO uint32_t MAINCLKUEN; /*!< Main clock source update enable */
682 __IO uint32_t SYSAHBCLKDIV; /*!< System clock divider */
683 __I uint32_t RESERVED4;
684 __IO uint32_t SYSAHBCLKCTRL; /*!< System clock control */
685 __I uint32_t RESERVED5[4];
686 __IO uint32_t SSP0CLKDIV; /*!< SSP0 clock divider */
687 __IO uint32_t USART0CLKDIV; /*!< USART0 clock divider */
688 __IO uint32_t SSP1CLKDIV; /*!< SSP1 clock divider */
689 __IO uint32_t FRGCLKDIV; /*!< Clock divider for the common fractional baud rate generator
690 of USART1 to USART4 */
691 __I uint32_t RESERVED6[7];
692 __IO uint32_t USBCLKSEL; /*!< USB clock source select */
693 __IO uint32_t USBCLKUEN; /*!< USB clock source update enable */
694 __IO uint32_t USBCLKDIV; /*!< USB clock source divider */
695 __I uint32_t RESERVED7[5];
696 __IO uint32_t CLKOUTSEL; /*!< CLKOUT clock source select */
697 __IO uint32_t CLKOUTUEN; /*!< CLKOUT clock source update enable */
698 __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */
699 __I uint32_t RESERVED8;
700 __IO uint32_t UARTFRGDIV; /*!< USART fractional generator divider value */
701 __IO uint32_t UARTFRGMULT; /*!< USART fractional generator multiplier value */
702 __I uint32_t RESERVED9;
703 __IO uint32_t EXTTRACECMD; /*!< External trace buffer command register */
704 __I uint32_t PIOPORCAP0; /*!< POR captured PIO status 0 */
705 __I uint32_t PIOPORCAP1; /*!< POR captured PIO status 1 */
706 __I uint32_t PIOPORCAP2; /*!< POR captured PIO status 1 */
707 __I uint32_t RESERVED10[10];
708 __IO uint32_t IOCONCLKDIV6; /*!< Peripheral clock 6 to the IOCON block for programmable glitch
710 __IO uint32_t IOCONCLKDIV5; /*!< Peripheral clock 5 to the IOCON block for programmable glitch
712 __IO uint32_t IOCONCLKDIV4; /*!< Peripheral clock 4 to the IOCON block for programmable glitch
714 __IO uint32_t IOCONCLKDIV3; /*!< Peripheral clock 3 to the IOCON block for programmable glitch
716 __IO uint32_t IOCONCLKDIV2; /*!< Peripheral clock 2 to the IOCON block for programmable glitch
718 __IO uint32_t IOCONCLKDIV1; /*!< Peripheral clock 1 to the IOCON block for programmable glitch
720 __IO uint32_t IOCONCLKDIV0; /*!< Peripheral clock 0 to the IOCON block for programmable glitch
722 __IO uint32_t BODCTRL; /*!< Brown-Out Detect */
723 __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */
724 __IO uint32_t AHBMATRIXPRIO; /*!< AHB matrix priority configuration */
725 __I uint32_t RESERVED11[5];
726 __IO uint32_t IRQLATENCY; /*!< IRQ delay. Allows trade-off between interrupt latency and determinism. */
727 __IO uint32_t NMISRC; /*!< NMI Source Control */
729 __IO uint32_t PINTSEL[8];
731 __IO uint32_t PINTSEL0; /*!< GPIO Pin Interrupt Select register 0 */
732 __IO uint32_t PINTSEL1; /*!< GPIO Pin Interrupt Select register 0 */
733 __IO uint32_t PINTSEL2; /*!< GPIO Pin Interrupt Select register 0 */
734 __IO uint32_t PINTSEL3; /*!< GPIO Pin Interrupt Select register 0 */
735 __IO uint32_t PINTSEL4; /*!< GPIO Pin Interrupt Select register 0 */
736 __IO uint32_t PINTSEL5; /*!< GPIO Pin Interrupt Select register 0 */
737 __IO uint32_t PINTSEL6; /*!< GPIO Pin Interrupt Select register 0 */
738 __IO uint32_t PINTSEL7; /*!< GPIO Pin Interrupt Select register 0 */
741 __IO uint32_t USBCLKCTRL; /*!< USB clock control */
742 __I uint32_t USBCLKST; /*!< USB clock status */
743 __I uint32_t RESERVED12[25];
744 __IO uint32_t STARTERP0; /*!< Start logic 0 interrupt wake-up enable register 0 */
745 __I uint32_t RESERVED13[3];
746 __IO uint32_t STARTERP1; /*!< Start logic 1 interrupt wake-up enable register 1 */
747 __I uint32_t RESERVED14[6];
748 __IO uint32_t PDSLEEPCFG; /*!< Power-down states in deep-sleep mode */
749 __IO uint32_t PDAWAKECFG; /*!< Power-down states for wake-up from deep-sleep */
750 __IO uint32_t PDRUNCFG; /*!< Power configuration register */
751 __I uint32_t RESERVED15[110];
752 __I uint32_t DEVICE_ID; /*!< Device ID */
756 /* ================================================================================ */
757 /* ================ USART4 ================ */
758 /* ================================================================================ */
762 * @brief USART4 (USART4)
765 typedef struct { /*!< USART4 Structure */
766 __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
767 that typically are not changed during operation. */
768 __IO uint32_t CTL; /*!< USART Control register. USART control settings that are more
769 likely to change during operation. */
770 __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
771 here. Writing ones clears some bits in the register. Some bits
772 can be cleared by writing a 1 to them. */
773 __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
774 interrupt enable bit for each potential USART interrupt. A complete
775 value may be read from this register. Writing a 1 to any implemented
776 bit position causes that bit to be set. */
777 __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
778 of bits in the INTENSET register. Writing a 1 to any implemented
779 bit position causes the corresponding bit to be cleared. */
780 __I uint32_t RXDAT; /*!< Receiver Data register. Contains the last character received. */
781 __I uint32_t RXDATSTAT; /*!< Receiver Data with Status register. Combines the last character
782 received with the current USART receive status. Allows DMA or
783 software to recover incoming data and status together. */
784 __IO uint32_t TXDAT; /*!< Transmit Data register. Data to be transmitted is written here. */
785 __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
787 __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
789 __IO uint32_t OSR; /*!< Oversample selection register for asynchronous communication. */
790 __IO uint32_t ADDR; /*!< Address register for automatic address matching. */
794 /* ================================================================================ */
795 /* ================ GINT0 ================ */
796 /* ================================================================================ */
800 * @brief GPIO group interrupt 0 (GINT0)
803 typedef struct { /*!< GINT0 Structure */
804 __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
805 __I uint32_t RESERVED0[7];
806 __IO uint32_t PORT_POL[3]; /*!< GPIO grouped interrupt port 0 polarity register */
807 __I uint32_t RESERVED1[5];
808 __IO uint32_t PORT_ENA[3]; /*!< GPIO grouped interrupt port enable register */
812 /* ================================================================================ */
813 /* ================ USB ================ */
814 /* ================================================================================ */
818 * @brief USB device controller (USB)
821 typedef struct { /*!< USB Structure */
822 __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */
823 __IO uint32_t INFO; /*!< USB Info register */
824 __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */
825 __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */
826 __IO uint32_t LPM; /*!< Link Power Management register */
827 __IO uint32_t EPSKIP; /*!< USB Endpoint skip */
828 __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */
829 __IO uint32_t EPBUFCFG; /*!< USB Endpoint Buffer Configuration register */
830 __IO uint32_t INTSTAT; /*!< USB interrupt status register */
831 __IO uint32_t INTEN; /*!< USB interrupt enable register */
832 __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */
833 __IO uint32_t INTROUTING; /*!< USB interrupt routing register */
834 __I uint32_t RESERVED0;
835 __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */
839 /* ================================================================================ */
840 /* ================ CRC ================ */
841 /* ================================================================================ */
845 * @brief Cyclic Redundancy Check (CRC) engine (CRC)
848 typedef struct { /*!< CRC Structure */
849 __IO uint32_t MODE; /*!< CRC mode register */
850 __IO uint32_t SEED; /*!< CRC seed register */
853 __O uint32_t WR_DATA; /*!< CRC data register */
854 __I uint32_t SUM; /*!< CRC checksum register */
859 /* ================================================================================ */
860 /* ================ DMA ================ */
861 /* ================================================================================ */
865 * @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMA)
868 typedef struct { /*!< DMA Structure */
869 __IO uint32_t CTRL; /*!< DMA control. */
870 __I uint32_t INTSTAT; /*!< Interrupt status. */
871 __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */
872 __I uint32_t RESERVED0[5];
873 __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels. */
874 __I uint32_t RESERVED1;
875 __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */
876 __I uint32_t RESERVED2;
877 __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */
878 __I uint32_t RESERVED3;
879 __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */
880 __I uint32_t RESERVED4;
881 __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */
882 __I uint32_t RESERVED5;
883 __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */
884 __I uint32_t RESERVED6;
885 __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */
886 __I uint32_t RESERVED7;
887 __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */
888 __I uint32_t RESERVED8;
889 __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */
890 __I uint32_t RESERVED9;
891 __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */
892 __I uint32_t RESERVED10;
893 __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */
894 __I uint32_t RESERVED11;
895 __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */
896 __I uint32_t RESERVED12[225];
897 __IO uint32_t CFG0; /*!< Configuration register for DMA channel 0. */
898 __I uint32_t CTLSTAT0; /*!< Control and status register for DMA channel 0. */
899 __IO uint32_t XFERCFG0; /*!< Transfer configuration register for DMA channel 0. */
900 __I uint32_t RESERVED13;
901 __IO uint32_t CFG1; /*!< Configuration register for DMA channel 0. */
902 __I uint32_t CTLSTAT1; /*!< Control and status register for DMA channel 0. */
903 __IO uint32_t XFERCFG1; /*!< Transfer configuration register for DMA channel 0. */
904 __I uint32_t RESERVED14;
905 __IO uint32_t CFG2; /*!< Configuration register for DMA channel 0. */
906 __I uint32_t CTLSTAT2; /*!< Control and status register for DMA channel 0. */
907 __IO uint32_t XFERCFG2; /*!< Transfer configuration register for DMA channel 0. */
908 __I uint32_t RESERVED15;
909 __IO uint32_t CFG3; /*!< Configuration register for DMA channel 0. */
910 __I uint32_t CTLSTAT3; /*!< Control and status register for DMA channel 0. */
911 __IO uint32_t XFERCFG3; /*!< Transfer configuration register for DMA channel 0. */
912 __I uint32_t RESERVED16;
913 __IO uint32_t CFG4; /*!< Configuration register for DMA channel 0. */
914 __I uint32_t CTLSTAT4; /*!< Control and status register for DMA channel 0. */
915 __IO uint32_t XFERCFG4; /*!< Transfer configuration register for DMA channel 0. */
916 __I uint32_t RESERVED17;
917 __IO uint32_t CFG5; /*!< Configuration register for DMA channel 0. */
918 __I uint32_t CTLSTAT5; /*!< Control and status register for DMA channel 0. */
919 __IO uint32_t XFERCFG5; /*!< Transfer configuration register for DMA channel 0. */
920 __I uint32_t RESERVED18;
921 __IO uint32_t CFG6; /*!< Configuration register for DMA channel 0. */
922 __I uint32_t CTLSTAT6; /*!< Control and status register for DMA channel 0. */
923 __IO uint32_t XFERCFG6; /*!< Transfer configuration register for DMA channel 0. */
924 __I uint32_t RESERVED19;
925 __IO uint32_t CFG7; /*!< Configuration register for DMA channel 0. */
926 __I uint32_t CTLSTAT7; /*!< Control and status register for DMA channel 0. */
927 __IO uint32_t XFERCFG7; /*!< Transfer configuration register for DMA channel 0. */
928 __I uint32_t RESERVED20;
929 __IO uint32_t CFG8; /*!< Configuration register for DMA channel 0. */
930 __I uint32_t CTLSTAT8; /*!< Control and status register for DMA channel 0. */
931 __IO uint32_t XFERCFG8; /*!< Transfer configuration register for DMA channel 0. */
932 __I uint32_t RESERVED21;
933 __IO uint32_t CFG9; /*!< Configuration register for DMA channel 0. */
934 __I uint32_t CTLSTAT9; /*!< Control and status register for DMA channel 0. */
935 __IO uint32_t XFERCFG9; /*!< Transfer configuration register for DMA channel 0. */
936 __I uint32_t RESERVED22;
937 __IO uint32_t CFG10; /*!< Configuration register for DMA channel 0. */
938 __I uint32_t CTLSTAT10; /*!< Control and status register for DMA channel 0. */
939 __IO uint32_t XFERCFG10; /*!< Transfer configuration register for DMA channel 0. */
940 __I uint32_t RESERVED23;
941 __IO uint32_t CFG11; /*!< Configuration register for DMA channel 0. */
942 __I uint32_t CTLSTAT11; /*!< Control and status register for DMA channel 0. */
943 __IO uint32_t XFERCFG11; /*!< Transfer configuration register for DMA channel 0. */
944 __I uint32_t RESERVED24;
945 __IO uint32_t CFG12; /*!< Configuration register for DMA channel 0. */
946 __I uint32_t CTLSTAT12; /*!< Control and status register for DMA channel 0. */
947 __IO uint32_t XFERCFG12; /*!< Transfer configuration register for DMA channel 0. */
948 __I uint32_t RESERVED25;
949 __IO uint32_t CFG13; /*!< Configuration register for DMA channel 0. */
950 __I uint32_t CTLSTAT13; /*!< Control and status register for DMA channel 0. */
951 __IO uint32_t XFERCFG13; /*!< Transfer configuration register for DMA channel 0. */
952 __I uint32_t RESERVED26;
953 __IO uint32_t CFG14; /*!< Configuration register for DMA channel 0. */
954 __I uint32_t CTLSTAT14; /*!< Control and status register for DMA channel 0. */
955 __IO uint32_t XFERCFG14; /*!< Transfer configuration register for DMA channel 0. */
956 __I uint32_t RESERVED27;
957 __IO uint32_t CFG15; /*!< Configuration register for DMA channel 0. */
958 __I uint32_t CTLSTAT15; /*!< Control and status register for DMA channel 0. */
959 __IO uint32_t XFERCFG15; /*!< Transfer configuration register for DMA channel 0. */
963 /* ================================================================================ */
964 /* ================ SCT0 ================ */
965 /* ================================================================================ */
969 * @brief Product name title=Kylin UM Chapter title=KylinState Configurable Timers (SCT0/1) Modification date=5/14/2013 Major revision=0 Minor revision=1 (SCT0)
972 typedef struct { /*!< SCT0 Structure */
973 __IO uint32_t CONFIG; /*!< SCT configuration register */
974 __IO uint32_t CTRL; /*!< SCT control register */
975 __IO uint32_t LIMIT; /*!< SCT limit register */
976 __IO uint32_t HALT; /*!< SCT halt condition register */
977 __IO uint32_t STOP; /*!< SCT stop condition register */
978 __IO uint32_t START; /*!< SCT start condition register */
979 __I uint32_t RESERVED0[10];
980 __IO uint32_t COUNT; /*!< SCT counter register */
981 __IO uint32_t STATE; /*!< SCT state register */
982 __I uint32_t INPUT; /*!< SCT input register */
983 __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
984 __IO uint32_t OUTPUT; /*!< SCT output register */
985 __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
986 __IO uint32_t RES; /*!< SCT conflict resolution register */
987 __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
988 __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
989 __I uint32_t RESERVED1[35];
990 __IO uint32_t EVEN; /*!< SCT event enable register */
991 __IO uint32_t EVFLAG; /*!< SCT event flag register */
992 __IO uint32_t CONEN; /*!< SCT conflict enable register */
993 __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
996 __IO uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
998 __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
1003 __IO uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
1005 __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
1010 __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
1012 __IO uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
1017 __IO uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
1019 __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
1024 __IO uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
1026 __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
1029 __I uint32_t RESERVED2[59];
1032 __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
1034 __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
1039 __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
1041 __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
1046 __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
1048 __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
1053 __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
1055 __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
1060 __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
1062 __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
1065 __I uint32_t RESERVED3[59];
1066 __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
1067 __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
1068 __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
1069 __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
1070 __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
1071 __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
1072 __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
1073 __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
1074 __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
1075 __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
1076 __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
1077 __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
1078 __I uint32_t RESERVED4[116];
1079 __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
1080 __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
1081 __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
1082 __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
1083 __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
1084 __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
1085 __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
1086 __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
1090 /* ================================================================================ */
1091 /* ================ GPIO_PORT ================ */
1092 /* ================================================================================ */
1096 * @brief General Purpose I/O (GPIO) (GPIO_PORT)
1099 typedef struct { /*!< GPIO_PORT Structure */
1100 __IO uint8_t B[88]; /*!< Byte pin registers */
1101 __I uint32_t RESERVED0[42];
1102 __IO uint32_t W[88]; /*!< Word pin registers */
1103 __I uint32_t RESERVED1[1896];
1104 __IO uint32_t DIR[3]; /*!< Port Direction registers */
1105 __I uint32_t RESERVED2[29];
1106 __IO uint32_t MASK[3]; /*!< Port Mask register */
1107 __I uint32_t RESERVED3[29];
1108 __IO uint32_t PIN[3]; /*!< Port pin register */
1109 __I uint32_t RESERVED4[29];
1110 __IO uint32_t MPIN[3]; /*!< Masked port register */
1111 __I uint32_t RESERVED5[29];
1112 __IO uint32_t SET[3]; /*!< Write: Set port register Read: port output bits */
1113 __I uint32_t RESERVED6[29];
1114 __O uint32_t CLR[3]; /*!< Clear port */
1115 __I uint32_t RESERVED7[29];
1116 __O uint32_t NOT[3]; /*!< Toggle port */
1117 } LPC_GPIO_PORT_Type;
1120 /* ================================================================================ */
1121 /* ================ PINT ================ */
1122 /* ================================================================================ */
1126 * @brief Pin interruptand pattern match (PINT) (PINT)
1129 typedef struct { /*!< PINT Structure */
1130 __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
1131 __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register */
1132 __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register */
1133 __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register */
1134 __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
1136 __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */
1137 __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */
1138 __IO uint32_t RISE; /*!< Pin interrupt rising edge register */
1139 __IO uint32_t FALL; /*!< Pin interrupt falling edge register */
1140 __IO uint32_t IST; /*!< Pin interrupt status register */
1141 __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */
1142 __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */
1143 __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */
1147 /* -------------------- End of section using anonymous unions ------------------- */
1148 #if defined(__CC_ARM)
1150 #elif defined(__ICCARM__)
1151 /* leave anonymous unions enabled */
1152 #elif defined(__GNUC__)
1153 /* anonymous unions are enabled by default */
1154 #elif defined(__TMS470__)
1155 /* anonymous unions are enabled by default */
1156 #elif defined(__TASKING__)
1157 #pragma warning restore
1159 #warning Not supported compiler type
1165 /* ================================================================================ */
1166 /* ================ Peripheral memory map ================ */
1167 /* ================================================================================ */
1169 #define LPC_I2C0_BASE 0x40000000UL
1170 #define LPC_WWDT_BASE 0x40004000UL
1171 #define LPC_USART0_BASE 0x40008000UL
1172 #define LPC_CT16B0_BASE 0x4000C000UL
1173 #define LPC_CT16B1_BASE 0x40010000UL
1174 #define LPC_CT32B0_BASE 0x40014000UL
1175 #define LPC_CT32B1_BASE 0x40018000UL
1176 #define LPC_ADC_BASE 0x4001C000UL
1177 #define LPC_I2C1_BASE 0x40020000UL
1178 #define LPC_RTC_BASE 0x40024000UL
1179 #define LPC_DMATRIGMUX_BASE 0x40028000UL
1180 #define LPC_PMU_BASE 0x40038000UL
1181 #define LPC_FLASHCTRL_BASE 0x4003C000UL
1182 #define LPC_SSP0_BASE 0x40040000UL
1183 #define LPC_IOCON_BASE 0x40044000UL
1184 #define LPC_SYSCON_BASE 0x40048000UL
1185 #define LPC_USART4_BASE 0x4004C000UL
1186 #define LPC_SSP1_BASE 0x40058000UL
1187 #define LPC_GINT0_BASE 0x4005C000UL
1188 #define LPC_GINT1_BASE 0x40060000UL
1189 #define LPC_USART1_BASE 0x4006C000UL
1190 #define LPC_USART2_BASE 0x40070000UL
1191 #define LPC_USART3_BASE 0x40074000UL
1192 #define LPC_USB_BASE 0x40080000UL
1193 #define LPC_CRC_BASE 0x50000000UL
1194 #define LPC_DMA_BASE 0x50004000UL
1195 #define LPC_SCT0_BASE 0x5000C000UL
1196 #define LPC_SCT1_BASE 0x5000E000UL
1197 #define LPC_GPIO_PORT_BASE 0xA0000000UL
1198 #define LPC_PINT_BASE 0xA0004000UL
1201 /* ================================================================================ */
1202 /* ================ Peripheral declaration ================ */
1203 /* ================================================================================ */
1205 #define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
1206 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
1207 #define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
1208 #define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
1209 #define LPC_CT16B1 ((LPC_CT16B0_Type *) LPC_CT16B1_BASE)
1210 #define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
1211 #define LPC_CT32B1 ((LPC_CT32B0_Type *) LPC_CT32B1_BASE)
1212 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
1213 #define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
1214 #define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
1215 #define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
1216 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
1217 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
1218 #define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
1219 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
1220 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
1221 #define LPC_USART4 ((LPC_USART4_Type *) LPC_USART4_BASE)
1222 #define LPC_SSP1 ((LPC_SSP0_Type *) LPC_SSP1_BASE)
1223 #define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
1224 #define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
1225 #define LPC_USART1 ((LPC_USART4_Type *) LPC_USART1_BASE)
1226 #define LPC_USART2 ((LPC_USART4_Type *) LPC_USART2_BASE)
1227 #define LPC_USART3 ((LPC_USART4_Type *) LPC_USART3_BASE)
1228 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
1229 #define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
1230 #define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
1231 #define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
1232 #define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
1233 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
1234 #define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
1237 /** @} */ /* End of group Device_Peripheral_Registers */
1238 /** @} */ /* End of group LPC11U6x */
1239 /** @} */ /* End of group (null) */
1246 #endif /* LPC11U6x_H */
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