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[qmk_firmware.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_NORDIC / TARGET_MCU_NRF51822 / TOOLCHAIN_ARM_STD / TARGET_MCU_NORDIC_32K / startup_nRF51822.s
1 ; mbed Microcontroller Library
2 ; Copyright (c) 2013 Nordic Semiconductor.
3 ;Licensed under the Apache License, Version 2.0 (the "License");
4 ;you may not use this file except in compliance with the License.
5 ;You may obtain a copy of the License at
6 ;http://www.apache.org/licenses/LICENSE-2.0
7 ;Unless required by applicable law or agreed to in writing, software
8 ;distributed under the License is distributed on an "AS IS" BASIS,
9 ;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
10 ;See the License for the specific language governing permissions and
11 ;limitations under the License.
12
13 ; Description message
14
15 __initial_sp    EQU     0x20008000
16
17
18                 PRESERVE8
19                 THUMB
20
21 ; Vector Table Mapped to Address 0 at Reset
22
23                 AREA    RESET, DATA, READONLY
24                 EXPORT  __Vectors
25                 EXPORT  __Vectors_End
26                 EXPORT  __Vectors_Size
27
28 __Vectors       DCD     __initial_sp              ; Top of Stack
29                 DCD     Reset_Handler             ; Reset Handler
30                 DCD     NMI_Handler               ; NMI Handler
31                 DCD     HardFault_Handler         ; Hard Fault Handler
32                 DCD     0                         ; Reserved
33                 DCD     0                         ; Reserved
34                 DCD     0                         ; Reserved
35                 DCD     0                         ; Reserved
36                 DCD     0                         ; Reserved
37                 DCD     0                         ; Reserved
38                 DCD     0                         ; Reserved
39                 DCD     SVC_Handler               ; SVCall Handler
40                 DCD     0                         ; Reserved
41                 DCD     0                         ; Reserved
42                 DCD     PendSV_Handler            ; PendSV Handler
43                 DCD     SysTick_Handler           ; SysTick Handler
44
45                 ; External Interrupts
46                 DCD      POWER_CLOCK_IRQHandler ;POWER_CLOCK
47                 DCD      RADIO_IRQHandler ;RADIO
48                 DCD      UART0_IRQHandler ;UART0
49                 DCD      SPI0_TWI0_IRQHandler ;SPI0_TWI0
50                 DCD      SPI1_TWI1_IRQHandler ;SPI1_TWI1
51                 DCD      0 ;Reserved
52                 DCD      GPIOTE_IRQHandler ;GPIOTE
53                 DCD      ADC_IRQHandler ;ADC
54                 DCD      TIMER0_IRQHandler ;TIMER0
55                 DCD      TIMER1_IRQHandler ;TIMER1
56                 DCD      TIMER2_IRQHandler ;TIMER2
57                 DCD      RTC0_IRQHandler ;RTC0
58                 DCD      TEMP_IRQHandler ;TEMP
59                 DCD      RNG_IRQHandler ;RNG
60                 DCD      ECB_IRQHandler ;ECB
61                 DCD      CCM_AAR_IRQHandler ;CCM_AAR
62                 DCD      WDT_IRQHandler ;WDT
63                 DCD      RTC1_IRQHandler ;RTC1
64                 DCD      QDEC_IRQHandler ;QDEC
65                 DCD      LPCOMP_IRQHandler ;LPCOMP
66                 DCD      SWI0_IRQHandler ;SWI0
67                 DCD      SWI1_IRQHandler ;SWI1
68                 DCD      SWI2_IRQHandler ;SWI2
69                 DCD      SWI3_IRQHandler ;SWI3
70                 DCD      SWI4_IRQHandler ;SWI4
71                 DCD      SWI5_IRQHandler ;SWI5
72                 DCD      0 ;Reserved
73                 DCD      0 ;Reserved
74                 DCD      0 ;Reserved
75                 DCD      0 ;Reserved
76                 DCD      0 ;Reserved
77                 DCD      0 ;Reserved
78
79
80 __Vectors_End
81
82 __Vectors_Size  EQU     __Vectors_End - __Vectors
83
84                 AREA    |.text|, CODE, READONLY
85
86 ; Reset Handler
87
88 NRF_POWER_RAMON_ADDRESS            EQU   0x40000524  ; NRF_POWER->RAMON address
89 NRF_POWER_RAMONB_ADDRESS           EQU   0x40000554  ; NRF_POWER->RAMONB address
90 NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU   0x3         ; All RAM blocks on in onmode bit mask
91
92 Reset_Handler   PROC
93                 EXPORT  Reset_Handler             [WEAK]
94                 IMPORT  SystemInit
95                 IMPORT  __main
96                 
97                 MOVS    R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
98                 
99                 LDR     R0, =NRF_POWER_RAMON_ADDRESS
100                 LDR     R2, [R0]
101                 ORRS    R2, R2, R1
102                 STR     R2, [R0]
103                 
104                 LDR     R0, =NRF_POWER_RAMONB_ADDRESS
105                 LDR     R2, [R0]
106                 ORRS    R2, R2, R1
107                 STR     R2, [R0]
108                 
109                 LDR     R0, =SystemInit
110                 BLX     R0
111                 LDR     R0, =__main
112                 BX      R0
113                 ENDP
114
115 ; Dummy Exception Handlers (infinite loops which can be modified)
116
117 NMI_Handler     PROC
118                 EXPORT  NMI_Handler               [WEAK]
119                 B       .
120                 ENDP
121 HardFault_Handler\
122                 PROC
123                 EXPORT  HardFault_Handler         [WEAK]
124                 B       .
125                 ENDP
126 SVC_Handler     PROC
127                 EXPORT  SVC_Handler               [WEAK]
128                 B       .
129                 ENDP
130 PendSV_Handler  PROC
131                 EXPORT  PendSV_Handler            [WEAK]
132                 B       .
133                 ENDP
134 SysTick_Handler PROC
135                 EXPORT  SysTick_Handler           [WEAK]
136                 B       .
137                 ENDP
138
139 Default_Handler PROC
140
141                 EXPORT   POWER_CLOCK_IRQHandler [WEAK]
142                 EXPORT   RADIO_IRQHandler [WEAK]
143                 EXPORT   UART0_IRQHandler [WEAK]
144                 EXPORT   SPI0_TWI0_IRQHandler [WEAK]
145                 EXPORT   SPI1_TWI1_IRQHandler [WEAK]
146                 EXPORT   GPIOTE_IRQHandler [WEAK]
147                 EXPORT   ADC_IRQHandler [WEAK]
148                 EXPORT   TIMER0_IRQHandler [WEAK]
149                 EXPORT   TIMER1_IRQHandler [WEAK]
150                 EXPORT   TIMER2_IRQHandler [WEAK]
151                 EXPORT   RTC0_IRQHandler [WEAK]
152                 EXPORT   TEMP_IRQHandler [WEAK]
153                 EXPORT   RNG_IRQHandler [WEAK]
154                 EXPORT   ECB_IRQHandler [WEAK]
155                 EXPORT   CCM_AAR_IRQHandler [WEAK]
156                 EXPORT   WDT_IRQHandler [WEAK]
157                 EXPORT   RTC1_IRQHandler [WEAK]
158                 EXPORT   QDEC_IRQHandler [WEAK]
159                 EXPORT   LPCOMP_IRQHandler [WEAK]
160                 EXPORT   SWI0_IRQHandler [WEAK]
161                 EXPORT   SWI1_IRQHandler [WEAK]
162                 EXPORT   SWI2_IRQHandler [WEAK]
163                 EXPORT   SWI3_IRQHandler [WEAK]
164                 EXPORT   SWI4_IRQHandler [WEAK]
165                 EXPORT   SWI5_IRQHandler [WEAK]
166 POWER_CLOCK_IRQHandler
167 RADIO_IRQHandler
168 UART0_IRQHandler
169 SPI0_TWI0_IRQHandler
170 SPI1_TWI1_IRQHandler
171 GPIOTE_IRQHandler
172 ADC_IRQHandler
173 TIMER0_IRQHandler
174 TIMER1_IRQHandler
175 TIMER2_IRQHandler
176 RTC0_IRQHandler
177 TEMP_IRQHandler
178 RNG_IRQHandler
179 ECB_IRQHandler
180 CCM_AAR_IRQHandler
181 WDT_IRQHandler
182 RTC1_IRQHandler
183 QDEC_IRQHandler
184 LPCOMP_IRQHandler
185 SWI0_IRQHandler
186 SWI1_IRQHandler
187 SWI2_IRQHandler
188 SWI3_IRQHandler
189 SWI4_IRQHandler
190 SWI5_IRQHandler
191
192                 B .
193                 ENDP
194                 ALIGN
195                 END
196