tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c

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  32  */
  33
  34 #include "max32610.h"
  35 #include "clkman_regs.h"
  36 #include "pwrman_regs.h"
  37 #include "ioman_regs.h"
  38 #include "trim_regs.h"
  39 #include "flc_regs.h"
  40 #include "pwrseq_regs.h"
  41 #include "dac_regs.h"
  42 #include "icc_regs.h"
  43
  44 /* Application developer should override where necessary with different external HFX source */
  45 #ifndef __SYSTEM_HFX
  46 #define __SYSTEM_HFX 24000000
  47 #endif
  48
  49 uint32_t SystemCoreClock = 24000000;
  50
  51 void SystemCoreClockUpdate(void)
  52 {
  53     switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) {
  54         case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8:
  55             SystemCoreClock = 3000000;
  56             break;
  57         case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO:
  58         case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2:
  59             SystemCoreClock = 24000000;
  60             break;
  61         case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX:
  62             SystemCoreClock = __SYSTEM_HFX;
  63             break;
  64     }
  65
  66     uint32_t shift = MXC_CLKMAN->clk_ctrl_0_system;
  67     if (shift) {
  68         SystemCoreClock = SystemCoreClock >> (shift - 1);
  69     }
  70 }
  71
  72 /* power seq registers */
  73 static void set_pwr_regs(void)
  74 {
  75     uint32_t dac2trim =  MXC_DAC2->reg & 0xff00ffff;
  76     uint32_t dac3trim =  MXC_DAC3->reg & 0xff00ffff;
  77     dac2trim = dac2trim + MXC_TRIM->trim_reg_36;
  78     dac3trim = dac3trim + MXC_TRIM->trim_reg_37;
  79     MXC_PWRSEQ->reg5 = MXC_TRIM->trim_reg_13;
  80     MXC_PWRSEQ->reg6 = MXC_TRIM->trim_reg_14;
  81     MXC_DAC0->trm = MXC_TRIM->trim_reg_34;
  82     MXC_DAC1->trm = MXC_TRIM->trim_reg_35;
  83     MXC_DAC2->reg = dac2trim;
  84     MXC_DAC3->reg = dac3trim;
  85 }
  86
  87 void ICC_Enable(void)
  88 {
  89     /* clock gater must be 'on' not 'dynamic' for cache control */
  90     uint32_t temp = MXC_CLKMAN->clk_gate_ctrl0;
  91     temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER;
  92     temp |= (MXC_E_CLKMAN_CLK_GATE_ON << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS);
  93     MXC_CLKMAN->clk_gate_ctrl0 = temp;
  94
  95
  96     /* invalidate, wait, enable */
  97     MXC_ICC->invdt_all = 0xFFFF;
  98     while(!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
  99     MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
 100
 101     /* must invalidate a second time for proper use */
 102     MXC_ICC->invdt_all = 1;
 103
 104     /* clock gater 'dynamic' safe again */
 105     temp = MXC_CLKMAN->clk_gate_ctrl0;
 106     temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER;
 107     temp |= (MXC_E_CLKMAN_CLK_GATE_DYNAMIC << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS);
 108     MXC_CLKMAN->clk_gate_ctrl0 = temp;
 109 }
 110
 111 // This function to be implemented by the hal
 112 extern void low_level_init(void);
 113
 114 void SystemInit(void)
 115 {
 116     set_pwr_regs();
 117
 118     // Turn off PADX
 119     MXC_IOMAN->padx_control = 0x00000441;
 120
 121     // enable instruction cache
 122     ICC_Enable();
 123
 124     low_level_init();
 125
 126     // Clear IO Active
 127     MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
 128                                 MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE);
 129
 130     // Set WUD Clear
 131     MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
 132                                 MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE |
 133                                 MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR);
 134
 135     // Set IO Active
 136     MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
 137                                 MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE |
 138                                 MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE |
 139                                 MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED);
 140
 141     MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN;
 142
 143     // set systick to the RTC input 32.768kHz clock, not system clock; this is needed to keep JTAG alive during sleep
 144     MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
 145
 146     SystemCoreClockUpdate();
 147 }