tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/i2cm_regs.h

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  33
  34 #ifndef _MXC_I2CM_REGS_H_
  35 #define _MXC_I2CM_REGS_H_
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 #include <stdint.h>
  42
  43 /**
  44  * @file  i2cm_regs.h
  45  * @addtogroup i2cm I2CM
  46  * @{
  47  */
  48
  49 /*                                      Offset   Register Description
  50                                         ======   ================================================ */
  51 typedef struct {
  52     __IO uint32_t fs_clk_div;       /*  0x0000   Full Speed SCL Clock Settings                    */
  53     __IO uint32_t hs_clk_div;       /*  0x0004   High Speed SCL Clock Settings                    */
  54     __I uint32_t rsv0008;           /*  0x0008                                                    */
  55     __IO uint32_t timeout;          /*  0x000C   [TO_CNTL] Timeout and Auto-Stop Settings         */
  56     __IO uint32_t ctrl;             /*  0x0010   [EN_CNTL] I2C Master Control Register            */
  57     __IO uint32_t trans;            /*  0x0014   [MSTR_CNTL] I2C Master Tx Start and Status Flags */
  58     __IO uint32_t intfl;            /*  0x0018   Interrupt Flags                                  */
  59     __IO uint32_t inten;            /*  0x001C   Interrupt Enable/Disable Controls                */
  60     __I uint32_t rsv0020[2];        /*  0x0020                                                    */
  61     __IO uint32_t bb;               /*  0x0028   Bit-Bang Control Register                        */
  62 } mxc_i2cm_regs_t;
  63
  64 /*                                      Offset   Register Description
  65                                         ======   ================================================ */
  66 typedef struct {
  67     __IO uint32_t trans[512];       /*  0x0000   I2C Master Transaction FIFO                      */
  68     __IO uint32_t rslts[512];       /*  0x0800   I2C Master Results FIFO                          */
  69 } mxc_i2cm_fifo_regs_t;
  70
  71 /*
  72    Register offsets for module I2CM.
  73 */
  74 #define MXC_R_I2CM_OFFS_FS_CLK_DIV                ((uint32_t)0x00000000UL)
  75 #define MXC_R_I2CM_OFFS_HS_CLK_DIV                ((uint32_t)0x00000004UL)
  76 #define MXC_R_I2CM_OFFS_TIMEOUT                   ((uint32_t)0x0000000CUL)
  77 #define MXC_R_I2CM_OFFS_CTRL                      ((uint32_t)0x00000010UL)
  78 #define MXC_R_I2CM_OFFS_TRANS                     ((uint32_t)0x00000014UL)
  79 #define MXC_R_I2CM_OFFS_INTFL                     ((uint32_t)0x00000018UL)
  80 #define MXC_R_I2CM_OFFS_INTEN                     ((uint32_t)0x0000001CUL)
  81 #define MXC_R_I2CM_OFFS_BB                        ((uint32_t)0x00000028UL)
  82 #define MXC_R_I2CM_OFFS_AHB_RETRY                 ((uint32_t)0x00000030UL)
  83
  84 #define MXC_R_I2CM_FIFO_OFFS_TRANS                ((uint32_t)0x00000000UL)
  85 #define MXC_R_I2CM_FIFO_OFFS_RSLTS                ((uint32_t)0x00000800UL)
  86
  87 /*
  88    Field positions and masks for module I2CM.
  89 */
  90 #define MXC_S_I2CM_TRANS_TAG_START                0x000
  91 #define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK           0x100
  92 #define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK          0x200
  93 #define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT         0x400
  94 #define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK          0x500
  95 #define MXC_S_I2CM_TRANS_TAG_STOP                 0x700
  96 #define MXC_S_I2CM_RSTLS_TAG_DATA                 0x100
  97 #define MXC_S_I2CM_RSTLS_TAG_EMPTY                0x200
  98
  99 #define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS               0
 100 #define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV                   ((uint32_t)(0x000000FFUL << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS))
 101 #define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS                   8
 102 #define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT                       ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS))
 103 #define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS                   20
 104 #define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT                       ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS))
 105
 106 #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS                   16
 107 #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT                       ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS))
 108 #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS                 24
 109 #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN                     ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS))
 110
 111 #define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS                      2
 112 #define MXC_F_I2CM_CTRL_TX_FIFO_EN                          ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS))
 113 #define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS                      3
 114 #define MXC_F_I2CM_CTRL_RX_FIFO_EN                          ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS))
 115 #define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS                   7
 116 #define MXC_F_I2CM_CTRL_MSTR_RESET_EN                       ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS))
 117
 118 #define MXC_F_I2CM_TRANS_TX_START_POS                       0
 119 #define MXC_F_I2CM_TRANS_TX_START                           ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS))
 120 #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS                 1
 121 #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS                     ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS))
 122 #define MXC_F_I2CM_TRANS_TX_DONE_POS                        2
 123 #define MXC_F_I2CM_TRANS_TX_DONE                            ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS))
 124 #define MXC_F_I2CM_TRANS_TX_NACKED_POS                      3
 125 #define MXC_F_I2CM_TRANS_TX_NACKED                          ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS))
 126 #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS                 4
 127 #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR                     ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS))
 128 #define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS                     5
 129 #define MXC_F_I2CM_TRANS_TX_TIMEOUT                         ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS))
 130
 131 #define MXC_F_I2CM_INTFL_TX_DONE_POS                        0
 132 #define MXC_F_I2CM_INTFL_TX_DONE                            ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS))
 133 #define MXC_F_I2CM_INTFL_TX_NACKED_POS                      1
 134 #define MXC_F_I2CM_INTFL_TX_NACKED                          ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS))
 135 #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS                 2
 136 #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR                     ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS))
 137 #define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS                     3
 138 #define MXC_F_I2CM_INTFL_TX_TIMEOUT                         ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS))
 139 #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS                  4
 140 #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS))
 141 #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS               5
 142 #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY                   ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS))
 143 #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS              6
 144 #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY                  ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS))
 145 #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS                7
 146 #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL                    ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS))
 147 #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS                8
 148 #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL                    ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS))
 149 #define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS                   9
 150 #define MXC_F_I2CM_INTFL_RX_FIFO_FULL                       ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS))
 151
 152 #define MXC_F_I2CM_INTEN_TX_DONE_POS                        0
 153 #define MXC_F_I2CM_INTEN_TX_DONE                            ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS))
 154 #define MXC_F_I2CM_INTEN_TX_NACKED_POS                      1
 155 #define MXC_F_I2CM_INTEN_TX_NACKED                          ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS))
 156 #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS                 2
 157 #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR                     ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS))
 158 #define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS                     3
 159 #define MXC_F_I2CM_INTEN_TX_TIMEOUT                         ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS))
 160 #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS                  4
 161 #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS))
 162 #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS               5
 163 #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY                   ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS))
 164 #define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS                  6
 165 #define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS))
 166 #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS                7
 167 #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL                    ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS))
 168 #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS                8
 169 #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL                    ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS))
 170 #define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS                   9
 171 #define MXC_F_I2CM_INTEN_RX_FIFO_FULL                       ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS))
 172
 173 #define MXC_F_I2CM_BB_BB_SCL_OUT_POS                        0
 174 #define MXC_F_I2CM_BB_BB_SCL_OUT                            ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS))
 175 #define MXC_F_I2CM_BB_BB_SDA_OUT_POS                        1
 176 #define MXC_F_I2CM_BB_BB_SDA_OUT                            ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS))
 177 #define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS                     2
 178 #define MXC_F_I2CM_BB_BB_SCL_IN_VAL                         ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS))
 179 #define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS                     3
 180 #define MXC_F_I2CM_BB_BB_SDA_IN_VAL                         ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS))
 181 #define MXC_F_I2CM_BB_RX_FIFO_CNT_POS                       16
 182 #define MXC_F_I2CM_BB_RX_FIFO_CNT                           ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS))
 183
 184 #ifdef __cplusplus
 185 }
 186 #endif
 187
 188 /**
 189 * @}
 190 */
 191
 192 #endif