tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/clkman_regs.h

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  33
  34 #ifndef _MXC_CLKMAN_REGS_H_
  35 #define _MXC_CLKMAN_REGS_H_
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 #include <stdint.h>
  42
  43 /**
  44  * @file  clkman_regs.h
  45  * @addtogroup clkman CLKMAN
  46  * @{
  47  */
  48
  49 /**
  50  * @brief Defines clock input selections for the phase locked loop.
  51  */
  52 typedef enum {
  53     /** Input select for high frequency crystal oscillator */
  54     MXC_E_CLKMAN_PLL_INPUT_SELECT_HFX = 0,
  55     /** Input select for 24MHz ring oscillator */
  56     MXC_E_CLKMAN_PLL_INPUT_SELECT_24MHZ_RO,
  57 } mxc_clkman_pll_input_select_t;
  58
  59 /**
  60  * @brief Defines clock input frequency for the phase locked loop.
  61  */
  62 typedef enum {
  63     /** Input frequency of 24MHz */
  64     MXC_E_CLKMAN_PLL_DIVISOR_SELECT_24MHZ = 0,
  65     /** Input frequency of 12MHz */
  66     MXC_E_CLKMAN_PLL_DIVISOR_SELECT_12MHZ,
  67     /** Input frequency of 8MHz */
  68     MXC_E_CLKMAN_PLL_DIVISOR_SELECT_8MHZ,
  69 } mxc_clkman_pll_divisor_select_t;
  70
  71 /**
  72  * @brief Defines terminal count for PLL stable.
  73  */
  74 typedef enum {
  75     /** Clock stable after 2^8 = 256 clock cycles */
  76     MXC_E_CLKMAN_STABILITY_COUNT_2_8_CLKS = 0,
  77     /** Clock stable after 2^9 = 512 clock cycles */
  78     MXC_E_CLKMAN_STABILITY_COUNT_2_9_CLKS,
  79     /** Clock stable after 2^10 = 1024 clock cycles */
  80     MXC_E_CLKMAN_STABILITY_COUNT_2_10_CLKS,
  81     /** Clock stable after 2^11 = 2048 clock cycles */
  82     MXC_E_CLKMAN_STABILITY_COUNT_2_11_CLKS,
  83     /** Clock stable after 2^12 = 4096 clock cycles */
  84     MXC_E_CLKMAN_STABILITY_COUNT_2_12_CLKS,
  85     /** Clock stable after 2^13 = 8192 clock cycles */
  86     MXC_E_CLKMAN_STABILITY_COUNT_2_13_CLKS,
  87     /** Clock stable after 2^14 = 16384 clock cycles */
  88     MXC_E_CLKMAN_STABILITY_COUNT_2_14_CLKS,
  89     /** Clock stable after 2^15 = 32768 clock cycles */
  90     MXC_E_CLKMAN_STABILITY_COUNT_2_15_CLKS,
  91     /** Clock stable after 2^16 = 65536 clock cycles */
  92     MXC_E_CLKMAN_STABILITY_COUNT_2_16_CLKS,
  93     /** Clock stable after 2^17 = 131072 clock cycles */
  94     MXC_E_CLKMAN_STABILITY_COUNT_2_17_CLKS,
  95     /** Clock stable after 2^18 = 262144 clock cycles */
  96     MXC_E_CLKMAN_STABILITY_COUNT_2_18_CLKS,
  97     /** Clock stable after 2^19 = 524288 clock cycles */
  98     MXC_E_CLKMAN_STABILITY_COUNT_2_19_CLKS,
  99     /** Clock stable after 2^20 = 1048576 clock cycles */
 100     MXC_E_CLKMAN_STABILITY_COUNT_2_20_CLKS,
 101     /** Clock stable after 2^21 = 2097152 clock cycles */
 102     MXC_E_CLKMAN_STABILITY_COUNT_2_21_CLKS,
 103     /** Clock stable after 2^22 = 4194304 clock cycles */
 104     MXC_E_CLKMAN_STABILITY_COUNT_2_22_CLKS,
 105     /** Clock stable after 2^23 = 8388608 clock cycles */
 106     MXC_E_CLKMAN_STABILITY_COUNT_2_23_CLKS
 107 } mxc_clkman_stability_count_t;
 108
 109 /**
 110  * @brief Defines clock source selections for system clock.
 111  */
 112 typedef enum {
 113     /** Clock select for 24MHz ring oscillator divided by 8 (3MHz) */
 114     MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8 = 0,
 115     /** Clock select for 24MHz ring oscillator */
 116     MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO,
 117     /** Clock select for high frequency crystal oscillator */
 118     MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX,
 119     /** Clock select for 48MHz phase locked loop output divided by 2 (24MHz) */
 120     MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2
 121 } mxc_clkman_system_source_select_t;
 122
 123 /**
 124  * @brief Defines clock source selections for analog to digital converter clock.
 125  */
 126 typedef enum {
 127     /** Clock select for system clock frequency */
 128     MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM = 0,
 129     /** Clock select for 8MHz phase locked loop output */
 130     MXC_E_CLKMAN_ADC_SOURCE_SELECT_PLL_8MHZ,
 131     /** Clock select for high frequency crystal oscillator */
 132     MXC_E_CLKMAN_ADC_SOURCE_SELECT_HFX,
 133     /** Clock select for 24MHz ring oscillator */
 134     MXC_E_CLKMAN_ADC_SOURCE_SELECT_24MHZ_RO,
 135 } mxc_clkman_adc_source_select_t;
 136
 137 /**
 138  * @brief Defines clock source selections for watchdog timer clock.
 139  */
 140 typedef enum {
 141     /** Clock select for system clock frequency */
 142     MXC_E_CLKMAN_WDT_SOURCE_SELECT_SYSTEM = 0,
 143     /** Clock select for 8MHz phase locked loop output */
 144     MXC_E_CLKMAN_WDT_SOURCE_SELECT_RTC,
 145     /** Clock select for high frequency crystal oscillator */
 146     MXC_E_CLKMAN_WDT_SOURCE_SELECT_24MHZ_RO,
 147     /** Clock select for 24MHz ring oscillator */
 148     MXC_E_CLKMAN_WDT_SOURCE_SELECT_NANO,
 149 } mxc_clkman_wdt_source_select_t;
 150
 151 /**
 152  * @brief Defines clock scales for various clocks.
 153  */
 154 typedef enum {
 155     /** Clock disabled */
 156     MXC_E_CLKMAN_CLK_SCALE_DISABLED = 0,
 157     /** Clock enabled */
 158     MXC_E_CLKMAN_CLK_SCALE_ENABLED,
 159     /** Clock scale for dividing by 2 */
 160     MXC_E_CLKMAN_CLK_SCALE_DIV_2,
 161     /** Clock scale for dividing by 4 */
 162     MXC_E_CLKMAN_CLK_SCALE_DIV_4,
 163     /** Clock scale for dividing by 8 */
 164     MXC_E_CLKMAN_CLK_SCALE_DIV_8,
 165     /** Clock scale for dividing by 16 */
 166     MXC_E_CLKMAN_CLK_SCALE_DIV_16,
 167     /** Clock scale for dividing by 32 */
 168     MXC_E_CLKMAN_CLK_SCALE_DIV_32,
 169     /** Clock scale for dividing by 64 */
 170     MXC_E_CLKMAN_CLK_SCALE_DIV_64,
 171     /** Clock scale for dividing by 128 */
 172     MXC_E_CLKMAN_CLK_SCALE_DIV_128,
 173     /** Clock scale for dividing by 256 */
 174     MXC_E_CLKMAN_CLK_SCALE_DIV_256
 175 } mxc_clkman_clk_scale_t;
 176
 177 /**
 178  * @brief Defines Setting of the Clock Gates .
 179  */
 180 typedef enum {
 181     /** Clock Gater is Off */
 182     MXC_E_CLKMAN_CLK_GATE_OFF  = 0,
 183     /** Clock Gater is Dynamic */
 184     MXC_E_CLKMAN_CLK_GATE_DYNAMIC,
 185     /** Clock Gater is On */
 186     MXC_E_CLKMAN_CLK_GATE_ON
 187 } mxc_clkman_clk_gate_t;
 188
 189 /*                                               Offset   Register Description
 190                                                  ======   ===================================================================== */
 191 typedef struct {
 192     __IO uint32_t clk_config;                /*  0x0000   System Clock Configuration                                  */
 193     __IO uint32_t clk_ctrl;                  /*  0x0004   System Clock Controls                                                 */
 194     __IO uint32_t intfl;                     /*  0x0008   Interrupt Flags                                             */
 195     __IO uint32_t inten;                     /*  0x000C   Interrupt Enable/Disable Controls                           */
 196     __IO uint32_t trim_calc;                 /*  0x0010   Trim Calculation Controls                                   */
 197     __I uint32_t rsv0014[4];                 /*  0x0014                                                               */
 198     __IO uint32_t i2c_timer_ctrl;            /*  0x0024   I2C Timer Control                                           */
 199     __I uint32_t rsv0028[6];                 /*  0x0028                                                               */
 200     __IO uint32_t clk_ctrl_0_system;         /*  0x0040   Control Settings for CLK0 - System Clock                    */
 201     __IO uint32_t clk_ctrl_1_gpio;           /*  0x0044   Control Settings for CLK1 - GPIO Module Clock               */
 202     __IO uint32_t clk_ctrl_2_pt;             /*  0x0048   Control Settings for CLK2 - Pulse Train Module Clock        */
 203     __IO uint32_t clk_ctrl_3_spi0;           /*  0x004C   Control Settings for CLK3 - SPI0 Master Clock               */
 204     __IO uint32_t clk_ctrl_4_spi1;           /*  0x0050   Control Settings for CLK4 - SPI1 Master Clock               */
 205     __IO uint32_t clk_ctrl_5_spi2;           /*  0x0054   Control Settings for CLK5 - SPI2 Master Clock               */
 206     __IO uint32_t clk_ctrl_6_i2cm;           /*  0x0058   Control Settings for CLK6 - Clock for all I2C Masters       */
 207     __IO uint32_t clk_ctrl_7_i2cs;           /*  0x005C   Control Settings for CLK7 - I2C Slave Clock                 */
 208     __IO uint32_t clk_ctrl_8_lcd_chpump;     /*  0x0060   Control Settings for CLK8 - LCD Charge Pump Clock           */
 209     __IO uint32_t clk_ctrl_9_puf;            /*  0x0064   Control Settings for CLK9 - PUF Clock                       */
 210     __IO uint32_t clk_ctrl_10_prng;          /*  0x0068   Control Settings for CLK10 - PRNG Clock                     */
 211     __IO uint32_t clk_ctrl_11_wdt0;          /*  0x006C   Control Settings for CLK11 - Watchdog Timer 0 ScaledSysClk  */
 212     __IO uint32_t clk_ctrl_12_wdt1;          /*  0x0070   Control Settings for CLK12 - Watchdog Timer 1 ScaledSysClk  */
 213     __IO uint32_t clk_ctrl_13_rtc_int_sync;  /*  0x0074   Control Settings for CLK13 - RTC Interrupt Sync Clock       */
 214     __IO uint32_t clk_ctrl_14_dac0;          /*  0x0078   Control Settings for CLK14 - 12-bit DAC 0 Clock             */
 215     __IO uint32_t clk_ctrl_15_dac1;          /*  0x007C   Control Settings for CLK15 - 12-bit DAC 1 Clock             */
 216     __IO uint32_t clk_ctrl_16_dac2;          /*  0x0080   Control Settings for CLK16 - 8-bit DAC 0 Clock              */
 217     __IO uint32_t clk_ctrl_17_dac3;          /*  0x0084   Control Settings for CLK17 - 8-bit DAC 1 Clock              */
 218     __I uint32_t rsv0088[30];                /*  0x0088                                                               */
 219     __IO uint32_t crypt_clk_ctrl_0_aes;      /*  0x0100   Control Settings for Crypto Clock 0 - AES                   */
 220     __IO uint32_t crypt_clk_ctrl_1_maa;      /*  0x0104   Control Settings for Crypto Clock 1 - MAA                   */
 221     __IO uint32_t crypt_clk_ctrl_2_prng;     /*  0x0108   Control Settings for Crypto Clock 2 - PRNG                  */
 222     __I uint32_t rsv010C[13];                /*  0x010C                                                               */
 223     __IO uint32_t clk_gate_ctrl0;            /*  0x0140   Dynamic Clock Gating Control Register 0                     */
 224     __IO uint32_t clk_gate_ctrl1;            /*  0x0144   Dynamic Clock Gating Control Register 1                     */
 225     __IO uint32_t clk_gate_ctrl2;            /*  0x0148   Dynamic Clock Gating Control Register 2                     */
 226 } mxc_clkman_regs_t;
 227
 228 /*
 229    Register offsets for module CLKMAN.
 230 */
 231 #define MXC_R_CLKMAN_OFFS_CLK_CONFIG                ((uint32_t)0x00000000UL)
 232 #define MXC_R_CLKMAN_OFFS_CLK_CTRL                  ((uint32_t)0x00000004UL)
 233 #define MXC_R_CLKMAN_OFFS_INTFL                     ((uint32_t)0x00000008UL)
 234 #define MXC_R_CLKMAN_OFFS_INTEN                     ((uint32_t)0x0000000CUL)
 235 #define MXC_R_CLKMAN_OFFS_TRIM_CALC                 ((uint32_t)0x00000010UL)
 236 #define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL            ((uint32_t)0x00000024UL)
 237 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_0_SYSTEM         ((uint32_t)0x00000040UL)
 238 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_1_GPIO           ((uint32_t)0x00000044UL)
 239 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_2_PT             ((uint32_t)0x00000048UL)
 240 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_3_SPI0           ((uint32_t)0x0000004CUL)
 241 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_4_SPI1           ((uint32_t)0x00000050UL)
 242 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_5_SPI2           ((uint32_t)0x00000054UL)
 243 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_6_I2CM           ((uint32_t)0x00000058UL)
 244 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_7_I2CS           ((uint32_t)0x0000005CUL)
 245 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_8_LCD_CHPUMP     ((uint32_t)0x00000060UL)
 246 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_9_PUF            ((uint32_t)0x00000064UL)
 247 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_10_PRNG          ((uint32_t)0x00000068UL)
 248 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_11_WDT0          ((uint32_t)0x0000006CUL)
 249 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_12_WDT1          ((uint32_t)0x00000070UL)
 250 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_13_RTC_INT_SYNC  ((uint32_t)0x00000074UL)
 251 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_14_DAC0          ((uint32_t)0x00000078UL)
 252 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_15_DAC1          ((uint32_t)0x0000007CUL)
 253 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_16_DAC2          ((uint32_t)0x00000080UL)
 254 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_17_DAC3          ((uint32_t)0x00000084UL)
 255 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES      ((uint32_t)0x00000100UL)
 256 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA      ((uint32_t)0x00000104UL)
 257 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG     ((uint32_t)0x00000108UL)
 258 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0            ((uint32_t)0x00000140UL)
 259 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1            ((uint32_t)0x00000144UL)
 260 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2            ((uint32_t)0x00000148UL)
 261
 262 /*
 263    Field positions and masks for module CLKMAN.
 264 */
 265 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS                  0
 266 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE                      ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS))
 267 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS                  1
 268 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS                      ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS))
 269 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS             2
 270 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE                 ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS))
 271 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS               4
 272 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST                   ((uint32_t)(0x0000001FUL << MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS))
 273 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS              9
 274 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL                  ((uint32_t)(0x00000007UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS))
 275 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS                  12
 276 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE                      ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS))
 277 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS                 13
 278 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N                     ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS))
 279 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS            14
 280 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT                ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS))
 281 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS          16
 282 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS))
 283 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS             18
 284 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE                 ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS))
 285 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS                  19
 286 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS                      ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS))
 287 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS         20
 288 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS))
 289 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS               24
 290 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE                   ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS))
 291 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS              25
 292 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N                  ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS))
 293 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS      28
 294 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT          ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
 295
 296 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS          1
 297 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
 298 #define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS              3
 299 #define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE                  ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS))
 300 #define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS                    4
 301 #define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N                        ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS))
 302 #define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS                    8
 303 #define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N                        ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS))
 304 #define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS             9
 305 #define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT                 ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))
 306 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS                 12
 307 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N                     ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS))
 308 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS              16
 309 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N                  ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS))
 310 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS       17
 311 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT           ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS))
 312 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS              20
 313 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N                  ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS))
 314 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS       21
 315 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT           ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS))
 316 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS                     24
 317 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE                         ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS))
 318
 319 #define MXC_F_CLKMAN_INTFL_RING_STABLE_POS                      0
 320 #define MXC_F_CLKMAN_INTFL_RING_STABLE                          ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_RING_STABLE_POS))
 321 #define MXC_F_CLKMAN_INTFL_PLL_STABLE_POS                       1
 322 #define MXC_F_CLKMAN_INTFL_PLL_STABLE                           ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_PLL_STABLE_POS))
 323 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS                    2
 324 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE                        ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS))
 325
 326 #define MXC_F_CLKMAN_INTEN_RING_STABLE_POS                      0
 327 #define MXC_F_CLKMAN_INTEN_RING_STABLE                          ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_RING_STABLE_POS))
 328 #define MXC_F_CLKMAN_INTEN_PLL_STABLE_POS                       1
 329 #define MXC_F_CLKMAN_INTEN_PLL_STABLE                           ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_PLL_STABLE_POS))
 330 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS                    2
 331 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE                        ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS))
 332
 333 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS                 0
 334 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL                     ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS))
 335 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS              1
 336 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START                  ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS))
 337 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS          2
 338 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED              ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS))
 339 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS                  3
 340 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE                      ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS))
 341 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS            16
 342 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS                ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS))
 343
 344 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS        0
 345 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN            ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS))
 346
 347 #define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS        0
 348 #define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS))
 349
 350 #define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS         0
 351 #define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS))
 352
 353 #define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS    0
 354 #define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE        ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS))
 355
 356 #define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS         0
 357 #define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS))
 358
 359 #define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS         0
 360 #define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS))
 361
 362 #define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS         0
 363 #define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS))
 364
 365 #define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS         0
 366 #define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS))
 367
 368 #define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS         0
 369 #define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS))
 370
 371 #define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS    0
 372 #define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE        ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS))
 373
 374 #define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS           0
 375 #define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE               ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS))
 376
 377 #define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS        0
 378 #define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS))
 379
 380 #define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS   0
 381 #define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE       ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS))
 382
 383 #define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS   0
 384 #define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE       ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS))
 385
 386 #define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS 0
 387 #define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE     ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS))
 388
 389 #define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS        0
 390 #define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS))
 391
 392 #define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS        0
 393 #define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS))
 394
 395 #define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS        0
 396 #define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS))
 397
 398 #define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS        0
 399 #define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS))
 400
 401 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS     0
 402 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE         ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS))
 403
 404 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS    0
 405 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE        ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS))
 406
 407 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS   0
 408 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE       ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS))
 409
 410 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS           0
 411 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS))
 412 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS        2
 413 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS))
 414 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS        4
 415 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS))
 416 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS         6
 417 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER             ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS))
 418 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS          8
 419 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS))
 420 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS    10
 421 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER        ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS))
 422 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS        12
 423 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS))
 424 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS         14
 425 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER             ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS))
 426 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS         16
 427 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER             ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS))
 428 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS        18
 429 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS))
 430 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS        20
 431 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS))
 432 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS        22
 433 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS))
 434 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS        24
 435 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS))
 436 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS     26
 437 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER         ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS))
 438 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS     28
 439 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER         ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS))
 440 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS           30
 441 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS))
 442
 443 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS       0
 444 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER           ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS))
 445 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS           2
 446 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS))
 447 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS       4
 448 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER           ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS))
 449 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS       6
 450 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER           ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS))
 451 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS        8
 452 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS))
 453 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS        10
 454 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS))
 455 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS           12
 456 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS))
 457 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS           14
 458 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS))
 459 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS          16
 460 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS))
 461 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS    18
 462 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER        ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS))
 463 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS          20
 464 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS))
 465 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS          22
 466 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS))
 467 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS          24
 468 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS))
 469 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS         26
 470 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER             ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS))
 471 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS         28
 472 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER             ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS))
 473 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS          30
 474 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS))
 475
 476 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS           0
 477 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS))
 478 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS           2
 479 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS))
 480 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS        4
 481 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS))
 482 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS           6
 483 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS))
 484
 485 #ifdef __cplusplus
 486 }
 487 #endif
 488
 489 /**
 490 * @}
 491 */
 492
 493 #endif   /* _MXC_CLKMAN_REGS_H_ */