tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.s

   1 ;/*****************************************************************************
   2 ; * @file:    startup_MKL25Z4.s
   3 ; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
   4 ; *           MKL25Z4
   5 ; * @version: 1.1
   6 ; * @date:    2012-6-21
   7 ; *
   8 ; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
   9 ;*
  10 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
  11 ; *
  12 ; *****************************************************************************/
  13
  14
  15 ; <h> Stack Configuration
  16 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
  17 ; </h>
  18
  19 Stack_Size      EQU     0x00000400
  20
  21                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
  22                 EXPORT  __initial_sp
  23
  24 Stack_Mem       SPACE   Stack_Size
  25 __initial_sp        EQU     0x20003000  ; Top of RAM
  26
  27
  28 Heap_Size       EQU     0x00000000
  29
  30                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
  31                 EXPORT  __heap_base
  32                 EXPORT  __heap_limit
  33
  34 __heap_base
  35 Heap_Mem        SPACE   Heap_Size
  36 __heap_limit
  37
  38                 PRESERVE8
  39                 THUMB
  40
  41
  42 ; Vector Table Mapped to Address 0 at Reset
  43
  44                 AREA    RESET, DATA, READONLY
  45                 EXPORT  __Vectors
  46                 EXPORT  __Vectors_End
  47                 EXPORT  __Vectors_Size
  48
  49 __Vectors       DCD     __initial_sp  ; Top of Stack
  50                 DCD     Reset_Handler  ; Reset Handler
  51                 DCD     NMI_Handler  ; NMI Handler
  52                 DCD     HardFault_Handler  ; Hard Fault Handler
  53                 DCD     0  ; Reserved
  54                 DCD     0  ; Reserved
  55                 DCD     0  ; Reserved
  56                 DCD     0  ; Reserved
  57                 DCD     0  ; Reserved
  58                 DCD     0  ; Reserved
  59                 DCD     0  ; Reserved
  60                 DCD     SVC_Handler  ; SVCall Handler
  61                 DCD     0  ; Reserved
  62                 DCD     0  ; Reserved
  63                 DCD     PendSV_Handler  ; PendSV Handler
  64                 DCD     SysTick_Handler  ; SysTick Handler
  65
  66                 ; External Interrupts
  67                 DCD     DMA0_IRQHandler  ; DMA channel 0 transfer complete interrupt
  68                 DCD     DMA1_IRQHandler  ; DMA channel 1 transfer complete interrupt
  69                 DCD     DMA2_IRQHandler  ; DMA channel 2 transfer complete interrupt
  70                 DCD     DMA3_IRQHandler  ; DMA channel 3 transfer complete interrupt
  71                 DCD     Reserved20_IRQHandler  ; Reserved interrupt 20
  72                 DCD     FTFA_IRQHandler  ; FTFA interrupt
  73                 DCD     LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
  74                 DCD     LLW_IRQHandler  ; Low Leakage Wakeup
  75                 DCD     I2C0_IRQHandler  ; I2C0 interrupt
  76                 DCD     I2C1_IRQHandler  ; I2C0 interrupt 25
  77                 DCD     SPI0_IRQHandler  ; SPI0 interrupt
  78                 DCD     SPI1_IRQHandler  ; SPI1 interrupt
  79                 DCD     UART0_IRQHandler  ; UART0 status/error interrupt
  80                 DCD     UART1_IRQHandler  ; UART1 status/error interrupt
  81                 DCD     UART2_IRQHandler  ; UART2 status/error interrupt
  82                 DCD     ADC0_IRQHandler  ; ADC0 interrupt
  83                 DCD     CMP0_IRQHandler  ; CMP0 interrupt
  84                 DCD     TPM0_IRQHandler  ; TPM0 fault, overflow and channels interrupt
  85                 DCD     TPM1_IRQHandler  ; TPM1 fault, overflow and channels interrupt
  86                 DCD     TPM2_IRQHandler  ; TPM2 fault, overflow and channels interrupt
  87                 DCD     RTC_IRQHandler  ; RTC interrupt
  88                 DCD     RTC_Seconds_IRQHandler  ; RTC seconds interrupt
  89                 DCD     PIT_IRQHandler  ; PIT timer interrupt
  90                 DCD     Reserved39_IRQHandler  ; Reserved interrupt 39
  91                 DCD     USB0_IRQHandler  ; USB0 interrupt
  92                 DCD     DAC0_IRQHandler  ; DAC interrupt
  93                 DCD     TSI0_IRQHandler  ; TSI0 interrupt
  94                 DCD     MCG_IRQHandler  ; MCG interrupt
  95                 DCD     LPTimer_IRQHandler  ; LPTimer interrupt
  96                 DCD     Reserved45_IRQHandler  ; Reserved interrupt 45
  97                 DCD     PORTA_IRQHandler  ; Port A interrupt
  98                 DCD     PORTD_IRQHandler  ; Port D interrupt
  99 __Vectors_End
 100
 101 __Vectors_Size  EQU     __Vectors_End - __Vectors
 102
 103 ; <h> Flash Configuration
 104 ;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
 105 ;   <i> and security information that allows the MCU to restrict acces to the FTFL module.
 106 ;   <h> Backdoor Comparison Key
 107 ;     <o0>  Backdoor Key 0  <0x0-0xFF:2>
 108 ;     <o1>  Backdoor Key 1  <0x0-0xFF:2>
 109 ;     <o2>  Backdoor Key 2  <0x0-0xFF:2>
 110 ;     <o3>  Backdoor Key 3  <0x0-0xFF:2>
 111 ;     <o4>  Backdoor Key 4  <0x0-0xFF:2>
 112 ;     <o5>  Backdoor Key 5  <0x0-0xFF:2>
 113 ;     <o6>  Backdoor Key 6  <0x0-0xFF:2>
 114 ;     <o7>  Backdoor Key 7  <0x0-0xFF:2>
 115 BackDoorK0      EQU     0xFF
 116 BackDoorK1      EQU     0xFF
 117 BackDoorK2      EQU     0xFF
 118 BackDoorK3      EQU     0xFF
 119 BackDoorK4      EQU     0xFF
 120 BackDoorK5      EQU     0xFF
 121 BackDoorK6      EQU     0xFF
 122 BackDoorK7      EQU     0xFF
 123 ;   </h>
 124 ;   <h> Program flash protection bytes (FPROT)
 125 ;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
 126 ;     <i> Each bit protects a 1/32 region of the program flash memory.
 127 ;     <h> FPROT0
 128 ;       <i> Program flash protection bytes
 129 ;       <i> 1/32 - 8/32 region
 130 ;       <o.0>   FPROT0.0
 131 ;       <o.1>   FPROT0.1
 132 ;       <o.2>   FPROT0.2
 133 ;       <o.3>   FPROT0.3
 134 ;       <o.4>   FPROT0.4
 135 ;       <o.5>   FPROT0.5
 136 ;       <o.6>   FPROT0.6
 137 ;       <o.7>   FPROT0.7
 138 nFPROT0         EQU     0x00
 139 FPROT0          EQU     nFPROT0:EOR:0xFF
 140 ;     </h>
 141 ;     <h> FPROT1
 142 ;       <i> Program Flash Region Protect Register 1
 143 ;       <i> 9/32 - 16/32 region
 144 ;       <o.0>   FPROT1.0
 145 ;       <o.1>   FPROT1.1
 146 ;       <o.2>   FPROT1.2
 147 ;       <o.3>   FPROT1.3
 148 ;       <o.4>   FPROT1.4
 149 ;       <o.5>   FPROT1.5
 150 ;       <o.6>   FPROT1.6
 151 ;       <o.7>   FPROT1.7
 152 nFPROT1         EQU     0x00
 153 FPROT1          EQU     nFPROT1:EOR:0xFF
 154 ;     </h>
 155 ;     <h> FPROT2
 156 ;       <i> Program Flash Region Protect Register 2
 157 ;       <i> 17/32 - 24/32 region
 158 ;       <o.0>   FPROT2.0
 159 ;       <o.1>   FPROT2.1
 160 ;       <o.2>   FPROT2.2
 161 ;       <o.3>   FPROT2.3
 162 ;       <o.4>   FPROT2.4
 163 ;       <o.5>   FPROT2.5
 164 ;       <o.6>   FPROT2.6
 165 ;       <o.7>   FPROT2.7
 166 nFPROT2         EQU     0x00
 167 FPROT2          EQU     nFPROT2:EOR:0xFF
 168 ;     </h>
 169 ;     <h> FPROT3
 170 ;       <i> Program Flash Region Protect Register 3
 171 ;       <i> 25/32 - 32/32 region
 172 ;       <o.0>   FPROT3.0
 173 ;       <o.1>   FPROT3.1
 174 ;       <o.2>   FPROT3.2
 175 ;       <o.3>   FPROT3.3
 176 ;       <o.4>   FPROT3.4
 177 ;       <o.5>   FPROT3.5
 178 ;       <o.6>   FPROT3.6
 179 ;       <o.7>   FPROT3.7
 180 nFPROT3         EQU     0x00
 181 FPROT3          EQU     nFPROT3:EOR:0xFF
 182 ;     </h>
 183 ;   </h>
 184 ;   </h>
 185 ;   <h> Flash nonvolatile option byte (FOPT)
 186 ;     <i> Allows the user to customize the operation of the MCU at boot time.
 187 ;     <o.0>  LPBOOT0
 188 ;       <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
 189 ;       <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
 190 ;     <o.4>  LPBOOT1
 191 ;       <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
 192 ;       <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
 193 ;     <o.2>  NMI_DIS
 194 ;       <0=> NMI interrupts are always blocked
 195 ;       <1=> NMI pin/interrupts reset default to enabled
 196 ;     <o.3>  RESET_PIN_CFG
 197 ;       <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
 198 ;       <1=> RESET pin is dedicated
 199 ;     <o.3>  FAST_INIT
 200 ;       <0=> Slower initialization
 201 ;       <1=> Fast Initialization
 202 FOPT            EQU     0xFF
 203 ;   </h>
 204 ;   <h> Flash security byte (FSEC)
 205 ;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
 206 ;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
 207 ;     <o.0..1> SEC
 208 ;       <2=> MCU security status is unsecure
 209 ;       <3=> MCU security status is secure
 210 ;         <i> Flash Security
 211 ;         <i> This bits define the security state of the MCU.
 212 ;     <o.2..3> FSLACC
 213 ;       <2=> Freescale factory access denied
 214 ;       <3=> Freescale factory access granted
 215 ;         <i> Freescale Failure Analysis Access Code
 216 ;         <i> This bits define the security state of the MCU.
 217 ;     <o.4..5> MEEN
 218 ;       <2=> Mass erase is disabled
 219 ;       <3=> Mass erase is enabled
 220 ;         <i> Mass Erase Enable Bits
 221 ;         <i> Enables and disables mass erase capability of the FTFL module
 222 ;     <o.6..7> KEYEN
 223 ;       <2=> Backdoor key access enabled
 224 ;       <3=> Backdoor key access disabled
 225 ;         <i> Backdoor key Security Enable
 226 ;         <i> These bits enable and disable backdoor key access to the FTFL module.
 227 FSEC            EQU     0xFE
 228 ;   </h>
 229
 230                 IF      :LNOT::DEF:RAM_TARGET
 231                 AREA    |.ARM.__at_0x400|, CODE, READONLY
 232                 DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
 233                 DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
 234                 DCB     FPROT0,     FPROT1,     FPROT2,     FPROT3
 235                 DCB     FSEC,       FOPT,       0xFF,     0xFF
 236                 ENDIF
 237
 238                 AREA    |.text|, CODE, READONLY
 239
 240
 241 ; Reset Handler
 242
 243 Reset_Handler   PROC
 244                 EXPORT  Reset_Handler             [WEAK]
 245                 IMPORT  SystemInit
 246                 IMPORT  __main
 247                 LDR     R0, =SystemInit
 248                 BLX     R0
 249                 LDR     R0, =__main
 250                 BX      R0
 251                 ENDP
 252
 253
 254 ; Dummy Exception Handlers (infinite loops which can be modified)
 255
 256 NMI_Handler     PROC
 257                 EXPORT  NMI_Handler               [WEAK]
 258                 B       .
 259                 ENDP
 260 HardFault_Handler\
 261                 PROC
 262                 EXPORT  HardFault_Handler         [WEAK]
 263                 B       .
 264                 ENDP
 265 SVC_Handler     PROC
 266                 EXPORT  SVC_Handler               [WEAK]
 267                 B       .
 268                 ENDP
 269 PendSV_Handler  PROC
 270                 EXPORT  PendSV_Handler            [WEAK]
 271                 B       .
 272                 ENDP
 273 SysTick_Handler PROC
 274                 EXPORT  SysTick_Handler           [WEAK]
 275                 B       .
 276                 ENDP
 277
 278 Default_Handler PROC
 279                 EXPORT  DMA0_IRQHandler     [WEAK]
 280                 EXPORT  DMA1_IRQHandler     [WEAK]
 281                 EXPORT  DMA2_IRQHandler     [WEAK]
 282                 EXPORT  DMA3_IRQHandler     [WEAK]
 283                 EXPORT  Reserved20_IRQHandler     [WEAK]
 284                 EXPORT  FTFA_IRQHandler     [WEAK]
 285                 EXPORT  LVD_LVW_IRQHandler     [WEAK]
 286                 EXPORT  LLW_IRQHandler     [WEAK]
 287                 EXPORT  I2C0_IRQHandler     [WEAK]
 288                 EXPORT  I2C1_IRQHandler     [WEAK]
 289                 EXPORT  SPI0_IRQHandler     [WEAK]
 290                 EXPORT  SPI1_IRQHandler     [WEAK]
 291                 EXPORT  UART0_IRQHandler     [WEAK]
 292                 EXPORT  UART1_IRQHandler     [WEAK]
 293                 EXPORT  UART2_IRQHandler     [WEAK]
 294                 EXPORT  ADC0_IRQHandler     [WEAK]
 295                 EXPORT  CMP0_IRQHandler     [WEAK]
 296                 EXPORT  TPM0_IRQHandler     [WEAK]
 297                 EXPORT  TPM1_IRQHandler     [WEAK]
 298                 EXPORT  TPM2_IRQHandler     [WEAK]
 299                 EXPORT  RTC_IRQHandler     [WEAK]
 300                 EXPORT  RTC_Seconds_IRQHandler     [WEAK]
 301                 EXPORT  PIT_IRQHandler     [WEAK]
 302                 EXPORT  Reserved39_IRQHandler     [WEAK]
 303                 EXPORT  USB0_IRQHandler     [WEAK]
 304                 EXPORT  DAC0_IRQHandler     [WEAK]
 305                 EXPORT  TSI0_IRQHandler     [WEAK]
 306                 EXPORT  MCG_IRQHandler     [WEAK]
 307                 EXPORT  LPTimer_IRQHandler     [WEAK]
 308                 EXPORT  Reserved45_IRQHandler     [WEAK]
 309                 EXPORT  PORTA_IRQHandler     [WEAK]
 310                 EXPORT  PORTD_IRQHandler     [WEAK]
 311                 EXPORT  DefaultISR                      [WEAK]
 312
 313 DMA0_IRQHandler
 314 DMA1_IRQHandler
 315 DMA2_IRQHandler
 316 DMA3_IRQHandler
 317 Reserved20_IRQHandler
 318 FTFA_IRQHandler
 319 LVD_LVW_IRQHandler
 320 LLW_IRQHandler
 321 I2C0_IRQHandler
 322 I2C1_IRQHandler
 323 SPI0_IRQHandler
 324 SPI1_IRQHandler
 325 UART0_IRQHandler
 326 UART1_IRQHandler
 327 UART2_IRQHandler
 328 ADC0_IRQHandler
 329 CMP0_IRQHandler
 330 TPM0_IRQHandler
 331 TPM1_IRQHandler
 332 TPM2_IRQHandler
 333 RTC_IRQHandler
 334 RTC_Seconds_IRQHandler
 335 PIT_IRQHandler
 336 Reserved39_IRQHandler
 337 USB0_IRQHandler
 338 DAC0_IRQHandler
 339 TSI0_IRQHandler
 340 MCG_IRQHandler
 341 LPTimer_IRQHandler
 342 Reserved45_IRQHandler
 343 PORTA_IRQHandler
 344 PORTD_IRQHandler
 345 DefaultISR
 346
 347                 B       .
 348
 349                 ENDP
 350
 351
 352                 ALIGN
 353                 END