tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/startup_MKL05Z4.s

   1 ;/*****************************************************************************
   2 ; * @file:    startup_MKL25Z4.s
   3 ; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
   4 ; *           MKL05Z4
   5 ; * @version: 1.1
   6 ; * @date:    2012-6-21
   7 ; *
   8 ; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
   9 ;*
  10 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
  11 ; *
  12 ; *****************************************************************************/
  13
  14 Stack_Size      EQU     0x00000400
  15
  16                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
  17                 EXPORT  __initial_sp
  18
  19 Stack_Mem       SPACE   Stack_Size
  20 __initial_sp        EQU     0x20000C00  ; Top of RAM
  21
  22
  23 Heap_Size       EQU     0x00000000
  24
  25                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
  26                 EXPORT  __heap_base
  27                 EXPORT  __heap_limit
  28
  29 __heap_base
  30 Heap_Mem        SPACE   Heap_Size
  31 __heap_limit
  32
  33                 PRESERVE8
  34                 THUMB
  35
  36
  37 ; Vector Table Mapped to Address 0 at Reset
  38
  39                 AREA    RESET, DATA, READONLY
  40                 EXPORT  __Vectors
  41                 EXPORT  __Vectors_End
  42                 EXPORT  __Vectors_Size
  43
  44 __Vectors       DCD     __initial_sp  ; Top of Stack
  45                 DCD     Reset_Handler  ; Reset Handler
  46                 DCD     NMI_Handler  ; NMI Handler
  47                 DCD     HardFault_Handler  ; Hard Fault Handler
  48                 DCD     0  ; Reserved
  49                 DCD     0  ; Reserved
  50                 DCD     0  ; Reserved
  51                 DCD     0  ; Reserved
  52                 DCD     0  ; Reserved
  53                 DCD     0  ; Reserved
  54                 DCD     0  ; Reserved
  55                 DCD     SVC_Handler  ; SVCall Handler
  56                 DCD     0  ; Reserved
  57                 DCD     0  ; Reserved
  58                 DCD     PendSV_Handler  ; PendSV Handler
  59                 DCD     SysTick_Handler  ; SysTick Handler
  60
  61                 ; External Interrupts
  62                 DCD     DMA0_IRQHandler  ; DMA channel 0 transfer complete/error interrupt
  63                 DCD     DMA1_IRQHandler  ; DMA channel 1 transfer complete/error interrupt
  64                 DCD     DMA2_IRQHandler  ; DMA channel 2 transfer complete/error interrupt
  65                 DCD     DMA3_IRQHandler  ; DMA channel 3 transfer complete/error interrupt
  66                 DCD     Reserved20_IRQHandler  ; Reserved interrupt 20
  67                 DCD     FTFA_IRQHandler  ; FTFA command complete/read collision interrupt
  68                 DCD     LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
  69                 DCD     LLW_IRQHandler  ; Low Leakage Wakeup
  70                 DCD     I2C0_IRQHandler  ; I2C0 interrupt
  71                 DCD     Reserved_25_IRQHandler  ; Reserved interrupt 25
  72                 DCD     SPI0_IRQHandler  ; SPI0 interrupt
  73                 DCD     Reserved_27_IRQHandler  ; Reserved interrupt 27
  74                 DCD     UART0_IRQHandler  ; UART0 status and error interrupt
  75                 DCD     Reserved_29_IRQHandler  ; Reserved interrupt 29
  76                 DCD     Reserved_30_IRQHandler  ; Reserved interrupt 30
  77                 DCD     ADC0_IRQHandler  ; ADC0 interrupt
  78                 DCD     CMP0_IRQHandler  ; CMP0 interrupt
  79                 DCD     TPM0_IRQHandler  ; TPM0 fault, overflow and channels interrupt
  80                 DCD     TPM1_IRQHandler  ; TPM1 fault, overflow and channels interrupt
  81                 DCD     Reserved_35_IRQHandler  ; Reserved interrupt 35
  82                 DCD     RTC_IRQHandler  ; RTC interrupt
  83                 DCD     RTC_Seconds_IRQHandler  ; RTC seconds interrupt
  84                 DCD     PIT_IRQHandler  ; PIT timer channel 0 interrupt
  85                 DCD     Reserved_39_IRQHandler  ; Reserved interrupt 39
  86                 DCD     Reserved_40_IRQHandler  ; Reserved interrupt 40
  87                 DCD     DAC0_IRQHandler  ; DAC0 interrupt
  88                 DCD     TSI0_IRQHandler  ; TSI0 interrupt
  89                 DCD     MCG_IRQHandler  ; MCG interrupt
  90                 DCD     LPTimer_IRQHandler  ; LPTimer interrupt
  91                 DCD     Reserved_45_IRQHandler  ; Reserved interrupt 45
  92                 DCD     PORTA_IRQHandler  ; Port A interrupt
  93                 DCD     PORTB_IRQHandler  ; Port B interrupt
  94 __Vectors_End
  95
  96 __Vectors_Size  EQU     __Vectors_End - __Vectors
  97
  98 ; <h> Flash Configuration
  99 ;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
 100 ;   <i> and security information that allows the MCU to restrict acces to the FTFL module.
 101 ;   <h> Backdoor Comparison Key
 102 ;     <o0>  Backdoor Key 0  <0x0-0xFF:2>
 103 ;     <o1>  Backdoor Key 1  <0x0-0xFF:2>
 104 ;     <o2>  Backdoor Key 2  <0x0-0xFF:2>
 105 ;     <o3>  Backdoor Key 3  <0x0-0xFF:2>
 106 ;     <o4>  Backdoor Key 4  <0x0-0xFF:2>
 107 ;     <o5>  Backdoor Key 5  <0x0-0xFF:2>
 108 ;     <o6>  Backdoor Key 6  <0x0-0xFF:2>
 109 ;     <o7>  Backdoor Key 7  <0x0-0xFF:2>
 110 BackDoorK0      EQU     0xFF
 111 BackDoorK1      EQU     0xFF
 112 BackDoorK2      EQU     0xFF
 113 BackDoorK3      EQU     0xFF
 114 BackDoorK4      EQU     0xFF
 115 BackDoorK5      EQU     0xFF
 116 BackDoorK6      EQU     0xFF
 117 BackDoorK7      EQU     0xFF
 118 ;   </h>
 119 ;   <h> Program flash protection bytes (FPROT)
 120 ;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
 121 ;     <i> Each bit protects a 1/32 region of the program flash memory.
 122 ;     <h> FPROT0
 123 ;       <i> Program flash protection bytes
 124 ;       <i> 1/32 - 8/32 region
 125 ;       <o.0>   FPROT0.0
 126 ;       <o.1>   FPROT0.1
 127 ;       <o.2>   FPROT0.2
 128 ;       <o.3>   FPROT0.3
 129 ;       <o.4>   FPROT0.4
 130 ;       <o.5>   FPROT0.5
 131 ;       <o.6>   FPROT0.6
 132 ;       <o.7>   FPROT0.7
 133 nFPROT0         EQU     0x00
 134 FPROT0          EQU     nFPROT0:EOR:0xFF
 135 ;     </h>
 136 ;     <h> FPROT1
 137 ;       <i> Program Flash Region Protect Register 1
 138 ;       <i> 9/32 - 16/32 region
 139 ;       <o.0>   FPROT1.0
 140 ;       <o.1>   FPROT1.1
 141 ;       <o.2>   FPROT1.2
 142 ;       <o.3>   FPROT1.3
 143 ;       <o.4>   FPROT1.4
 144 ;       <o.5>   FPROT1.5
 145 ;       <o.6>   FPROT1.6
 146 ;       <o.7>   FPROT1.7
 147 nFPROT1         EQU     0x00
 148 FPROT1          EQU     nFPROT1:EOR:0xFF
 149 ;     </h>
 150 ;     <h> FPROT2
 151 ;       <i> Program Flash Region Protect Register 2
 152 ;       <i> 17/32 - 24/32 region
 153 ;       <o.0>   FPROT2.0
 154 ;       <o.1>   FPROT2.1
 155 ;       <o.2>   FPROT2.2
 156 ;       <o.3>   FPROT2.3
 157 ;       <o.4>   FPROT2.4
 158 ;       <o.5>   FPROT2.5
 159 ;       <o.6>   FPROT2.6
 160 ;       <o.7>   FPROT2.7
 161 nFPROT2         EQU     0x00
 162 FPROT2          EQU     nFPROT2:EOR:0xFF
 163 ;     </h>
 164 ;     <h> FPROT3
 165 ;       <i> Program Flash Region Protect Register 3
 166 ;       <i> 25/32 - 32/32 region
 167 ;       <o.0>   FPROT3.0
 168 ;       <o.1>   FPROT3.1
 169 ;       <o.2>   FPROT3.2
 170 ;       <o.3>   FPROT3.3
 171 ;       <o.4>   FPROT3.4
 172 ;       <o.5>   FPROT3.5
 173 ;       <o.6>   FPROT3.6
 174 ;       <o.7>   FPROT3.7
 175 nFPROT3         EQU     0x00
 176 FPROT3          EQU     nFPROT3:EOR:0xFF
 177 ;     </h>
 178 ;   </h>
 179 ;   </h>
 180 ;   <h> Flash nonvolatile option byte (FOPT)
 181 ;     <i> Allows the user to customize the operation of the MCU at boot time.
 182 ;     <o.0>  LPBOOT0
 183 ;       <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
 184 ;       <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
 185 ;     <o.4>  LPBOOT1
 186 ;       <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
 187 ;       <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
 188 ;     <o.2>  NMI_DIS
 189 ;       <0=> NMI interrupts are always blocked
 190 ;       <1=> NMI pin/interrupts reset default to enabled
 191 ;     <o.3>  RESET_PIN_CFG
 192 ;       <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
 193 ;       <1=> RESET pin is dedicated
 194 ;     <o.3>  FAST_INIT
 195 ;       <0=> Slower initialization
 196 ;       <1=> Fast Initialization
 197 FOPT            EQU     0xFF
 198 ;   </h>
 199 ;   <h> Flash security byte (FSEC)
 200 ;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
 201 ;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
 202 ;     <o.0..1> SEC
 203 ;       <2=> MCU security status is unsecure
 204 ;       <3=> MCU security status is secure
 205 ;         <i> Flash Security
 206 ;         <i> This bits define the security state of the MCU.
 207 ;     <o.2..3> FSLACC
 208 ;       <2=> Freescale factory access denied
 209 ;       <3=> Freescale factory access granted
 210 ;         <i> Freescale Failure Analysis Access Code
 211 ;         <i> This bits define the security state of the MCU.
 212 ;     <o.4..5> MEEN
 213 ;       <2=> Mass erase is disabled
 214 ;       <3=> Mass erase is enabled
 215 ;         <i> Mass Erase Enable Bits
 216 ;         <i> Enables and disables mass erase capability of the FTFL module
 217 ;     <o.6..7> KEYEN
 218 ;       <2=> Backdoor key access enabled
 219 ;       <3=> Backdoor key access disabled
 220 ;         <i> Backdoor key Security Enable
 221 ;         <i> These bits enable and disable backdoor key access to the FTFL module.
 222 FSEC            EQU     0xFE
 223 ;   </h>
 224
 225                 IF      :LNOT::DEF:RAM_TARGET
 226                 AREA    |.ARM.__at_0x400|, CODE, READONLY
 227                 DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
 228                 DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
 229                 DCB     FPROT0,     FPROT1,     FPROT2,     FPROT3
 230                 DCB     FSEC,       FOPT,       0xFF,     0xFF
 231                 ENDIF
 232
 233                 AREA    |.text|, CODE, READONLY
 234
 235
 236 ; Reset Handler
 237
 238 Reset_Handler   PROC
 239                 EXPORT  Reset_Handler             [WEAK]
 240                 IMPORT  SystemInit
 241                 IMPORT  __main
 242                 LDR     R0, =SystemInit
 243                 BLX     R0
 244                 LDR     R0, =__main
 245                 BX      R0
 246                 ENDP
 247
 248
 249 ; Dummy Exception Handlers (infinite loops which can be modified)
 250
 251 NMI_Handler     PROC
 252                 EXPORT  NMI_Handler               [WEAK]
 253                 B       .
 254                 ENDP
 255 HardFault_Handler\
 256                 PROC
 257                 EXPORT  HardFault_Handler         [WEAK]
 258                 B       .
 259                 ENDP
 260 SVC_Handler     PROC
 261                 EXPORT  SVC_Handler               [WEAK]
 262                 B       .
 263                 ENDP
 264 PendSV_Handler  PROC
 265                 EXPORT  PendSV_Handler            [WEAK]
 266                 B       .
 267                 ENDP
 268 SysTick_Handler PROC
 269                 EXPORT  SysTick_Handler           [WEAK]
 270                 B       .
 271                 ENDP
 272
 273 Default_Handler PROC
 274                 EXPORT  DMA0_IRQHandler     [WEAK]
 275                 EXPORT  DMA1_IRQHandler     [WEAK]
 276                 EXPORT  DMA2_IRQHandler     [WEAK]
 277                 EXPORT  DMA3_IRQHandler     [WEAK]
 278                 EXPORT  Reserved20_IRQHandler     [WEAK]
 279                 EXPORT  FTFA_IRQHandler     [WEAK]
 280                 EXPORT  LVD_LVW_IRQHandler     [WEAK]
 281                 EXPORT  LLW_IRQHandler     [WEAK]
 282                 EXPORT  I2C0_IRQHandler     [WEAK]
 283                 EXPORT  Reserved_25_IRQHandler     [WEAK]
 284                 EXPORT  SPI0_IRQHandler     [WEAK]
 285                 EXPORT  Reserved_27_IRQHandler     [WEAK]
 286                 EXPORT  UART0_IRQHandler     [WEAK]
 287                 EXPORT  Reserved_29_IRQHandler     [WEAK]
 288                 EXPORT  Reserved_30_IRQHandler     [WEAK]
 289                 EXPORT  ADC0_IRQHandler     [WEAK]
 290                 EXPORT  CMP0_IRQHandler     [WEAK]
 291                 EXPORT  TPM0_IRQHandler     [WEAK]
 292                 EXPORT  TPM1_IRQHandler     [WEAK]
 293                 EXPORT  Reserved_35_IRQHandler     [WEAK]
 294                 EXPORT  RTC_IRQHandler     [WEAK]
 295                 EXPORT  RTC_Seconds_IRQHandler     [WEAK]
 296                 EXPORT  PIT_IRQHandler     [WEAK]
 297                 EXPORT  Reserved_39_IRQHandler     [WEAK]
 298                 EXPORT  Reserved_40_IRQHandler     [WEAK]
 299                 EXPORT  DAC0_IRQHandler     [WEAK]
 300                 EXPORT  TSI0_IRQHandler     [WEAK]
 301                 EXPORT  MCG_IRQHandler     [WEAK]
 302                 EXPORT  LPTimer_IRQHandler     [WEAK]
 303                 EXPORT  Reserved_45_IRQHandler     [WEAK]
 304                 EXPORT  PORTA_IRQHandler     [WEAK]
 305                 EXPORT  PORTB_IRQHandler     [WEAK]
 306                 EXPORT  DefaultISR                      [WEAK]
 307
 308 DMA0_IRQHandler
 309 DMA1_IRQHandler
 310 DMA2_IRQHandler
 311 DMA3_IRQHandler
 312 Reserved20_IRQHandler
 313 FTFA_IRQHandler
 314 LVD_LVW_IRQHandler
 315 LLW_IRQHandler
 316 I2C0_IRQHandler
 317 Reserved_25_IRQHandler
 318 SPI0_IRQHandler
 319 Reserved_27_IRQHandler
 320 UART0_IRQHandler
 321 Reserved_29_IRQHandler
 322 Reserved_30_IRQHandler
 323 ADC0_IRQHandler
 324 CMP0_IRQHandler
 325 TPM0_IRQHandler
 326 TPM1_IRQHandler
 327 Reserved_35_IRQHandler
 328 RTC_IRQHandler
 329 RTC_Seconds_IRQHandler
 330 PIT_IRQHandler
 331 Reserved_39_IRQHandler
 332 Reserved_40_IRQHandler
 333 DAC0_IRQHandler
 334 TSI0_IRQHandler
 335 MCG_IRQHandler
 336 LPTimer_IRQHandler
 337 Reserved_45_IRQHandler
 338 PORTA_IRQHandler
 339 PORTB_IRQHandler
 340 DefaultISR
 341
 342                 B       .
 343
 344                 ENDP
 345
 346
 347                 ALIGN
 348                 END