tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/MKL05Z4.h

   1 /*
   2 ** ###################################################################
   3 **     Processors:          MKL05Z32FK4
   4 **                          MKL05Z32LC4
   5 **                          MKL05Z32VLF4
   6 **
   7 **     Compilers:           ARM Compiler
   8 **                          Freescale C/C++ for Embedded ARM
   9 **                          GNU C Compiler
  10 **                          IAR ANSI C/C++ Compiler for ARM
  11 **
  12 **     Reference manual:    KL05P48M48SF1RM, Rev.3, Sep 2012
  13 **     Version:             rev. 1.3, 2012-10-04
  14 **
  15 **     Abstract:
  16 **         CMSIS Peripheral Access Layer for MKL05Z4
  17 **
  18 **     Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved.
  19 **
  20 **     http:                 www.freescale.com
  21 **     mail:                 support@freescale.com
  22 **
  23 **     Revisions:
  24 **     - rev. 1.0 (2012-06-08)
  25 **         Initial version.
  26 **     - rev. 1.1 (2012-06-21)
  27 **         Update according to reference manual rev. 1.
  28 **     - rev. 1.2 (2012-08-01)
  29 **         Device type UARTLP changed to UART0.
  30 **         Missing PORTB_IRQn interrupt number definition added.
  31 **     - rev. 1.3 (2012-10-04)
  32 **         Update according to reference manual rev. 3.
  33 **
  34 ** ###################################################################
  35 */
  36
  37 /**
  38  * @file MKL05Z4.h
  39  * @version 1.3
  40  * @date 2012-10-04
  41  * @brief CMSIS Peripheral Access Layer for MKL05Z4
  42  *
  43  * CMSIS Peripheral Access Layer for MKL05Z4
  44  */
  45
  46 #if !defined(MKL05Z4_H_)
  47 #define MKL05Z4_H_                               /**< Symbol preventing repeated inclusion */
  48
  49 /** Memory map major version (memory maps with equal major version number are
  50  * compatible) */
  51 #define MCU_MEM_MAP_VERSION 0x0100u
  52 /** Memory map minor version */
  53 #define MCU_MEM_MAP_VERSION_MINOR 0x0003u
  54
  55
  56 /* ----------------------------------------------------------------------------
  57    -- Interrupt vector numbers
  58    ---------------------------------------------------------------------------- */
  59
  60 /**
  61  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
  62  * @{
  63  */
  64
  65 /** Interrupt Number Definitions */
  66 typedef enum IRQn {
  67   /* Core interrupts */
  68   NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
  69   HardFault_IRQn               = -13,              /**< Cortex-M0 SV Hard Fault Interrupt */
  70   SVCall_IRQn                  = -5,               /**< Cortex-M0 SV Call Interrupt */
  71   PendSV_IRQn                  = -2,               /**< Cortex-M0 Pend SV Interrupt */
  72   SysTick_IRQn                 = -1,               /**< Cortex-M0 System Tick Interrupt */
  73
  74   /* Device specific interrupts */
  75   DMA0_IRQn                    = 0,                /**< DMA channel 0 transfer complete/error interrupt */
  76   DMA1_IRQn                    = 1,                /**< DMA channel 1 transfer complete/error interrupt */
  77   DMA2_IRQn                    = 2,                /**< DMA channel 2 transfer complete/error interrupt */
  78   DMA3_IRQn                    = 3,                /**< DMA channel 3 transfer complete/error interrupt */
  79   Reserved20_IRQn              = 4,                /**< Reserved interrupt 20 */
  80   FTFA_IRQn                    = 5,                /**< FTFA command complete/read collision interrupt */
  81   LVD_LVW_IRQn                 = 6,                /**< Low Voltage Detect, Low Voltage Warning */
  82   LLW_IRQn                     = 7,                /**< Low Leakage Wakeup */
  83   I2C0_IRQn                    = 8,                /**< I2C0 interrupt */
  84   Reserved25_IRQn              = 9,                /**< Reserved interrupt 25 */
  85   SPI0_IRQn                    = 10,               /**< SPI0 interrupt */
  86   Reserved27_IRQn              = 11,               /**< Reserved interrupt 27 */
  87   UART0_IRQn                   = 12,               /**< UART0 status/error interrupt */
  88   Reserved29_IRQn              = 13,               /**< Reserved interrupt 29 */
  89   Reserved30_IRQn              = 14,               /**< Reserved interrupt 30 */
  90   ADC0_IRQn                    = 15,               /**< ADC0 interrupt */
  91   CMP0_IRQn                    = 16,               /**< CMP0 interrupt */
  92   TPM0_IRQn                    = 17,               /**< TPM0 fault, overflow and channels interrupt */
  93   TPM1_IRQn                    = 18,               /**< TPM1 fault, overflow and channels interrupt */
  94   Reserved35_IRQn              = 19,               /**< Reserved interrupt 35 */
  95   RTC_IRQn                     = 20,               /**< RTC interrupt */
  96   RTC_Seconds_IRQn             = 21,               /**< RTC seconds interrupt */
  97   PIT_IRQn                     = 22,               /**< PIT timer interrupt */
  98   Reserved39_IRQn              = 23,               /**< Reserved interrupt 39 */
  99   Reserved40_IRQn              = 24,               /**< Reserved interrupt 40 */
 100   DAC0_IRQn                    = 25,               /**< DAC0 interrupt */
 101   TSI0_IRQn                    = 26,               /**< TSI0 interrupt */
 102   MCG_IRQn                     = 27,               /**< MCG interrupt */
 103   LPTimer_IRQn                 = 28,               /**< LPTimer interrupt */
 104   Reserved45_IRQn              = 29,               /**< Reserved interrupt 45 */
 105   PORTA_IRQn                   = 30,               /**< Port A interrupt */
 106   PORTB_IRQn                   = 31                /**< Port B interrupt */
 107 } IRQn_Type;
 108
 109 /**
 110  * @}
 111  */ /* end of group Interrupt_vector_numbers */
 112
 113
 114 /* ----------------------------------------------------------------------------
 115    -- Cortex M0 Core Configuration
 116    ---------------------------------------------------------------------------- */
 117
 118 /**
 119  * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
 120  * @{
 121  */
 122
 123 #define __CM0PLUS_REV                  0x0000    /**< Core revision r0p0 */
 124 #define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
 125 #define __VTOR_PRESENT                 1         /**< Defines if an MPU is present or not */
 126 #define __NVIC_PRIO_BITS               2         /**< Number of priority bits implemented in the NVIC */
 127 #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
 128
 129 #include "core_cm0plus.h"              /* Core Peripheral Access Layer */
 130 #include "system_MKL05Z4.h"            /* Device specific configuration file */
 131
 132 /**
 133  * @}
 134  */ /* end of group Cortex_Core_Configuration */
 135
 136
 137 /* ----------------------------------------------------------------------------
 138    -- Device Peripheral Access Layer
 139    ---------------------------------------------------------------------------- */
 140
 141 /**
 142  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
 143  * @{
 144  */
 145
 146
 147 /*
 148 ** Start of section using anonymous unions
 149 */
 150
 151 #if defined(__ARMCC_VERSION)
 152   #pragma push
 153   #pragma anon_unions
 154 #elif defined(__CWCC__)
 155   #pragma push
 156   #pragma cpp_extensions on
 157 #elif defined(__GNUC__)
 158   /* anonymous unions are enabled by default */
 159 #elif defined(__IAR_SYSTEMS_ICC__)
 160   #pragma language=extended
 161 #else
 162   #error Not supported compiler type
 163 #endif
 164
 165 /* ----------------------------------------------------------------------------
 166    -- ADC Peripheral Access Layer
 167    ---------------------------------------------------------------------------- */
 168
 169 /**
 170  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
 171  * @{
 172  */
 173
 174 /** ADC - Register Layout Typedef */
 175 typedef struct {
 176   __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
 177   __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
 178   __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
 179   __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
 180   __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
 181   __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
 182   __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
 183   __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
 184   __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
 185   __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
 186        uint8_t RESERVED_0[4];
 187   __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
 188   __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
 189   __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
 190   __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
 191   __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
 192   __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
 193   __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
 194 } ADC_Type;
 195
 196 /* ----------------------------------------------------------------------------
 197    -- ADC Register Masks
 198    ---------------------------------------------------------------------------- */
 199
 200 /**
 201  * @addtogroup ADC_Register_Masks ADC Register Masks
 202  * @{
 203  */
 204
 205 /* SC1 Bit Fields */
 206 #define ADC_SC1_ADCH_MASK                        0x1Fu
 207 #define ADC_SC1_ADCH_SHIFT                       0
 208 #define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
 209 #define ADC_SC1_AIEN_MASK                        0x40u
 210 #define ADC_SC1_AIEN_SHIFT                       6
 211 #define ADC_SC1_COCO_MASK                        0x80u
 212 #define ADC_SC1_COCO_SHIFT                       7
 213 /* CFG1 Bit Fields */
 214 #define ADC_CFG1_ADICLK_MASK                     0x3u
 215 #define ADC_CFG1_ADICLK_SHIFT                    0
 216 #define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
 217 #define ADC_CFG1_MODE_MASK                       0xCu
 218 #define ADC_CFG1_MODE_SHIFT                      2
 219 #define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
 220 #define ADC_CFG1_ADLSMP_MASK                     0x10u
 221 #define ADC_CFG1_ADLSMP_SHIFT                    4
 222 #define ADC_CFG1_ADIV_MASK                       0x60u
 223 #define ADC_CFG1_ADIV_SHIFT                      5
 224 #define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
 225 #define ADC_CFG1_ADLPC_MASK                      0x80u
 226 #define ADC_CFG1_ADLPC_SHIFT                     7
 227 /* CFG2 Bit Fields */
 228 #define ADC_CFG2_ADLSTS_MASK                     0x3u
 229 #define ADC_CFG2_ADLSTS_SHIFT                    0
 230 #define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
 231 #define ADC_CFG2_ADHSC_MASK                      0x4u
 232 #define ADC_CFG2_ADHSC_SHIFT                     2
 233 #define ADC_CFG2_ADACKEN_MASK                    0x8u
 234 #define ADC_CFG2_ADACKEN_SHIFT                   3
 235 #define ADC_CFG2_MUXSEL_MASK                     0x10u
 236 #define ADC_CFG2_MUXSEL_SHIFT                    4
 237 /* R Bit Fields */
 238 #define ADC_R_D_MASK                             0xFFFFu
 239 #define ADC_R_D_SHIFT                            0
 240 #define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
 241 /* CV1 Bit Fields */
 242 #define ADC_CV1_CV_MASK                          0xFFFFu
 243 #define ADC_CV1_CV_SHIFT                         0
 244 #define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
 245 /* CV2 Bit Fields */
 246 #define ADC_CV2_CV_MASK                          0xFFFFu
 247 #define ADC_CV2_CV_SHIFT                         0
 248 #define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
 249 /* SC2 Bit Fields */
 250 #define ADC_SC2_REFSEL_MASK                      0x3u
 251 #define ADC_SC2_REFSEL_SHIFT                     0
 252 #define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
 253 #define ADC_SC2_DMAEN_MASK                       0x4u
 254 #define ADC_SC2_DMAEN_SHIFT                      2
 255 #define ADC_SC2_ACREN_MASK                       0x8u
 256 #define ADC_SC2_ACREN_SHIFT                      3
 257 #define ADC_SC2_ACFGT_MASK                       0x10u
 258 #define ADC_SC2_ACFGT_SHIFT                      4
 259 #define ADC_SC2_ACFE_MASK                        0x20u
 260 #define ADC_SC2_ACFE_SHIFT                       5
 261 #define ADC_SC2_ADTRG_MASK                       0x40u
 262 #define ADC_SC2_ADTRG_SHIFT                      6
 263 #define ADC_SC2_ADACT_MASK                       0x80u
 264 #define ADC_SC2_ADACT_SHIFT                      7
 265 /* SC3 Bit Fields */
 266 #define ADC_SC3_AVGS_MASK                        0x3u
 267 #define ADC_SC3_AVGS_SHIFT                       0
 268 #define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
 269 #define ADC_SC3_AVGE_MASK                        0x4u
 270 #define ADC_SC3_AVGE_SHIFT                       2
 271 #define ADC_SC3_ADCO_MASK                        0x8u
 272 #define ADC_SC3_ADCO_SHIFT                       3
 273 #define ADC_SC3_CALF_MASK                        0x40u
 274 #define ADC_SC3_CALF_SHIFT                       6
 275 #define ADC_SC3_CAL_MASK                         0x80u
 276 #define ADC_SC3_CAL_SHIFT                        7
 277 /* OFS Bit Fields */
 278 #define ADC_OFS_OFS_MASK                         0xFFFFu
 279 #define ADC_OFS_OFS_SHIFT                        0
 280 #define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
 281 /* PG Bit Fields */
 282 #define ADC_PG_PG_MASK                           0xFFFFu
 283 #define ADC_PG_PG_SHIFT                          0
 284 #define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
 285 /* CLPD Bit Fields */
 286 #define ADC_CLPD_CLPD_MASK                       0x3Fu
 287 #define ADC_CLPD_CLPD_SHIFT                      0
 288 #define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
 289 /* CLPS Bit Fields */
 290 #define ADC_CLPS_CLPS_MASK                       0x3Fu
 291 #define ADC_CLPS_CLPS_SHIFT                      0
 292 #define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
 293 /* CLP4 Bit Fields */
 294 #define ADC_CLP4_CLP4_MASK                       0x3FFu
 295 #define ADC_CLP4_CLP4_SHIFT                      0
 296 #define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
 297 /* CLP3 Bit Fields */
 298 #define ADC_CLP3_CLP3_MASK                       0x1FFu
 299 #define ADC_CLP3_CLP3_SHIFT                      0
 300 #define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
 301 /* CLP2 Bit Fields */
 302 #define ADC_CLP2_CLP2_MASK                       0xFFu
 303 #define ADC_CLP2_CLP2_SHIFT                      0
 304 #define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
 305 /* CLP1 Bit Fields */
 306 #define ADC_CLP1_CLP1_MASK                       0x7Fu
 307 #define ADC_CLP1_CLP1_SHIFT                      0
 308 #define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
 309 /* CLP0 Bit Fields */
 310 #define ADC_CLP0_CLP0_MASK                       0x3Fu
 311 #define ADC_CLP0_CLP0_SHIFT                      0
 312 #define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
 313
 314 /**
 315  * @}
 316  */ /* end of group ADC_Register_Masks */
 317
 318
 319 /* ADC - Peripheral instance base addresses */
 320 /** Peripheral ADC0 base address */
 321 #define ADC0_BASE                                (0x4003B000u)
 322 /** Peripheral ADC0 base pointer */
 323 #define ADC0                                     ((ADC_Type *)ADC0_BASE)
 324 /** Array initializer of ADC peripheral base pointers */
 325 #define ADC_BASES                                { ADC0 }
 326
 327 /**
 328  * @}
 329  */ /* end of group ADC_Peripheral_Access_Layer */
 330
 331
 332 /* ----------------------------------------------------------------------------
 333    -- CMP Peripheral Access Layer
 334    ---------------------------------------------------------------------------- */
 335
 336 /**
 337  * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
 338  * @{
 339  */
 340
 341 /** CMP - Register Layout Typedef */
 342 typedef struct {
 343   __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
 344   __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
 345   __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
 346   __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
 347   __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
 348   __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
 349 } CMP_Type;
 350
 351 /* ----------------------------------------------------------------------------
 352    -- CMP Register Masks
 353    ---------------------------------------------------------------------------- */
 354
 355 /**
 356  * @addtogroup CMP_Register_Masks CMP Register Masks
 357  * @{
 358  */
 359
 360 /* CR0 Bit Fields */
 361 #define CMP_CR0_HYSTCTR_MASK                     0x3u
 362 #define CMP_CR0_HYSTCTR_SHIFT                    0
 363 #define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
 364 #define CMP_CR0_FILTER_CNT_MASK                  0x70u
 365 #define CMP_CR0_FILTER_CNT_SHIFT                 4
 366 #define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
 367 /* CR1 Bit Fields */
 368 #define CMP_CR1_EN_MASK                          0x1u
 369 #define CMP_CR1_EN_SHIFT                         0
 370 #define CMP_CR1_OPE_MASK                         0x2u
 371 #define CMP_CR1_OPE_SHIFT                        1
 372 #define CMP_CR1_COS_MASK                         0x4u
 373 #define CMP_CR1_COS_SHIFT                        2
 374 #define CMP_CR1_INV_MASK                         0x8u
 375 #define CMP_CR1_INV_SHIFT                        3
 376 #define CMP_CR1_PMODE_MASK                       0x10u
 377 #define CMP_CR1_PMODE_SHIFT                      4
 378 #define CMP_CR1_TRIGM_MASK                       0x20u
 379 #define CMP_CR1_TRIGM_SHIFT                      5
 380 #define CMP_CR1_WE_MASK                          0x40u
 381 #define CMP_CR1_WE_SHIFT                         6
 382 #define CMP_CR1_SE_MASK                          0x80u
 383 #define CMP_CR1_SE_SHIFT                         7
 384 /* FPR Bit Fields */
 385 #define CMP_FPR_FILT_PER_MASK                    0xFFu
 386 #define CMP_FPR_FILT_PER_SHIFT                   0
 387 #define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
 388 /* SCR Bit Fields */
 389 #define CMP_SCR_COUT_MASK                        0x1u
 390 #define CMP_SCR_COUT_SHIFT                       0
 391 #define CMP_SCR_CFF_MASK                         0x2u
 392 #define CMP_SCR_CFF_SHIFT                        1
 393 #define CMP_SCR_CFR_MASK                         0x4u
 394 #define CMP_SCR_CFR_SHIFT                        2
 395 #define CMP_SCR_IEF_MASK                         0x8u
 396 #define CMP_SCR_IEF_SHIFT                        3
 397 #define CMP_SCR_IER_MASK                         0x10u
 398 #define CMP_SCR_IER_SHIFT                        4
 399 #define CMP_SCR_DMAEN_MASK                       0x40u
 400 #define CMP_SCR_DMAEN_SHIFT                      6
 401 /* DACCR Bit Fields */
 402 #define CMP_DACCR_VOSEL_MASK                     0x3Fu
 403 #define CMP_DACCR_VOSEL_SHIFT                    0
 404 #define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
 405 #define CMP_DACCR_VRSEL_MASK                     0x40u
 406 #define CMP_DACCR_VRSEL_SHIFT                    6
 407 #define CMP_DACCR_DACEN_MASK                     0x80u
 408 #define CMP_DACCR_DACEN_SHIFT                    7
 409 /* MUXCR Bit Fields */
 410 #define CMP_MUXCR_MSEL_MASK                      0x7u
 411 #define CMP_MUXCR_MSEL_SHIFT                     0
 412 #define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
 413 #define CMP_MUXCR_PSEL_MASK                      0x38u
 414 #define CMP_MUXCR_PSEL_SHIFT                     3
 415 #define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
 416 #define CMP_MUXCR_PSTM_MASK                      0x80u
 417 #define CMP_MUXCR_PSTM_SHIFT                     7
 418
 419 /**
 420  * @}
 421  */ /* end of group CMP_Register_Masks */
 422
 423
 424 /* CMP - Peripheral instance base addresses */
 425 /** Peripheral CMP0 base address */
 426 #define CMP0_BASE                                (0x40073000u)
 427 /** Peripheral CMP0 base pointer */
 428 #define CMP0                                     ((CMP_Type *)CMP0_BASE)
 429 /** Array initializer of CMP peripheral base pointers */
 430 #define CMP_BASES                                { CMP0 }
 431
 432 /**
 433  * @}
 434  */ /* end of group CMP_Peripheral_Access_Layer */
 435
 436
 437 /* ----------------------------------------------------------------------------
 438    -- DAC Peripheral Access Layer
 439    ---------------------------------------------------------------------------- */
 440
 441 /**
 442  * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
 443  * @{
 444  */
 445
 446 /** DAC - Register Layout Typedef */
 447 typedef struct {
 448   struct {                                         /* offset: 0x0, array step: 0x2 */
 449     __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
 450     __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
 451   } DAT[2];
 452        uint8_t RESERVED_0[28];
 453   __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
 454   __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
 455   __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
 456   __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
 457 } DAC_Type;
 458
 459 /* ----------------------------------------------------------------------------
 460    -- DAC Register Masks
 461    ---------------------------------------------------------------------------- */
 462
 463 /**
 464  * @addtogroup DAC_Register_Masks DAC Register Masks
 465  * @{
 466  */
 467
 468 /* DATL Bit Fields */
 469 #define DAC_DATL_DATA0_MASK                      0xFFu
 470 #define DAC_DATL_DATA0_SHIFT                     0
 471 #define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
 472 /* DATH Bit Fields */
 473 #define DAC_DATH_DATA1_MASK                      0xFu
 474 #define DAC_DATH_DATA1_SHIFT                     0
 475 #define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
 476 /* SR Bit Fields */
 477 #define DAC_SR_DACBFRPBF_MASK                    0x1u
 478 #define DAC_SR_DACBFRPBF_SHIFT                   0
 479 #define DAC_SR_DACBFRPTF_MASK                    0x2u
 480 #define DAC_SR_DACBFRPTF_SHIFT                   1
 481 /* C0 Bit Fields */
 482 #define DAC_C0_DACBBIEN_MASK                     0x1u
 483 #define DAC_C0_DACBBIEN_SHIFT                    0
 484 #define DAC_C0_DACBTIEN_MASK                     0x2u
 485 #define DAC_C0_DACBTIEN_SHIFT                    1
 486 #define DAC_C0_LPEN_MASK                         0x8u
 487 #define DAC_C0_LPEN_SHIFT                        3
 488 #define DAC_C0_DACSWTRG_MASK                     0x10u
 489 #define DAC_C0_DACSWTRG_SHIFT                    4
 490 #define DAC_C0_DACTRGSEL_MASK                    0x20u
 491 #define DAC_C0_DACTRGSEL_SHIFT                   5
 492 #define DAC_C0_DACRFS_MASK                       0x40u
 493 #define DAC_C0_DACRFS_SHIFT                      6
 494 #define DAC_C0_DACEN_MASK                        0x80u
 495 #define DAC_C0_DACEN_SHIFT                       7
 496 /* C1 Bit Fields */
 497 #define DAC_C1_DACBFEN_MASK                      0x1u
 498 #define DAC_C1_DACBFEN_SHIFT                     0
 499 #define DAC_C1_DACBFMD_MASK                      0x4u
 500 #define DAC_C1_DACBFMD_SHIFT                     2
 501 #define DAC_C1_DMAEN_MASK                        0x80u
 502 #define DAC_C1_DMAEN_SHIFT                       7
 503 /* C2 Bit Fields */
 504 #define DAC_C2_DACBFUP_MASK                      0x1u
 505 #define DAC_C2_DACBFUP_SHIFT                     0
 506 #define DAC_C2_DACBFRP_MASK                      0x10u
 507 #define DAC_C2_DACBFRP_SHIFT                     4
 508
 509 /**
 510  * @}
 511  */ /* end of group DAC_Register_Masks */
 512
 513
 514 /* DAC - Peripheral instance base addresses */
 515 /** Peripheral DAC0 base address */
 516 #define DAC0_BASE                                (0x4003F000u)
 517 /** Peripheral DAC0 base pointer */
 518 #define DAC0                                     ((DAC_Type *)DAC0_BASE)
 519 /** Array initializer of DAC peripheral base pointers */
 520 #define DAC_BASES                                { DAC0 }
 521
 522 /**
 523  * @}
 524  */ /* end of group DAC_Peripheral_Access_Layer */
 525
 526
 527 /* ----------------------------------------------------------------------------
 528    -- DMA Peripheral Access Layer
 529    ---------------------------------------------------------------------------- */
 530
 531 /**
 532  * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
 533  * @{
 534  */
 535
 536 /** DMA - Register Layout Typedef */
 537 typedef struct {
 538        uint8_t RESERVED_0[256];
 539   struct {                                         /* offset: 0x100, array step: 0x10 */
 540     __IO uint32_t SAR;                               /**< Source Address Register, array offset: 0x100, array step: 0x10 */
 541     __IO uint32_t DAR;                               /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
 542     union {                                          /* offset: 0x108, array step: 0x10 */
 543       __IO uint32_t DSR_BCR;                           /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
 544       struct {                                         /* offset: 0x108, array step: 0x10 */
 545              uint8_t RESERVED_0[3];
 546         __IO uint8_t DSR;                                /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
 547       } DMA_DSR_ACCESS8BIT;
 548     };
 549     __IO uint32_t DCR;                               /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
 550   } DMA[4];
 551 } DMA_Type;
 552
 553 /* ----------------------------------------------------------------------------
 554    -- DMA Register Masks
 555    ---------------------------------------------------------------------------- */
 556
 557 /**
 558  * @addtogroup DMA_Register_Masks DMA Register Masks
 559  * @{
 560  */
 561
 562 /* SAR Bit Fields */
 563 #define DMA_SAR_SAR_MASK                         0xFFFFFFFFu
 564 #define DMA_SAR_SAR_SHIFT                        0
 565 #define DMA_SAR_SAR(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
 566 /* DAR Bit Fields */
 567 #define DMA_DAR_DAR_MASK                         0xFFFFFFFFu
 568 #define DMA_DAR_DAR_SHIFT                        0
 569 #define DMA_DAR_DAR(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
 570 /* DSR_BCR Bit Fields */
 571 #define DMA_DSR_BCR_BCR_MASK                     0xFFFFFFu
 572 #define DMA_DSR_BCR_BCR_SHIFT                    0
 573 #define DMA_DSR_BCR_BCR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
 574 #define DMA_DSR_BCR_DONE_MASK                    0x1000000u
 575 #define DMA_DSR_BCR_DONE_SHIFT                   24
 576 #define DMA_DSR_BCR_BSY_MASK                     0x2000000u
 577 #define DMA_DSR_BCR_BSY_SHIFT                    25
 578 #define DMA_DSR_BCR_REQ_MASK                     0x4000000u
 579 #define DMA_DSR_BCR_REQ_SHIFT                    26
 580 #define DMA_DSR_BCR_BED_MASK                     0x10000000u
 581 #define DMA_DSR_BCR_BED_SHIFT                    28
 582 #define DMA_DSR_BCR_BES_MASK                     0x20000000u
 583 #define DMA_DSR_BCR_BES_SHIFT                    29
 584 #define DMA_DSR_BCR_CE_MASK                      0x40000000u
 585 #define DMA_DSR_BCR_CE_SHIFT                     30
 586 /* DCR Bit Fields */
 587 #define DMA_DCR_LCH2_MASK                        0x3u
 588 #define DMA_DCR_LCH2_SHIFT                       0
 589 #define DMA_DCR_LCH2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
 590 #define DMA_DCR_LCH1_MASK                        0xCu
 591 #define DMA_DCR_LCH1_SHIFT                       2
 592 #define DMA_DCR_LCH1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
 593 #define DMA_DCR_LINKCC_MASK                      0x30u
 594 #define DMA_DCR_LINKCC_SHIFT                     4
 595 #define DMA_DCR_LINKCC(x)                        (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
 596 #define DMA_DCR_D_REQ_MASK                       0x80u
 597 #define DMA_DCR_D_REQ_SHIFT                      7
 598 #define DMA_DCR_DMOD_MASK                        0xF00u
 599 #define DMA_DCR_DMOD_SHIFT                       8
 600 #define DMA_DCR_DMOD(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
 601 #define DMA_DCR_SMOD_MASK                        0xF000u
 602 #define DMA_DCR_SMOD_SHIFT                       12
 603 #define DMA_DCR_SMOD(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
 604 #define DMA_DCR_START_MASK                       0x10000u
 605 #define DMA_DCR_START_SHIFT                      16
 606 #define DMA_DCR_DSIZE_MASK                       0x60000u
 607 #define DMA_DCR_DSIZE_SHIFT                      17
 608 #define DMA_DCR_DSIZE(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
 609 #define DMA_DCR_DINC_MASK                        0x80000u
 610 #define DMA_DCR_DINC_SHIFT                       19
 611 #define DMA_DCR_SSIZE_MASK                       0x300000u
 612 #define DMA_DCR_SSIZE_SHIFT                      20
 613 #define DMA_DCR_SSIZE(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
 614 #define DMA_DCR_SINC_MASK                        0x400000u
 615 #define DMA_DCR_SINC_SHIFT                       22
 616 #define DMA_DCR_EADREQ_MASK                      0x800000u
 617 #define DMA_DCR_EADREQ_SHIFT                     23
 618 #define DMA_DCR_AA_MASK                          0x10000000u
 619 #define DMA_DCR_AA_SHIFT                         28
 620 #define DMA_DCR_CS_MASK                          0x20000000u
 621 #define DMA_DCR_CS_SHIFT                         29
 622 #define DMA_DCR_ERQ_MASK                         0x40000000u
 623 #define DMA_DCR_ERQ_SHIFT                        30
 624 #define DMA_DCR_EINT_MASK                        0x80000000u
 625 #define DMA_DCR_EINT_SHIFT                       31
 626
 627 /**
 628  * @}
 629  */ /* end of group DMA_Register_Masks */
 630
 631
 632 /* DMA - Peripheral instance base addresses */
 633 /** Peripheral DMA base address */
 634 #define DMA_BASE                                 (0x40008000u)
 635 /** Peripheral DMA base pointer */
 636 #define DMA0                                     ((DMA_Type *)DMA_BASE)
 637 /** Array initializer of DMA peripheral base pointers */
 638 #define DMA_BASES                                { DMA0 }
 639
 640 /**
 641  * @}
 642  */ /* end of group DMA_Peripheral_Access_Layer */
 643
 644
 645 /* ----------------------------------------------------------------------------
 646    -- DMAMUX Peripheral Access Layer
 647    ---------------------------------------------------------------------------- */
 648
 649 /**
 650  * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
 651  * @{
 652  */
 653
 654 /** DMAMUX - Register Layout Typedef */
 655 typedef struct {
 656   __IO uint8_t CHCFG[4];                           /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
 657 } DMAMUX_Type;
 658
 659 /* ----------------------------------------------------------------------------
 660    -- DMAMUX Register Masks
 661    ---------------------------------------------------------------------------- */
 662
 663 /**
 664  * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
 665  * @{
 666  */
 667
 668 /* CHCFG Bit Fields */
 669 #define DMAMUX_CHCFG_SOURCE_MASK                 0x3Fu
 670 #define DMAMUX_CHCFG_SOURCE_SHIFT                0
 671 #define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
 672 #define DMAMUX_CHCFG_TRIG_MASK                   0x40u
 673 #define DMAMUX_CHCFG_TRIG_SHIFT                  6
 674 #define DMAMUX_CHCFG_ENBL_MASK                   0x80u
 675 #define DMAMUX_CHCFG_ENBL_SHIFT                  7
 676
 677 /**
 678  * @}
 679  */ /* end of group DMAMUX_Register_Masks */
 680
 681
 682 /* DMAMUX - Peripheral instance base addresses */
 683 /** Peripheral DMAMUX0 base address */
 684 #define DMAMUX0_BASE                             (0x40021000u)
 685 /** Peripheral DMAMUX0 base pointer */
 686 #define DMAMUX0                                  ((DMAMUX_Type *)DMAMUX0_BASE)
 687 /** Array initializer of DMAMUX peripheral base pointers */
 688 #define DMAMUX_BASES                             { DMAMUX0 }
 689
 690 /**
 691  * @}
 692  */ /* end of group DMAMUX_Peripheral_Access_Layer */
 693
 694
 695 /* ----------------------------------------------------------------------------
 696    -- FGPIO Peripheral Access Layer
 697    ---------------------------------------------------------------------------- */
 698
 699 /**
 700  * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
 701  * @{
 702  */
 703
 704 /** FGPIO - Register Layout Typedef */
 705 typedef struct {
 706   __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
 707   __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
 708   __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
 709   __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
 710   __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
 711   __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
 712 } FGPIO_Type;
 713
 714 /* ----------------------------------------------------------------------------
 715    -- FGPIO Register Masks
 716    ---------------------------------------------------------------------------- */
 717
 718 /**
 719  * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
 720  * @{
 721  */
 722
 723 /* PDOR Bit Fields */
 724 #define FGPIO_PDOR_PDO_MASK                      0xFFFFFFFFu
 725 #define FGPIO_PDOR_PDO_SHIFT                     0
 726 #define FGPIO_PDOR_PDO(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
 727 /* PSOR Bit Fields */
 728 #define FGPIO_PSOR_PTSO_MASK                     0xFFFFFFFFu
 729 #define FGPIO_PSOR_PTSO_SHIFT                    0
 730 #define FGPIO_PSOR_PTSO(x)                       (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
 731 /* PCOR Bit Fields */
 732 #define FGPIO_PCOR_PTCO_MASK                     0xFFFFFFFFu
 733 #define FGPIO_PCOR_PTCO_SHIFT                    0
 734 #define FGPIO_PCOR_PTCO(x)                       (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
 735 /* PTOR Bit Fields */
 736 #define FGPIO_PTOR_PTTO_MASK                     0xFFFFFFFFu
 737 #define FGPIO_PTOR_PTTO_SHIFT                    0
 738 #define FGPIO_PTOR_PTTO(x)                       (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
 739 /* PDIR Bit Fields */
 740 #define FGPIO_PDIR_PDI_MASK                      0xFFFFFFFFu
 741 #define FGPIO_PDIR_PDI_SHIFT                     0
 742 #define FGPIO_PDIR_PDI(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
 743 /* PDDR Bit Fields */
 744 #define FGPIO_PDDR_PDD_MASK                      0xFFFFFFFFu
 745 #define FGPIO_PDDR_PDD_SHIFT                     0
 746 #define FGPIO_PDDR_PDD(x)                        (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
 747
 748 /**
 749  * @}
 750  */ /* end of group FGPIO_Register_Masks */
 751
 752
 753 /* FGPIO - Peripheral instance base addresses */
 754 /** Peripheral FPTA base address */
 755 #define FPTA_BASE                                (0xF80FF000u)
 756 /** Peripheral FPTA base pointer */
 757 #define FPTA                                     ((FGPIO_Type *)FPTA_BASE)
 758 /** Peripheral FPTB base address */
 759 #define FPTB_BASE                                (0xF80FF040u)
 760 /** Peripheral FPTB base pointer */
 761 #define FPTB                                     ((FGPIO_Type *)FPTB_BASE)
 762 /** Array initializer of FGPIO peripheral base pointers */
 763 #define FGPIO_BASES                              { FPTA, FPTB }
 764
 765 /**
 766  * @}
 767  */ /* end of group FGPIO_Peripheral_Access_Layer */
 768
 769
 770 /* ----------------------------------------------------------------------------
 771    -- FTFA Peripheral Access Layer
 772    ---------------------------------------------------------------------------- */
 773
 774 /**
 775  * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
 776  * @{
 777  */
 778
 779 /** FTFA - Register Layout Typedef */
 780 typedef struct {
 781   __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
 782   __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
 783   __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
 784   __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
 785   __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
 786   __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
 787   __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
 788   __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
 789   __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
 790   __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
 791   __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
 792   __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
 793   __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
 794   __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
 795   __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
 796   __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
 797   __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
 798   __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
 799   __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
 800   __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
 801 } FTFA_Type;
 802
 803 /* ----------------------------------------------------------------------------
 804    -- FTFA Register Masks
 805    ---------------------------------------------------------------------------- */
 806
 807 /**
 808  * @addtogroup FTFA_Register_Masks FTFA Register Masks
 809  * @{
 810  */
 811
 812 /* FSTAT Bit Fields */
 813 #define FTFA_FSTAT_MGSTAT0_MASK                  0x1u
 814 #define FTFA_FSTAT_MGSTAT0_SHIFT                 0
 815 #define FTFA_FSTAT_FPVIOL_MASK                   0x10u
 816 #define FTFA_FSTAT_FPVIOL_SHIFT                  4
 817 #define FTFA_FSTAT_ACCERR_MASK                   0x20u
 818 #define FTFA_FSTAT_ACCERR_SHIFT                  5
 819 #define FTFA_FSTAT_RDCOLERR_MASK                 0x40u
 820 #define FTFA_FSTAT_RDCOLERR_SHIFT                6
 821 #define FTFA_FSTAT_CCIF_MASK                     0x80u
 822 #define FTFA_FSTAT_CCIF_SHIFT                    7
 823 /* FCNFG Bit Fields */
 824 #define FTFA_FCNFG_ERSSUSP_MASK                  0x10u
 825 #define FTFA_FCNFG_ERSSUSP_SHIFT                 4
 826 #define FTFA_FCNFG_ERSAREQ_MASK                  0x20u
 827 #define FTFA_FCNFG_ERSAREQ_SHIFT                 5
 828 #define FTFA_FCNFG_RDCOLLIE_MASK                 0x40u
 829 #define FTFA_FCNFG_RDCOLLIE_SHIFT                6
 830 #define FTFA_FCNFG_CCIE_MASK                     0x80u
 831 #define FTFA_FCNFG_CCIE_SHIFT                    7
 832 /* FSEC Bit Fields */
 833 #define FTFA_FSEC_SEC_MASK                       0x3u
 834 #define FTFA_FSEC_SEC_SHIFT                      0
 835 #define FTFA_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
 836 #define FTFA_FSEC_FSLACC_MASK                    0xCu
 837 #define FTFA_FSEC_FSLACC_SHIFT                   2
 838 #define FTFA_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
 839 #define FTFA_FSEC_MEEN_MASK                      0x30u
 840 #define FTFA_FSEC_MEEN_SHIFT                     4
 841 #define FTFA_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
 842 #define FTFA_FSEC_KEYEN_MASK                     0xC0u
 843 #define FTFA_FSEC_KEYEN_SHIFT                    6
 844 #define FTFA_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
 845 /* FOPT Bit Fields */
 846 #define FTFA_FOPT_OPT_MASK                       0xFFu
 847 #define FTFA_FOPT_OPT_SHIFT                      0
 848 #define FTFA_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
 849 /* FCCOB3 Bit Fields */
 850 #define FTFA_FCCOB3_CCOBn_MASK                   0xFFu
 851 #define FTFA_FCCOB3_CCOBn_SHIFT                  0
 852 #define FTFA_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
 853 /* FCCOB2 Bit Fields */
 854 #define FTFA_FCCOB2_CCOBn_MASK                   0xFFu
 855 #define FTFA_FCCOB2_CCOBn_SHIFT                  0
 856 #define FTFA_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
 857 /* FCCOB1 Bit Fields */
 858 #define FTFA_FCCOB1_CCOBn_MASK                   0xFFu
 859 #define FTFA_FCCOB1_CCOBn_SHIFT                  0
 860 #define FTFA_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
 861 /* FCCOB0 Bit Fields */
 862 #define FTFA_FCCOB0_CCOBn_MASK                   0xFFu
 863 #define FTFA_FCCOB0_CCOBn_SHIFT                  0
 864 #define FTFA_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
 865 /* FCCOB7 Bit Fields */
 866 #define FTFA_FCCOB7_CCOBn_MASK                   0xFFu
 867 #define FTFA_FCCOB7_CCOBn_SHIFT                  0
 868 #define FTFA_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
 869 /* FCCOB6 Bit Fields */
 870 #define FTFA_FCCOB6_CCOBn_MASK                   0xFFu
 871 #define FTFA_FCCOB6_CCOBn_SHIFT                  0
 872 #define FTFA_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
 873 /* FCCOB5 Bit Fields */
 874 #define FTFA_FCCOB5_CCOBn_MASK                   0xFFu
 875 #define FTFA_FCCOB5_CCOBn_SHIFT                  0
 876 #define FTFA_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
 877 /* FCCOB4 Bit Fields */
 878 #define FTFA_FCCOB4_CCOBn_MASK                   0xFFu
 879 #define FTFA_FCCOB4_CCOBn_SHIFT                  0
 880 #define FTFA_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
 881 /* FCCOBB Bit Fields */
 882 #define FTFA_FCCOBB_CCOBn_MASK                   0xFFu
 883 #define FTFA_FCCOBB_CCOBn_SHIFT                  0
 884 #define FTFA_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
 885 /* FCCOBA Bit Fields */
 886 #define FTFA_FCCOBA_CCOBn_MASK                   0xFFu
 887 #define FTFA_FCCOBA_CCOBn_SHIFT                  0
 888 #define FTFA_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
 889 /* FCCOB9 Bit Fields */
 890 #define FTFA_FCCOB9_CCOBn_MASK                   0xFFu
 891 #define FTFA_FCCOB9_CCOBn_SHIFT                  0
 892 #define FTFA_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
 893 /* FCCOB8 Bit Fields */
 894 #define FTFA_FCCOB8_CCOBn_MASK                   0xFFu
 895 #define FTFA_FCCOB8_CCOBn_SHIFT                  0
 896 #define FTFA_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
 897 /* FPROT3 Bit Fields */
 898 #define FTFA_FPROT3_PROT_MASK                    0xFFu
 899 #define FTFA_FPROT3_PROT_SHIFT                   0
 900 #define FTFA_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
 901 /* FPROT2 Bit Fields */
 902 #define FTFA_FPROT2_PROT_MASK                    0xFFu
 903 #define FTFA_FPROT2_PROT_SHIFT                   0
 904 #define FTFA_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
 905 /* FPROT1 Bit Fields */
 906 #define FTFA_FPROT1_PROT_MASK                    0xFFu
 907 #define FTFA_FPROT1_PROT_SHIFT                   0
 908 #define FTFA_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
 909 /* FPROT0 Bit Fields */
 910 #define FTFA_FPROT0_PROT_MASK                    0xFFu
 911 #define FTFA_FPROT0_PROT_SHIFT                   0
 912 #define FTFA_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
 913
 914 /**
 915  * @}
 916  */ /* end of group FTFA_Register_Masks */
 917
 918
 919 /* FTFA - Peripheral instance base addresses */
 920 /** Peripheral FTFA base address */
 921 #define FTFA_BASE                                (0x40020000u)
 922 /** Peripheral FTFA base pointer */
 923 #define FTFA                                     ((FTFA_Type *)FTFA_BASE)
 924 /** Array initializer of FTFA peripheral base pointers */
 925 #define FTFA_BASES                               { FTFA }
 926
 927 /**
 928  * @}
 929  */ /* end of group FTFA_Peripheral_Access_Layer */
 930
 931
 932 /* ----------------------------------------------------------------------------
 933    -- GPIO Peripheral Access Layer
 934    ---------------------------------------------------------------------------- */
 935
 936 /**
 937  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
 938  * @{
 939  */
 940
 941 /** GPIO - Register Layout Typedef */
 942 typedef struct {
 943   __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
 944   __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
 945   __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
 946   __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
 947   __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
 948   __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
 949 } GPIO_Type;
 950
 951 /* ----------------------------------------------------------------------------
 952    -- GPIO Register Masks
 953    ---------------------------------------------------------------------------- */
 954
 955 /**
 956  * @addtogroup GPIO_Register_Masks GPIO Register Masks
 957  * @{
 958  */
 959
 960 /* PDOR Bit Fields */
 961 #define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
 962 #define GPIO_PDOR_PDO_SHIFT                      0
 963 #define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
 964 /* PSOR Bit Fields */
 965 #define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
 966 #define GPIO_PSOR_PTSO_SHIFT                     0
 967 #define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
 968 /* PCOR Bit Fields */
 969 #define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
 970 #define GPIO_PCOR_PTCO_SHIFT                     0
 971 #define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
 972 /* PTOR Bit Fields */
 973 #define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
 974 #define GPIO_PTOR_PTTO_SHIFT                     0
 975 #define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
 976 /* PDIR Bit Fields */
 977 #define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
 978 #define GPIO_PDIR_PDI_SHIFT                      0
 979 #define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
 980 /* PDDR Bit Fields */
 981 #define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
 982 #define GPIO_PDDR_PDD_SHIFT                      0
 983 #define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
 984
 985 /**
 986  * @}
 987  */ /* end of group GPIO_Register_Masks */
 988
 989
 990 /* GPIO - Peripheral instance base addresses */
 991 /** Peripheral PTA base address */
 992 #define PTA_BASE                                 (0x400FF000u)
 993 /** Peripheral PTA base pointer */
 994 #define PTA                                      ((GPIO_Type *)PTA_BASE)
 995 /** Peripheral PTB base address */
 996 #define PTB_BASE                                 (0x400FF040u)
 997 /** Peripheral PTB base pointer */
 998 #define PTB                                      ((GPIO_Type *)PTB_BASE)
 999 /** Array initializer of GPIO peripheral base pointers */
1000 #define GPIO_BASES                               { PTA, PTB }
1001
1002 /**
1003  * @}
1004  */ /* end of group GPIO_Peripheral_Access_Layer */
1005
1006
1007 /* ----------------------------------------------------------------------------
1008    -- I2C Peripheral Access Layer
1009    ---------------------------------------------------------------------------- */
1010
1011 /**
1012  * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
1013  * @{
1014  */
1015
1016 /** I2C - Register Layout Typedef */
1017 typedef struct {
1018   __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
1019   __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
1020   __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
1021   __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
1022   __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
1023   __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
1024   __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
1025   __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
1026   __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
1027   __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
1028   __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
1029   __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
1030 } I2C_Type;
1031
1032 /* ----------------------------------------------------------------------------
1033    -- I2C Register Masks
1034    ---------------------------------------------------------------------------- */
1035
1036 /**
1037  * @addtogroup I2C_Register_Masks I2C Register Masks
1038  * @{
1039  */
1040
1041 /* A1 Bit Fields */
1042 #define I2C_A1_AD_MASK                           0xFEu
1043 #define I2C_A1_AD_SHIFT                          1
1044 #define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
1045 /* F Bit Fields */
1046 #define I2C_F_ICR_MASK                           0x3Fu
1047 #define I2C_F_ICR_SHIFT                          0
1048 #define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
1049 #define I2C_F_MULT_MASK                          0xC0u
1050 #define I2C_F_MULT_SHIFT                         6
1051 #define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
1052 /* C1 Bit Fields */
1053 #define I2C_C1_DMAEN_MASK                        0x1u
1054 #define I2C_C1_DMAEN_SHIFT                       0
1055 #define I2C_C1_WUEN_MASK                         0x2u
1056 #define I2C_C1_WUEN_SHIFT                        1
1057 #define I2C_C1_RSTA_MASK                         0x4u
1058 #define I2C_C1_RSTA_SHIFT                        2
1059 #define I2C_C1_TXAK_MASK                         0x8u
1060 #define I2C_C1_TXAK_SHIFT                        3
1061 #define I2C_C1_TX_MASK                           0x10u
1062 #define I2C_C1_TX_SHIFT                          4
1063 #define I2C_C1_MST_MASK                          0x20u
1064 #define I2C_C1_MST_SHIFT                         5
1065 #define I2C_C1_IICIE_MASK                        0x40u
1066 #define I2C_C1_IICIE_SHIFT                       6
1067 #define I2C_C1_IICEN_MASK                        0x80u
1068 #define I2C_C1_IICEN_SHIFT                       7
1069 /* S Bit Fields */
1070 #define I2C_S_RXAK_MASK                          0x1u
1071 #define I2C_S_RXAK_SHIFT                         0
1072 #define I2C_S_IICIF_MASK                         0x2u
1073 #define I2C_S_IICIF_SHIFT                        1
1074 #define I2C_S_SRW_MASK                           0x4u
1075 #define I2C_S_SRW_SHIFT                          2
1076 #define I2C_S_RAM_MASK                           0x8u
1077 #define I2C_S_RAM_SHIFT                          3
1078 #define I2C_S_ARBL_MASK                          0x10u
1079 #define I2C_S_ARBL_SHIFT                         4
1080 #define I2C_S_BUSY_MASK                          0x20u
1081 #define I2C_S_BUSY_SHIFT                         5
1082 #define I2C_S_IAAS_MASK                          0x40u
1083 #define I2C_S_IAAS_SHIFT                         6
1084 #define I2C_S_TCF_MASK                           0x80u
1085 #define I2C_S_TCF_SHIFT                          7
1086 /* D Bit Fields */
1087 #define I2C_D_DATA_MASK                          0xFFu
1088 #define I2C_D_DATA_SHIFT                         0
1089 #define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
1090 /* C2 Bit Fields */
1091 #define I2C_C2_AD_MASK                           0x7u
1092 #define I2C_C2_AD_SHIFT                          0
1093 #define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
1094 #define I2C_C2_RMEN_MASK                         0x8u
1095 #define I2C_C2_RMEN_SHIFT                        3
1096 #define I2C_C2_SBRC_MASK                         0x10u
1097 #define I2C_C2_SBRC_SHIFT                        4
1098 #define I2C_C2_HDRS_MASK                         0x20u
1099 #define I2C_C2_HDRS_SHIFT                        5
1100 #define I2C_C2_ADEXT_MASK                        0x40u
1101 #define I2C_C2_ADEXT_SHIFT                       6
1102 #define I2C_C2_GCAEN_MASK                        0x80u
1103 #define I2C_C2_GCAEN_SHIFT                       7
1104 /* FLT Bit Fields */
1105 #define I2C_FLT_FLT_MASK                         0x1Fu
1106 #define I2C_FLT_FLT_SHIFT                        0
1107 #define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
1108 #define I2C_FLT_STOPIE_MASK                      0x20u
1109 #define I2C_FLT_STOPIE_SHIFT                     5
1110 #define I2C_FLT_STOPF_MASK                       0x40u
1111 #define I2C_FLT_STOPF_SHIFT                      6
1112 #define I2C_FLT_SHEN_MASK                        0x80u
1113 #define I2C_FLT_SHEN_SHIFT                       7
1114 /* RA Bit Fields */
1115 #define I2C_RA_RAD_MASK                          0xFEu
1116 #define I2C_RA_RAD_SHIFT                         1
1117 #define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
1118 /* SMB Bit Fields */
1119 #define I2C_SMB_SHTF2IE_MASK                     0x1u
1120 #define I2C_SMB_SHTF2IE_SHIFT                    0
1121 #define I2C_SMB_SHTF2_MASK                       0x2u
1122 #define I2C_SMB_SHTF2_SHIFT                      1
1123 #define I2C_SMB_SHTF1_MASK                       0x4u
1124 #define I2C_SMB_SHTF1_SHIFT                      2
1125 #define I2C_SMB_SLTF_MASK                        0x8u
1126 #define I2C_SMB_SLTF_SHIFT                       3
1127 #define I2C_SMB_TCKSEL_MASK                      0x10u
1128 #define I2C_SMB_TCKSEL_SHIFT                     4
1129 #define I2C_SMB_SIICAEN_MASK                     0x20u
1130 #define I2C_SMB_SIICAEN_SHIFT                    5
1131 #define I2C_SMB_ALERTEN_MASK                     0x40u
1132 #define I2C_SMB_ALERTEN_SHIFT                    6
1133 #define I2C_SMB_FACK_MASK                        0x80u
1134 #define I2C_SMB_FACK_SHIFT                       7
1135 /* A2 Bit Fields */
1136 #define I2C_A2_SAD_MASK                          0xFEu
1137 #define I2C_A2_SAD_SHIFT                         1
1138 #define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
1139 /* SLTH Bit Fields */
1140 #define I2C_SLTH_SSLT_MASK                       0xFFu
1141 #define I2C_SLTH_SSLT_SHIFT                      0
1142 #define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
1143 /* SLTL Bit Fields */
1144 #define I2C_SLTL_SSLT_MASK                       0xFFu
1145 #define I2C_SLTL_SSLT_SHIFT                      0
1146 #define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
1147
1148 /**
1149  * @}
1150  */ /* end of group I2C_Register_Masks */
1151
1152
1153 /* I2C - Peripheral instance base addresses */
1154 /** Peripheral I2C0 base address */
1155 #define I2C0_BASE                                (0x40066000u)
1156 /** Peripheral I2C0 base pointer */
1157 #define I2C0                                     ((I2C_Type *)I2C0_BASE)
1158 /** Array initializer of I2C peripheral base pointers */
1159 #define I2C_BASES                                { I2C0 }
1160
1161 /**
1162  * @}
1163  */ /* end of group I2C_Peripheral_Access_Layer */
1164
1165
1166 /* ----------------------------------------------------------------------------
1167    -- LLWU Peripheral Access Layer
1168    ---------------------------------------------------------------------------- */
1169
1170 /**
1171  * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
1172  * @{
1173  */
1174
1175 /** LLWU - Register Layout Typedef */
1176 typedef struct {
1177   __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
1178   __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
1179   __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x2 */
1180   __IO uint8_t F1;                                 /**< LLWU Flag 1 register, offset: 0x3 */
1181   __I  uint8_t F3;                                 /**< LLWU Flag 3 register, offset: 0x4 */
1182   __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x5 */
1183   __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x6 */
1184 } LLWU_Type;
1185
1186 /* ----------------------------------------------------------------------------
1187    -- LLWU Register Masks
1188    ---------------------------------------------------------------------------- */
1189
1190 /**
1191  * @addtogroup LLWU_Register_Masks LLWU Register Masks
1192  * @{
1193  */
1194
1195 /* PE1 Bit Fields */
1196 #define LLWU_PE1_WUPE0_MASK                      0x3u
1197 #define LLWU_PE1_WUPE0_SHIFT                     0
1198 #define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
1199 #define LLWU_PE1_WUPE1_MASK                      0xCu
1200 #define LLWU_PE1_WUPE1_SHIFT                     2
1201 #define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
1202 #define LLWU_PE1_WUPE2_MASK                      0x30u
1203 #define LLWU_PE1_WUPE2_SHIFT                     4
1204 #define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
1205 #define LLWU_PE1_WUPE3_MASK                      0xC0u
1206 #define LLWU_PE1_WUPE3_SHIFT                     6
1207 #define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
1208 /* PE2 Bit Fields */
1209 #define LLWU_PE2_WUPE4_MASK                      0x3u
1210 #define LLWU_PE2_WUPE4_SHIFT                     0
1211 #define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
1212 #define LLWU_PE2_WUPE5_MASK                      0xCu
1213 #define LLWU_PE2_WUPE5_SHIFT                     2
1214 #define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
1215 #define LLWU_PE2_WUPE6_MASK                      0x30u
1216 #define LLWU_PE2_WUPE6_SHIFT                     4
1217 #define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
1218 #define LLWU_PE2_WUPE7_MASK                      0xC0u
1219 #define LLWU_PE2_WUPE7_SHIFT                     6
1220 #define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
1221 /* ME Bit Fields */
1222 #define LLWU_ME_WUME0_MASK                       0x1u
1223 #define LLWU_ME_WUME0_SHIFT                      0
1224 #define LLWU_ME_WUME1_MASK                       0x2u
1225 #define LLWU_ME_WUME1_SHIFT                      1
1226 #define LLWU_ME_WUME2_MASK                       0x4u
1227 #define LLWU_ME_WUME2_SHIFT                      2
1228 #define LLWU_ME_WUME3_MASK                       0x8u
1229 #define LLWU_ME_WUME3_SHIFT                      3
1230 #define LLWU_ME_WUME4_MASK                       0x10u
1231 #define LLWU_ME_WUME4_SHIFT                      4
1232 #define LLWU_ME_WUME5_MASK                       0x20u
1233 #define LLWU_ME_WUME5_SHIFT                      5
1234 #define LLWU_ME_WUME6_MASK                       0x40u
1235 #define LLWU_ME_WUME6_SHIFT                      6
1236 #define LLWU_ME_WUME7_MASK                       0x80u
1237 #define LLWU_ME_WUME7_SHIFT                      7
1238 /* F1 Bit Fields */
1239 #define LLWU_F1_WUF0_MASK                        0x1u
1240 #define LLWU_F1_WUF0_SHIFT                       0
1241 #define LLWU_F1_WUF1_MASK                        0x2u
1242 #define LLWU_F1_WUF1_SHIFT                       1
1243 #define LLWU_F1_WUF2_MASK                        0x4u
1244 #define LLWU_F1_WUF2_SHIFT                       2
1245 #define LLWU_F1_WUF3_MASK                        0x8u
1246 #define LLWU_F1_WUF3_SHIFT                       3
1247 #define LLWU_F1_WUF4_MASK                        0x10u
1248 #define LLWU_F1_WUF4_SHIFT                       4
1249 #define LLWU_F1_WUF5_MASK                        0x20u
1250 #define LLWU_F1_WUF5_SHIFT                       5
1251 #define LLWU_F1_WUF6_MASK                        0x40u
1252 #define LLWU_F1_WUF6_SHIFT                       6
1253 #define LLWU_F1_WUF7_MASK                        0x80u
1254 #define LLWU_F1_WUF7_SHIFT                       7
1255 /* F3 Bit Fields */
1256 #define LLWU_F3_MWUF0_MASK                       0x1u
1257 #define LLWU_F3_MWUF0_SHIFT                      0
1258 #define LLWU_F3_MWUF1_MASK                       0x2u
1259 #define LLWU_F3_MWUF1_SHIFT                      1
1260 #define LLWU_F3_MWUF2_MASK                       0x4u
1261 #define LLWU_F3_MWUF2_SHIFT                      2
1262 #define LLWU_F3_MWUF3_MASK                       0x8u
1263 #define LLWU_F3_MWUF3_SHIFT                      3
1264 #define LLWU_F3_MWUF4_MASK                       0x10u
1265 #define LLWU_F3_MWUF4_SHIFT                      4
1266 #define LLWU_F3_MWUF5_MASK                       0x20u
1267 #define LLWU_F3_MWUF5_SHIFT                      5
1268 #define LLWU_F3_MWUF6_MASK                       0x40u
1269 #define LLWU_F3_MWUF6_SHIFT                      6
1270 #define LLWU_F3_MWUF7_MASK                       0x80u
1271 #define LLWU_F3_MWUF7_SHIFT                      7
1272 /* FILT1 Bit Fields */
1273 #define LLWU_FILT1_FILTSEL_MASK                  0xFu
1274 #define LLWU_FILT1_FILTSEL_SHIFT                 0
1275 #define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
1276 #define LLWU_FILT1_FILTE_MASK                    0x60u
1277 #define LLWU_FILT1_FILTE_SHIFT                   5
1278 #define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
1279 #define LLWU_FILT1_FILTF_MASK                    0x80u
1280 #define LLWU_FILT1_FILTF_SHIFT                   7
1281 /* FILT2 Bit Fields */
1282 #define LLWU_FILT2_FILTSEL_MASK                  0xFu
1283 #define LLWU_FILT2_FILTSEL_SHIFT                 0
1284 #define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
1285 #define LLWU_FILT2_FILTE_MASK                    0x60u
1286 #define LLWU_FILT2_FILTE_SHIFT                   5
1287 #define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
1288 #define LLWU_FILT2_FILTF_MASK                    0x80u
1289 #define LLWU_FILT2_FILTF_SHIFT                   7
1290
1291 /**
1292  * @}
1293  */ /* end of group LLWU_Register_Masks */
1294
1295
1296 /* LLWU - Peripheral instance base addresses */
1297 /** Peripheral LLWU base address */
1298 #define LLWU_BASE                                (0x4007C000u)
1299 /** Peripheral LLWU base pointer */
1300 #define LLWU                                     ((LLWU_Type *)LLWU_BASE)
1301 /** Array initializer of LLWU peripheral base pointers */
1302 #define LLWU_BASES                               { LLWU }
1303
1304 /**
1305  * @}
1306  */ /* end of group LLWU_Peripheral_Access_Layer */
1307
1308
1309 /* ----------------------------------------------------------------------------
1310    -- LPTMR Peripheral Access Layer
1311    ---------------------------------------------------------------------------- */
1312
1313 /**
1314  * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
1315  * @{
1316  */
1317
1318 /** LPTMR - Register Layout Typedef */
1319 typedef struct {
1320   __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
1321   __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
1322   __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
1323   __I  uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
1324 } LPTMR_Type;
1325
1326 /* ----------------------------------------------------------------------------
1327    -- LPTMR Register Masks
1328    ---------------------------------------------------------------------------- */
1329
1330 /**
1331  * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
1332  * @{
1333  */
1334
1335 /* CSR Bit Fields */
1336 #define LPTMR_CSR_TEN_MASK                       0x1u
1337 #define LPTMR_CSR_TEN_SHIFT                      0
1338 #define LPTMR_CSR_TMS_MASK                       0x2u
1339 #define LPTMR_CSR_TMS_SHIFT                      1
1340 #define LPTMR_CSR_TFC_MASK                       0x4u
1341 #define LPTMR_CSR_TFC_SHIFT                      2
1342 #define LPTMR_CSR_TPP_MASK                       0x8u
1343 #define LPTMR_CSR_TPP_SHIFT                      3
1344 #define LPTMR_CSR_TPS_MASK                       0x30u
1345 #define LPTMR_CSR_TPS_SHIFT                      4
1346 #define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
1347 #define LPTMR_CSR_TIE_MASK                       0x40u
1348 #define LPTMR_CSR_TIE_SHIFT                      6
1349 #define LPTMR_CSR_TCF_MASK                       0x80u
1350 #define LPTMR_CSR_TCF_SHIFT                      7
1351 /* PSR Bit Fields */
1352 #define LPTMR_PSR_PCS_MASK                       0x3u
1353 #define LPTMR_PSR_PCS_SHIFT                      0
1354 #define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
1355 #define LPTMR_PSR_PBYP_MASK                      0x4u
1356 #define LPTMR_PSR_PBYP_SHIFT                     2
1357 #define LPTMR_PSR_PRESCALE_MASK                  0x78u
1358 #define LPTMR_PSR_PRESCALE_SHIFT                 3
1359 #define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
1360 /* CMR Bit Fields */
1361 #define LPTMR_CMR_COMPARE_MASK                   0xFFFFu
1362 #define LPTMR_CMR_COMPARE_SHIFT                  0
1363 #define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
1364 /* CNR Bit Fields */
1365 #define LPTMR_CNR_COUNTER_MASK                   0xFFFFu
1366 #define LPTMR_CNR_COUNTER_SHIFT                  0
1367 #define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
1368
1369 /**
1370  * @}
1371  */ /* end of group LPTMR_Register_Masks */
1372
1373
1374 /* LPTMR - Peripheral instance base addresses */
1375 /** Peripheral LPTMR0 base address */
1376 #define LPTMR0_BASE                              (0x40040000u)
1377 /** Peripheral LPTMR0 base pointer */
1378 #define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
1379 /** Array initializer of LPTMR peripheral base pointers */
1380 #define LPTMR_BASES                              { LPTMR0 }
1381
1382 /**
1383  * @}
1384  */ /* end of group LPTMR_Peripheral_Access_Layer */
1385
1386
1387 /* ----------------------------------------------------------------------------
1388    -- MCG Peripheral Access Layer
1389    ---------------------------------------------------------------------------- */
1390
1391 /**
1392  * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
1393  * @{
1394  */
1395
1396 /** MCG - Register Layout Typedef */
1397 typedef struct {
1398   __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
1399   __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
1400   __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
1401   __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
1402   __I  uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
1403   __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
1404   __I  uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
1405        uint8_t RESERVED_0[1];
1406   __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
1407        uint8_t RESERVED_1[1];
1408   __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
1409   __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
1410 } MCG_Type;
1411
1412 /* ----------------------------------------------------------------------------
1413    -- MCG Register Masks
1414    ---------------------------------------------------------------------------- */
1415
1416 /**
1417  * @addtogroup MCG_Register_Masks MCG Register Masks
1418  * @{
1419  */
1420
1421 /* C1 Bit Fields */
1422 #define MCG_C1_IREFSTEN_MASK                     0x1u
1423 #define MCG_C1_IREFSTEN_SHIFT                    0
1424 #define MCG_C1_IRCLKEN_MASK                      0x2u
1425 #define MCG_C1_IRCLKEN_SHIFT                     1
1426 #define MCG_C1_IREFS_MASK                        0x4u
1427 #define MCG_C1_IREFS_SHIFT                       2
1428 #define MCG_C1_FRDIV_MASK                        0x38u
1429 #define MCG_C1_FRDIV_SHIFT                       3
1430 #define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
1431 #define MCG_C1_CLKS_MASK                         0xC0u
1432 #define MCG_C1_CLKS_SHIFT                        6
1433 #define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
1434 /* C2 Bit Fields */
1435 #define MCG_C2_IRCS_MASK                         0x1u
1436 #define MCG_C2_IRCS_SHIFT                        0
1437 #define MCG_C2_LP_MASK                           0x2u
1438 #define MCG_C2_LP_SHIFT                          1
1439 #define MCG_C2_EREFS0_MASK                       0x4u
1440 #define MCG_C2_EREFS0_SHIFT                      2
1441 #define MCG_C2_HGO0_MASK                         0x8u
1442 #define MCG_C2_HGO0_SHIFT                        3
1443 #define MCG_C2_RANGE0_MASK                       0x30u
1444 #define MCG_C2_RANGE0_SHIFT                      4
1445 #define MCG_C2_RANGE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
1446 #define MCG_C2_LOCRE0_MASK                       0x80u
1447 #define MCG_C2_LOCRE0_SHIFT                      7
1448 /* C3 Bit Fields */
1449 #define MCG_C3_SCTRIM_MASK                       0xFFu
1450 #define MCG_C3_SCTRIM_SHIFT                      0
1451 #define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
1452 /* C4 Bit Fields */
1453 #define MCG_C4_SCFTRIM_MASK                      0x1u
1454 #define MCG_C4_SCFTRIM_SHIFT                     0
1455 #define MCG_C4_FCTRIM_MASK                       0x1Eu
1456 #define MCG_C4_FCTRIM_SHIFT                      1
1457 #define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
1458 #define MCG_C4_DRST_DRS_MASK                     0x60u
1459 #define MCG_C4_DRST_DRS_SHIFT                    5
1460 #define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
1461 #define MCG_C4_DMX32_MASK                        0x80u
1462 #define MCG_C4_DMX32_SHIFT                       7
1463 /* C6 Bit Fields */
1464 #define MCG_C6_CME_MASK                          0x20u
1465 #define MCG_C6_CME_SHIFT                         5
1466 /* S Bit Fields */
1467 #define MCG_S_IRCST_MASK                         0x1u
1468 #define MCG_S_IRCST_SHIFT                        0
1469 #define MCG_S_OSCINIT0_MASK                      0x2u
1470 #define MCG_S_OSCINIT0_SHIFT                     1
1471 #define MCG_S_CLKST_MASK                         0xCu
1472 #define MCG_S_CLKST_SHIFT                        2
1473 #define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
1474 #define MCG_S_IREFST_MASK                        0x10u
1475 #define MCG_S_IREFST_SHIFT                       4
1476 /* SC Bit Fields */
1477 #define MCG_SC_LOCS0_MASK                        0x1u
1478 #define MCG_SC_LOCS0_SHIFT                       0
1479 #define MCG_SC_FCRDIV_MASK                       0xEu
1480 #define MCG_SC_FCRDIV_SHIFT                      1
1481 #define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
1482 #define MCG_SC_FLTPRSRV_MASK                     0x10u
1483 #define MCG_SC_FLTPRSRV_SHIFT                    4
1484 #define MCG_SC_ATMF_MASK                         0x20u
1485 #define MCG_SC_ATMF_SHIFT                        5
1486 #define MCG_SC_ATMS_MASK                         0x40u
1487 #define MCG_SC_ATMS_SHIFT                        6
1488 #define MCG_SC_ATME_MASK                         0x80u
1489 #define MCG_SC_ATME_SHIFT                        7
1490 /* ATCVH Bit Fields */
1491 #define MCG_ATCVH_ATCVH_MASK                     0xFFu
1492 #define MCG_ATCVH_ATCVH_SHIFT                    0
1493 #define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
1494 /* ATCVL Bit Fields */
1495 #define MCG_ATCVL_ATCVL_MASK                     0xFFu
1496 #define MCG_ATCVL_ATCVL_SHIFT                    0
1497 #define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
1498
1499 /**
1500  * @}
1501  */ /* end of group MCG_Register_Masks */
1502
1503
1504 /* MCG - Peripheral instance base addresses */
1505 /** Peripheral MCG base address */
1506 #define MCG_BASE                                 (0x40064000u)
1507 /** Peripheral MCG base pointer */
1508 #define MCG                                      ((MCG_Type *)MCG_BASE)
1509 /** Array initializer of MCG peripheral base pointers */
1510 #define MCG_BASES                                { MCG }
1511
1512 /**
1513  * @}
1514  */ /* end of group MCG_Peripheral_Access_Layer */
1515
1516
1517 /* ----------------------------------------------------------------------------
1518    -- MCM Peripheral Access Layer
1519    ---------------------------------------------------------------------------- */
1520
1521 /**
1522  * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
1523  * @{
1524  */
1525
1526 /** MCM - Register Layout Typedef */
1527 typedef struct {
1528        uint8_t RESERVED_0[8];
1529   __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
1530   __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
1531   __IO uint32_t PLACR;                             /**< Platform Control Register, offset: 0xC */
1532        uint8_t RESERVED_1[48];
1533   __IO uint32_t CPO;                               /**< Compute Operation Control Register, offset: 0x40 */
1534 } MCM_Type;
1535
1536 /* ----------------------------------------------------------------------------
1537    -- MCM Register Masks
1538    ---------------------------------------------------------------------------- */
1539
1540 /**
1541  * @addtogroup MCM_Register_Masks MCM Register Masks
1542  * @{
1543  */
1544
1545 /* PLASC Bit Fields */
1546 #define MCM_PLASC_ASC_MASK                       0xFFu
1547 #define MCM_PLASC_ASC_SHIFT                      0
1548 #define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
1549 /* PLAMC Bit Fields */
1550 #define MCM_PLAMC_AMC_MASK                       0xFFu
1551 #define MCM_PLAMC_AMC_SHIFT                      0
1552 #define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
1553 /* PLACR Bit Fields */
1554 #define MCM_PLACR_ARB_MASK                       0x200u
1555 #define MCM_PLACR_ARB_SHIFT                      9
1556 #define MCM_PLACR_CFCC_MASK                      0x400u
1557 #define MCM_PLACR_CFCC_SHIFT                     10
1558 #define MCM_PLACR_DFCDA_MASK                     0x800u
1559 #define MCM_PLACR_DFCDA_SHIFT                    11
1560 #define MCM_PLACR_DFCIC_MASK                     0x1000u
1561 #define MCM_PLACR_DFCIC_SHIFT                    12
1562 #define MCM_PLACR_DFCC_MASK                      0x2000u
1563 #define MCM_PLACR_DFCC_SHIFT                     13
1564 #define MCM_PLACR_EFDS_MASK                      0x4000u
1565 #define MCM_PLACR_EFDS_SHIFT                     14
1566 #define MCM_PLACR_DFCS_MASK                      0x8000u
1567 #define MCM_PLACR_DFCS_SHIFT                     15
1568 #define MCM_PLACR_ESFC_MASK                      0x10000u
1569 #define MCM_PLACR_ESFC_SHIFT                     16
1570 /* CPO Bit Fields */
1571 #define MCM_CPO_CPOREQ_MASK                      0x1u
1572 #define MCM_CPO_CPOREQ_SHIFT                     0
1573 #define MCM_CPO_CPOACK_MASK                      0x2u
1574 #define MCM_CPO_CPOACK_SHIFT                     1
1575 #define MCM_CPO_CPOWOI_MASK                      0x4u
1576 #define MCM_CPO_CPOWOI_SHIFT                     2
1577
1578 /**
1579  * @}
1580  */ /* end of group MCM_Register_Masks */
1581
1582
1583 /* MCM - Peripheral instance base addresses */
1584 /** Peripheral MCM base address */
1585 #define MCM_BASE                                 (0xF0003000u)
1586 /** Peripheral MCM base pointer */
1587 #define MCM                                      ((MCM_Type *)MCM_BASE)
1588 /** Array initializer of MCM peripheral base pointers */
1589 #define MCM_BASES                                { MCM }
1590
1591 /**
1592  * @}
1593  */ /* end of group MCM_Peripheral_Access_Layer */
1594
1595
1596 /* ----------------------------------------------------------------------------
1597    -- MTB Peripheral Access Layer
1598    ---------------------------------------------------------------------------- */
1599
1600 /**
1601  * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
1602  * @{
1603  */
1604
1605 /** MTB - Register Layout Typedef */
1606 typedef struct {
1607   __IO uint32_t POSITION;                          /**< MTB Position Register, offset: 0x0 */
1608   __IO uint32_t MASTER;                            /**< MTB Master Register, offset: 0x4 */
1609   __IO uint32_t FLOW;                              /**< MTB Flow Register, offset: 0x8 */
1610   __I  uint32_t BASE;                              /**< MTB Base Register, offset: 0xC */
1611        uint8_t RESERVED_0[3824];
1612   __I  uint32_t MODECTRL;                          /**< Integration Mode Control Register, offset: 0xF00 */
1613        uint8_t RESERVED_1[156];
1614   __I  uint32_t TAGSET;                            /**< Claim TAG Set Register, offset: 0xFA0 */
1615   __I  uint32_t TAGCLEAR;                          /**< Claim TAG Clear Register, offset: 0xFA4 */
1616        uint8_t RESERVED_2[8];
1617   __I  uint32_t LOCKACCESS;                        /**< Lock Access Register, offset: 0xFB0 */
1618   __I  uint32_t LOCKSTAT;                          /**< Lock Status Register, offset: 0xFB4 */
1619   __I  uint32_t AUTHSTAT;                          /**< Authentication Status Register, offset: 0xFB8 */
1620   __I  uint32_t DEVICEARCH;                        /**< Device Architecture Register, offset: 0xFBC */
1621        uint8_t RESERVED_3[8];
1622   __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
1623   __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
1624   __I  uint32_t PERIPHID[8];                       /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
1625   __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
1626 } MTB_Type;
1627
1628 /* ----------------------------------------------------------------------------
1629    -- MTB Register Masks
1630    ---------------------------------------------------------------------------- */
1631
1632 /**
1633  * @addtogroup MTB_Register_Masks MTB Register Masks
1634  * @{
1635  */
1636
1637 /* POSITION Bit Fields */
1638 #define MTB_POSITION_WRAP_MASK                   0x4u
1639 #define MTB_POSITION_WRAP_SHIFT                  2
1640 #define MTB_POSITION_POINTER_MASK                0xFFFFFFF8u
1641 #define MTB_POSITION_POINTER_SHIFT               3
1642 #define MTB_POSITION_POINTER(x)                  (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
1643 /* MASTER Bit Fields */
1644 #define MTB_MASTER_MASK_MASK                     0x1Fu
1645 #define MTB_MASTER_MASK_SHIFT                    0
1646 #define MTB_MASTER_MASK(x)                       (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
1647 #define MTB_MASTER_TSTARTEN_MASK                 0x20u
1648 #define MTB_MASTER_TSTARTEN_SHIFT                5
1649 #define MTB_MASTER_TSTOPEN_MASK                  0x40u
1650 #define MTB_MASTER_TSTOPEN_SHIFT                 6
1651 #define MTB_MASTER_SFRWPRIV_MASK                 0x80u
1652 #define MTB_MASTER_SFRWPRIV_SHIFT                7
1653 #define MTB_MASTER_RAMPRIV_MASK                  0x100u
1654 #define MTB_MASTER_RAMPRIV_SHIFT                 8
1655 #define MTB_MASTER_HALTREQ_MASK                  0x200u
1656 #define MTB_MASTER_HALTREQ_SHIFT                 9
1657 #define MTB_MASTER_EN_MASK                       0x80000000u
1658 #define MTB_MASTER_EN_SHIFT                      31
1659 /* FLOW Bit Fields */
1660 #define MTB_FLOW_AUTOSTOP_MASK                   0x1u
1661 #define MTB_FLOW_AUTOSTOP_SHIFT                  0
1662 #define MTB_FLOW_AUTOHALT_MASK                   0x2u
1663 #define MTB_FLOW_AUTOHALT_SHIFT                  1
1664 #define MTB_FLOW_WATERMARK_MASK                  0xFFFFFFF8u
1665 #define MTB_FLOW_WATERMARK_SHIFT                 3
1666 #define MTB_FLOW_WATERMARK(x)                    (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
1667 /* BASE Bit Fields */
1668 #define MTB_BASE_BASEADDR_MASK                   0xFFFFFFFFu
1669 #define MTB_BASE_BASEADDR_SHIFT                  0
1670 #define MTB_BASE_BASEADDR(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
1671 /* MODECTRL Bit Fields */
1672 #define MTB_MODECTRL_MODECTRL_MASK               0xFFFFFFFFu
1673 #define MTB_MODECTRL_MODECTRL_SHIFT              0
1674 #define MTB_MODECTRL_MODECTRL(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
1675 /* TAGSET Bit Fields */
1676 #define MTB_TAGSET_TAGSET_MASK                   0xFFFFFFFFu
1677 #define MTB_TAGSET_TAGSET_SHIFT                  0
1678 #define MTB_TAGSET_TAGSET(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
1679 /* TAGCLEAR Bit Fields */
1680 #define MTB_TAGCLEAR_TAGCLEAR_MASK               0xFFFFFFFFu
1681 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT              0
1682 #define MTB_TAGCLEAR_TAGCLEAR(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
1683 /* LOCKACCESS Bit Fields */
1684 #define MTB_LOCKACCESS_LOCKACCESS_MASK           0xFFFFFFFFu
1685 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT          0
1686 #define MTB_LOCKACCESS_LOCKACCESS(x)             (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
1687 /* LOCKSTAT Bit Fields */
1688 #define MTB_LOCKSTAT_LOCKSTAT_MASK               0xFFFFFFFFu
1689 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT              0
1690 #define MTB_LOCKSTAT_LOCKSTAT(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
1691 /* AUTHSTAT Bit Fields */
1692 #define MTB_AUTHSTAT_BIT0_MASK                   0x1u
1693 #define MTB_AUTHSTAT_BIT0_SHIFT                  0
1694 #define MTB_AUTHSTAT_BIT1_MASK                   0x2u
1695 #define MTB_AUTHSTAT_BIT1_SHIFT                  1
1696 #define MTB_AUTHSTAT_BIT2_MASK                   0x4u
1697 #define MTB_AUTHSTAT_BIT2_SHIFT                  2
1698 #define MTB_AUTHSTAT_BIT3_MASK                   0x8u
1699 #define MTB_AUTHSTAT_BIT3_SHIFT                  3
1700 /* DEVICEARCH Bit Fields */
1701 #define MTB_DEVICEARCH_DEVICEARCH_MASK           0xFFFFFFFFu
1702 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT          0
1703 #define MTB_DEVICEARCH_DEVICEARCH(x)             (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
1704 /* DEVICECFG Bit Fields */
1705 #define MTB_DEVICECFG_DEVICECFG_MASK             0xFFFFFFFFu
1706 #define MTB_DEVICECFG_DEVICECFG_SHIFT            0
1707 #define MTB_DEVICECFG_DEVICECFG(x)               (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
1708 /* DEVICETYPID Bit Fields */
1709 #define MTB_DEVICETYPID_DEVICETYPID_MASK         0xFFFFFFFFu
1710 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT        0
1711 #define MTB_DEVICETYPID_DEVICETYPID(x)           (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
1712 /* PERIPHID Bit Fields */
1713 #define MTB_PERIPHID_PERIPHID_MASK               0xFFFFFFFFu
1714 #define MTB_PERIPHID_PERIPHID_SHIFT              0
1715 #define MTB_PERIPHID_PERIPHID(x)                 (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
1716 /* COMPID Bit Fields */
1717 #define MTB_COMPID_COMPID_MASK                   0xFFFFFFFFu
1718 #define MTB_COMPID_COMPID_SHIFT                  0
1719 #define MTB_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
1720
1721 /**
1722  * @}
1723  */ /* end of group MTB_Register_Masks */
1724
1725
1726 /* MTB - Peripheral instance base addresses */
1727 /** Peripheral MTB base address */
1728 #define MTB_BASE                                 (0xF0000000u)
1729 /** Peripheral MTB base pointer */
1730 #define MTB                                      ((MTB_Type *)MTB_BASE)
1731 /** Array initializer of MTB peripheral base pointers */
1732 #define MTB_BASES                                { MTB }
1733
1734 /**
1735  * @}
1736  */ /* end of group MTB_Peripheral_Access_Layer */
1737
1738
1739 /* ----------------------------------------------------------------------------
1740    -- MTBDWT Peripheral Access Layer
1741    ---------------------------------------------------------------------------- */
1742
1743 /**
1744  * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
1745  * @{
1746  */
1747
1748 /** MTBDWT - Register Layout Typedef */
1749 typedef struct {
1750   __I  uint32_t CTRL;                              /**< MTB DWT Control Register, offset: 0x0 */
1751        uint8_t RESERVED_0[28];
1752   struct {                                         /* offset: 0x20, array step: 0x10 */
1753     __IO uint32_t COMP;                              /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
1754     __IO uint32_t MASK;                              /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
1755     __IO uint32_t FCT;                               /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
1756          uint8_t RESERVED_0[4];
1757   } COMPARATOR[2];
1758        uint8_t RESERVED_1[448];
1759   __IO uint32_t TBCTRL;                            /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
1760        uint8_t RESERVED_2[3524];
1761   __I  uint32_t DEVICECFG;                         /**< Device Configuration Register, offset: 0xFC8 */
1762   __I  uint32_t DEVICETYPID;                       /**< Device Type Identifier Register, offset: 0xFCC */
1763   __I  uint32_t PERIPHID[8];                       /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
1764   __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
1765 } MTBDWT_Type;
1766
1767 /* ----------------------------------------------------------------------------
1768    -- MTBDWT Register Masks
1769    ---------------------------------------------------------------------------- */
1770
1771 /**
1772  * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
1773  * @{
1774  */
1775
1776 /* CTRL Bit Fields */
1777 #define MTBDWT_CTRL_DWTCFGCTRL_MASK              0xFFFFFFFu
1778 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT             0
1779 #define MTBDWT_CTRL_DWTCFGCTRL(x)                (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
1780 #define MTBDWT_CTRL_NUMCMP_MASK                  0xF0000000u
1781 #define MTBDWT_CTRL_NUMCMP_SHIFT                 28
1782 #define MTBDWT_CTRL_NUMCMP(x)                    (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
1783 /* COMP Bit Fields */
1784 #define MTBDWT_COMP_COMP_MASK                    0xFFFFFFFFu
1785 #define MTBDWT_COMP_COMP_SHIFT                   0
1786 #define MTBDWT_COMP_COMP(x)                      (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
1787 /* MASK Bit Fields */
1788 #define MTBDWT_MASK_MASK_MASK                    0x1Fu
1789 #define MTBDWT_MASK_MASK_SHIFT                   0
1790 #define MTBDWT_MASK_MASK(x)                      (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
1791 /* FCT Bit Fields */
1792 #define MTBDWT_FCT_FUNCTION_MASK                 0xFu
1793 #define MTBDWT_FCT_FUNCTION_SHIFT                0
1794 #define MTBDWT_FCT_FUNCTION(x)                   (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
1795 #define MTBDWT_FCT_DATAVMATCH_MASK               0x100u
1796 #define MTBDWT_FCT_DATAVMATCH_SHIFT              8
1797 #define MTBDWT_FCT_DATAVSIZE_MASK                0xC00u
1798 #define MTBDWT_FCT_DATAVSIZE_SHIFT               10
1799 #define MTBDWT_FCT_DATAVSIZE(x)                  (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
1800 #define MTBDWT_FCT_DATAVADDR0_MASK               0xF000u
1801 #define MTBDWT_FCT_DATAVADDR0_SHIFT              12
1802 #define MTBDWT_FCT_DATAVADDR0(x)                 (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
1803 #define MTBDWT_FCT_MATCHED_MASK                  0x1000000u
1804 #define MTBDWT_FCT_MATCHED_SHIFT                 24
1805 /* TBCTRL Bit Fields */
1806 #define MTBDWT_TBCTRL_ACOMP0_MASK                0x1u
1807 #define MTBDWT_TBCTRL_ACOMP0_SHIFT               0
1808 #define MTBDWT_TBCTRL_ACOMP1_MASK                0x2u
1809 #define MTBDWT_TBCTRL_ACOMP1_SHIFT               1
1810 #define MTBDWT_TBCTRL_NUMCOMP_MASK               0xF0000000u
1811 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT              28
1812 #define MTBDWT_TBCTRL_NUMCOMP(x)                 (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
1813 /* DEVICECFG Bit Fields */
1814 #define MTBDWT_DEVICECFG_DEVICECFG_MASK          0xFFFFFFFFu
1815 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT         0
1816 #define MTBDWT_DEVICECFG_DEVICECFG(x)            (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
1817 /* DEVICETYPID Bit Fields */
1818 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK      0xFFFFFFFFu
1819 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT     0
1820 #define MTBDWT_DEVICETYPID_DEVICETYPID(x)        (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
1821 /* PERIPHID Bit Fields */
1822 #define MTBDWT_PERIPHID_PERIPHID_MASK            0xFFFFFFFFu
1823 #define MTBDWT_PERIPHID_PERIPHID_SHIFT           0
1824 #define MTBDWT_PERIPHID_PERIPHID(x)              (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
1825 /* COMPID Bit Fields */
1826 #define MTBDWT_COMPID_COMPID_MASK                0xFFFFFFFFu
1827 #define MTBDWT_COMPID_COMPID_SHIFT               0
1828 #define MTBDWT_COMPID_COMPID(x)                  (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
1829
1830 /**
1831  * @}
1832  */ /* end of group MTBDWT_Register_Masks */
1833
1834
1835 /* MTBDWT - Peripheral instance base addresses */
1836 /** Peripheral MTBDWT base address */
1837 #define MTBDWT_BASE                              (0xF0001000u)
1838 /** Peripheral MTBDWT base pointer */
1839 #define MTBDWT                                   ((MTBDWT_Type *)MTBDWT_BASE)
1840 /** Array initializer of MTBDWT peripheral base pointers */
1841 #define MTBDWT_BASES                             { MTBDWT }
1842
1843 /**
1844  * @}
1845  */ /* end of group MTBDWT_Peripheral_Access_Layer */
1846
1847
1848 /* ----------------------------------------------------------------------------
1849    -- NV Peripheral Access Layer
1850    ---------------------------------------------------------------------------- */
1851
1852 /**
1853  * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
1854  * @{
1855  */
1856
1857 /** NV - Register Layout Typedef */
1858 typedef struct {
1859   __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
1860   __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
1861   __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
1862   __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
1863   __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
1864   __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
1865   __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
1866   __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
1867   __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
1868   __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
1869   __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
1870   __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
1871   __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
1872   __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
1873 } NV_Type;
1874
1875 /* ----------------------------------------------------------------------------
1876    -- NV Register Masks
1877    ---------------------------------------------------------------------------- */
1878
1879 /**
1880  * @addtogroup NV_Register_Masks NV Register Masks
1881  * @{
1882  */
1883
1884 /* BACKKEY3 Bit Fields */
1885 #define NV_BACKKEY3_KEY_MASK                     0xFFu
1886 #define NV_BACKKEY3_KEY_SHIFT                    0
1887 #define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
1888 /* BACKKEY2 Bit Fields */
1889 #define NV_BACKKEY2_KEY_MASK                     0xFFu
1890 #define NV_BACKKEY2_KEY_SHIFT                    0
1891 #define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
1892 /* BACKKEY1 Bit Fields */
1893 #define NV_BACKKEY1_KEY_MASK                     0xFFu
1894 #define NV_BACKKEY1_KEY_SHIFT                    0
1895 #define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
1896 /* BACKKEY0 Bit Fields */
1897 #define NV_BACKKEY0_KEY_MASK                     0xFFu
1898 #define NV_BACKKEY0_KEY_SHIFT                    0
1899 #define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
1900 /* BACKKEY7 Bit Fields */
1901 #define NV_BACKKEY7_KEY_MASK                     0xFFu
1902 #define NV_BACKKEY7_KEY_SHIFT                    0
1903 #define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
1904 /* BACKKEY6 Bit Fields */
1905 #define NV_BACKKEY6_KEY_MASK                     0xFFu
1906 #define NV_BACKKEY6_KEY_SHIFT                    0
1907 #define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
1908 /* BACKKEY5 Bit Fields */
1909 #define NV_BACKKEY5_KEY_MASK                     0xFFu
1910 #define NV_BACKKEY5_KEY_SHIFT                    0
1911 #define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
1912 /* BACKKEY4 Bit Fields */
1913 #define NV_BACKKEY4_KEY_MASK                     0xFFu
1914 #define NV_BACKKEY4_KEY_SHIFT                    0
1915 #define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
1916 /* FPROT3 Bit Fields */
1917 #define NV_FPROT3_PROT_MASK                      0xFFu
1918 #define NV_FPROT3_PROT_SHIFT                     0
1919 #define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
1920 /* FPROT2 Bit Fields */
1921 #define NV_FPROT2_PROT_MASK                      0xFFu
1922 #define NV_FPROT2_PROT_SHIFT                     0
1923 #define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
1924 /* FPROT1 Bit Fields */
1925 #define NV_FPROT1_PROT_MASK                      0xFFu
1926 #define NV_FPROT1_PROT_SHIFT                     0
1927 #define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
1928 /* FPROT0 Bit Fields */
1929 #define NV_FPROT0_PROT_MASK                      0xFFu
1930 #define NV_FPROT0_PROT_SHIFT                     0
1931 #define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
1932 /* FSEC Bit Fields */
1933 #define NV_FSEC_SEC_MASK                         0x3u
1934 #define NV_FSEC_SEC_SHIFT                        0
1935 #define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
1936 #define NV_FSEC_FSLACC_MASK                      0xCu
1937 #define NV_FSEC_FSLACC_SHIFT                     2
1938 #define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
1939 #define NV_FSEC_MEEN_MASK                        0x30u
1940 #define NV_FSEC_MEEN_SHIFT                       4
1941 #define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
1942 #define NV_FSEC_KEYEN_MASK                       0xC0u
1943 #define NV_FSEC_KEYEN_SHIFT                      6
1944 #define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
1945 /* FOPT Bit Fields */
1946 #define NV_FOPT_LPBOOT0_MASK                     0x1u
1947 #define NV_FOPT_LPBOOT0_SHIFT                    0
1948 #define NV_FOPT_EZPORT_DIS_MASK                  0x2u
1949 #define NV_FOPT_EZPORT_DIS_SHIFT                 1
1950 #define NV_FOPT_NMI_DIS_MASK                     0x4u
1951 #define NV_FOPT_NMI_DIS_SHIFT                    2
1952 #define NV_FOPT_RESET_PIN_CFG_MASK               0x8u
1953 #define NV_FOPT_RESET_PIN_CFG_SHIFT              3
1954 #define NV_FOPT_LPBOOT1_MASK                     0x10u
1955 #define NV_FOPT_LPBOOT1_SHIFT                    4
1956 #define NV_FOPT_FAST_INIT_MASK                   0x20u
1957 #define NV_FOPT_FAST_INIT_SHIFT                  5
1958
1959 /**
1960  * @}
1961  */ /* end of group NV_Register_Masks */
1962
1963
1964 /* NV - Peripheral instance base addresses */
1965 /** Peripheral FTFA_FlashConfig base address */
1966 #define FTFA_FlashConfig_BASE                    (0x400u)
1967 /** Peripheral FTFA_FlashConfig base pointer */
1968 #define FTFA_FlashConfig                         ((NV_Type *)FTFA_FlashConfig_BASE)
1969 /** Array initializer of NV peripheral base pointers */
1970 #define NV_BASES                                 { FTFA_FlashConfig }
1971
1972 /**
1973  * @}
1974  */ /* end of group NV_Peripheral_Access_Layer */
1975
1976
1977 /* ----------------------------------------------------------------------------
1978    -- OSC Peripheral Access Layer
1979    ---------------------------------------------------------------------------- */
1980
1981 /**
1982  * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
1983  * @{
1984  */
1985
1986 /** OSC - Register Layout Typedef */
1987 typedef struct {
1988   __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
1989 } OSC_Type;
1990
1991 /* ----------------------------------------------------------------------------
1992    -- OSC Register Masks
1993    ---------------------------------------------------------------------------- */
1994
1995 /**
1996  * @addtogroup OSC_Register_Masks OSC Register Masks
1997  * @{
1998  */
1999
2000 /* CR Bit Fields */
2001 #define OSC_CR_SC16P_MASK                        0x1u
2002 #define OSC_CR_SC16P_SHIFT                       0
2003 #define OSC_CR_SC8P_MASK                         0x2u
2004 #define OSC_CR_SC8P_SHIFT                        1
2005 #define OSC_CR_SC4P_MASK                         0x4u
2006 #define OSC_CR_SC4P_SHIFT                        2
2007 #define OSC_CR_SC2P_MASK                         0x8u
2008 #define OSC_CR_SC2P_SHIFT                        3
2009 #define OSC_CR_EREFSTEN_MASK                     0x20u
2010 #define OSC_CR_EREFSTEN_SHIFT                    5
2011 #define OSC_CR_ERCLKEN_MASK                      0x80u
2012 #define OSC_CR_ERCLKEN_SHIFT                     7
2013
2014 /**
2015  * @}
2016  */ /* end of group OSC_Register_Masks */
2017
2018
2019 /* OSC - Peripheral instance base addresses */
2020 /** Peripheral OSC0 base address */
2021 #define OSC0_BASE                                (0x40065000u)
2022 /** Peripheral OSC0 base pointer */
2023 #define OSC0                                     ((OSC_Type *)OSC0_BASE)
2024 /** Array initializer of OSC peripheral base pointers */
2025 #define OSC_BASES                                { OSC0 }
2026
2027 /**
2028  * @}
2029  */ /* end of group OSC_Peripheral_Access_Layer */
2030
2031
2032 /* ----------------------------------------------------------------------------
2033    -- PIT Peripheral Access Layer
2034    ---------------------------------------------------------------------------- */
2035
2036 /**
2037  * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
2038  * @{
2039  */
2040
2041 /** PIT - Register Layout Typedef */
2042 typedef struct {
2043   __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
2044        uint8_t RESERVED_0[220];
2045   __I  uint32_t LTMR64H;                           /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
2046   __I  uint32_t LTMR64L;                           /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
2047        uint8_t RESERVED_1[24];
2048   struct {                                         /* offset: 0x100, array step: 0x10 */
2049     __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
2050     __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
2051     __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
2052     __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
2053   } CHANNEL[2];
2054 } PIT_Type;
2055
2056 /* ----------------------------------------------------------------------------
2057    -- PIT Register Masks
2058    ---------------------------------------------------------------------------- */
2059
2060 /**
2061  * @addtogroup PIT_Register_Masks PIT Register Masks
2062  * @{
2063  */
2064
2065 /* MCR Bit Fields */
2066 #define PIT_MCR_FRZ_MASK                         0x1u
2067 #define PIT_MCR_FRZ_SHIFT                        0
2068 #define PIT_MCR_MDIS_MASK                        0x2u
2069 #define PIT_MCR_MDIS_SHIFT                       1
2070 /* LTMR64H Bit Fields */
2071 #define PIT_LTMR64H_LTH_MASK                     0xFFFFFFFFu
2072 #define PIT_LTMR64H_LTH_SHIFT                    0
2073 #define PIT_LTMR64H_LTH(x)                       (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
2074 /* LTMR64L Bit Fields */
2075 #define PIT_LTMR64L_LTL_MASK                     0xFFFFFFFFu
2076 #define PIT_LTMR64L_LTL_SHIFT                    0
2077 #define PIT_LTMR64L_LTL(x)                       (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
2078 /* LDVAL Bit Fields */
2079 #define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
2080 #define PIT_LDVAL_TSV_SHIFT                      0
2081 #define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
2082 /* CVAL Bit Fields */
2083 #define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
2084 #define PIT_CVAL_TVL_SHIFT                       0
2085 #define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
2086 /* TCTRL Bit Fields */
2087 #define PIT_TCTRL_TEN_MASK                       0x1u
2088 #define PIT_TCTRL_TEN_SHIFT                      0
2089 #define PIT_TCTRL_TIE_MASK                       0x2u
2090 #define PIT_TCTRL_TIE_SHIFT                      1
2091 #define PIT_TCTRL_CHN_MASK                       0x4u
2092 #define PIT_TCTRL_CHN_SHIFT                      2
2093 /* TFLG Bit Fields */
2094 #define PIT_TFLG_TIF_MASK                        0x1u
2095 #define PIT_TFLG_TIF_SHIFT                       0
2096
2097 /**
2098  * @}
2099  */ /* end of group PIT_Register_Masks */
2100
2101
2102 /* PIT - Peripheral instance base addresses */
2103 /** Peripheral PIT base address */
2104 #define PIT_BASE                                 (0x40037000u)
2105 /** Peripheral PIT base pointer */
2106 #define PIT                                      ((PIT_Type *)PIT_BASE)
2107 /** Array initializer of PIT peripheral base pointers */
2108 #define PIT_BASES                                { PIT }
2109
2110 /**
2111  * @}
2112  */ /* end of group PIT_Peripheral_Access_Layer */
2113
2114
2115 /* ----------------------------------------------------------------------------
2116    -- PMC Peripheral Access Layer
2117    ---------------------------------------------------------------------------- */
2118
2119 /**
2120  * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
2121  * @{
2122  */
2123
2124 /** PMC - Register Layout Typedef */
2125 typedef struct {
2126   __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
2127   __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
2128   __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
2129 } PMC_Type;
2130
2131 /* ----------------------------------------------------------------------------
2132    -- PMC Register Masks
2133    ---------------------------------------------------------------------------- */
2134
2135 /**
2136  * @addtogroup PMC_Register_Masks PMC Register Masks
2137  * @{
2138  */
2139
2140 /* LVDSC1 Bit Fields */
2141 #define PMC_LVDSC1_LVDV_MASK                     0x3u
2142 #define PMC_LVDSC1_LVDV_SHIFT                    0
2143 #define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
2144 #define PMC_LVDSC1_LVDRE_MASK                    0x10u
2145 #define PMC_LVDSC1_LVDRE_SHIFT                   4
2146 #define PMC_LVDSC1_LVDIE_MASK                    0x20u
2147 #define PMC_LVDSC1_LVDIE_SHIFT                   5
2148 #define PMC_LVDSC1_LVDACK_MASK                   0x40u
2149 #define PMC_LVDSC1_LVDACK_SHIFT                  6
2150 #define PMC_LVDSC1_LVDF_MASK                     0x80u
2151 #define PMC_LVDSC1_LVDF_SHIFT                    7
2152 /* LVDSC2 Bit Fields */
2153 #define PMC_LVDSC2_LVWV_MASK                     0x3u
2154 #define PMC_LVDSC2_LVWV_SHIFT                    0
2155 #define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
2156 #define PMC_LVDSC2_LVWIE_MASK                    0x20u
2157 #define PMC_LVDSC2_LVWIE_SHIFT                   5
2158 #define PMC_LVDSC2_LVWACK_MASK                   0x40u
2159 #define PMC_LVDSC2_LVWACK_SHIFT                  6
2160 #define PMC_LVDSC2_LVWF_MASK                     0x80u
2161 #define PMC_LVDSC2_LVWF_SHIFT                    7
2162 /* REGSC Bit Fields */
2163 #define PMC_REGSC_BGBE_MASK                      0x1u
2164 #define PMC_REGSC_BGBE_SHIFT                     0
2165 #define PMC_REGSC_REGONS_MASK                    0x4u
2166 #define PMC_REGSC_REGONS_SHIFT                   2
2167 #define PMC_REGSC_ACKISO_MASK                    0x8u
2168 #define PMC_REGSC_ACKISO_SHIFT                   3
2169 #define PMC_REGSC_BGEN_MASK                      0x10u
2170 #define PMC_REGSC_BGEN_SHIFT                     4
2171
2172 /**
2173  * @}
2174  */ /* end of group PMC_Register_Masks */
2175
2176
2177 /* PMC - Peripheral instance base addresses */
2178 /** Peripheral PMC base address */
2179 #define PMC_BASE                                 (0x4007D000u)
2180 /** Peripheral PMC base pointer */
2181 #define PMC                                      ((PMC_Type *)PMC_BASE)
2182 /** Array initializer of PMC peripheral base pointers */
2183 #define PMC_BASES                                { PMC }
2184
2185 /**
2186  * @}
2187  */ /* end of group PMC_Peripheral_Access_Layer */
2188
2189
2190 /* ----------------------------------------------------------------------------
2191    -- PORT Peripheral Access Layer
2192    ---------------------------------------------------------------------------- */
2193
2194 /**
2195  * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
2196  * @{
2197  */
2198
2199 /** PORT - Register Layout Typedef */
2200 typedef struct {
2201   __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
2202   __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
2203   __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
2204        uint8_t RESERVED_0[24];
2205   __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
2206 } PORT_Type;
2207
2208 /* ----------------------------------------------------------------------------
2209    -- PORT Register Masks
2210    ---------------------------------------------------------------------------- */
2211
2212 /**
2213  * @addtogroup PORT_Register_Masks PORT Register Masks
2214  * @{
2215  */
2216
2217 /* PCR Bit Fields */
2218 #define PORT_PCR_PS_MASK                         0x1u
2219 #define PORT_PCR_PS_SHIFT                        0
2220 #define PORT_PCR_PE_MASK                         0x2u
2221 #define PORT_PCR_PE_SHIFT                        1
2222 #define PORT_PCR_SRE_MASK                        0x4u
2223 #define PORT_PCR_SRE_SHIFT                       2
2224 #define PORT_PCR_PFE_MASK                        0x10u
2225 #define PORT_PCR_PFE_SHIFT                       4
2226 #define PORT_PCR_DSE_MASK                        0x40u
2227 #define PORT_PCR_DSE_SHIFT                       6
2228 #define PORT_PCR_MUX_MASK                        0x700u
2229 #define PORT_PCR_MUX_SHIFT                       8
2230 #define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
2231 #define PORT_PCR_IRQC_MASK                       0xF0000u
2232 #define PORT_PCR_IRQC_SHIFT                      16
2233 #define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
2234 #define PORT_PCR_ISF_MASK                        0x1000000u
2235 #define PORT_PCR_ISF_SHIFT                       24
2236 /* GPCLR Bit Fields */
2237 #define PORT_GPCLR_GPWD_MASK                     0xFFFFu
2238 #define PORT_GPCLR_GPWD_SHIFT                    0
2239 #define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
2240 #define PORT_GPCLR_GPWE_MASK                     0xFFFF0000u
2241 #define PORT_GPCLR_GPWE_SHIFT                    16
2242 #define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
2243 /* GPCHR Bit Fields */
2244 #define PORT_GPCHR_GPWD_MASK                     0xFFFFu
2245 #define PORT_GPCHR_GPWD_SHIFT                    0
2246 #define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
2247 #define PORT_GPCHR_GPWE_MASK                     0xFFFF0000u
2248 #define PORT_GPCHR_GPWE_SHIFT                    16
2249 #define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
2250 /* ISFR Bit Fields */
2251 #define PORT_ISFR_ISF_MASK                       0xFFFFFFFFu
2252 #define PORT_ISFR_ISF_SHIFT                      0
2253 #define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
2254
2255 /**
2256  * @}
2257  */ /* end of group PORT_Register_Masks */
2258
2259
2260 /* PORT - Peripheral instance base addresses */
2261 /** Peripheral PORTA base address */
2262 #define PORTA_BASE                               (0x40049000u)
2263 /** Peripheral PORTA base pointer */
2264 #define PORTA                                    ((PORT_Type *)PORTA_BASE)
2265 /** Peripheral PORTB base address */
2266 #define PORTB_BASE                               (0x4004A000u)
2267 /** Peripheral PORTB base pointer */
2268 #define PORTB                                    ((PORT_Type *)PORTB_BASE)
2269 /** Array initializer of PORT peripheral base pointers */
2270 #define PORT_BASES                               { PORTA, PORTB }
2271
2272 /**
2273  * @}
2274  */ /* end of group PORT_Peripheral_Access_Layer */
2275
2276
2277 /* ----------------------------------------------------------------------------
2278    -- RCM Peripheral Access Layer
2279    ---------------------------------------------------------------------------- */
2280
2281 /**
2282  * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
2283  * @{
2284  */
2285
2286 /** RCM - Register Layout Typedef */
2287 typedef struct {
2288   __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
2289   __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
2290        uint8_t RESERVED_0[2];
2291   __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
2292   __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
2293 } RCM_Type;
2294
2295 /* ----------------------------------------------------------------------------
2296    -- RCM Register Masks
2297    ---------------------------------------------------------------------------- */
2298
2299 /**
2300  * @addtogroup RCM_Register_Masks RCM Register Masks
2301  * @{
2302  */
2303
2304 /* SRS0 Bit Fields */
2305 #define RCM_SRS0_WAKEUP_MASK                     0x1u
2306 #define RCM_SRS0_WAKEUP_SHIFT                    0
2307 #define RCM_SRS0_LVD_MASK                        0x2u
2308 #define RCM_SRS0_LVD_SHIFT                       1
2309 #define RCM_SRS0_LOC_MASK                        0x4u
2310 #define RCM_SRS0_LOC_SHIFT                       2
2311 #define RCM_SRS0_WDOG_MASK                       0x20u
2312 #define RCM_SRS0_WDOG_SHIFT                      5
2313 #define RCM_SRS0_PIN_MASK                        0x40u
2314 #define RCM_SRS0_PIN_SHIFT                       6
2315 #define RCM_SRS0_POR_MASK                        0x80u
2316 #define RCM_SRS0_POR_SHIFT                       7
2317 /* SRS1 Bit Fields */
2318 #define RCM_SRS1_LOCKUP_MASK                     0x2u
2319 #define RCM_SRS1_LOCKUP_SHIFT                    1
2320 #define RCM_SRS1_SW_MASK                         0x4u
2321 #define RCM_SRS1_SW_SHIFT                        2
2322 #define RCM_SRS1_MDM_AP_MASK                     0x8u
2323 #define RCM_SRS1_MDM_AP_SHIFT                    3
2324 #define RCM_SRS1_SACKERR_MASK                    0x20u
2325 #define RCM_SRS1_SACKERR_SHIFT                   5
2326 /* RPFC Bit Fields */
2327 #define RCM_RPFC_RSTFLTSRW_MASK                  0x3u
2328 #define RCM_RPFC_RSTFLTSRW_SHIFT                 0
2329 #define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
2330 #define RCM_RPFC_RSTFLTSS_MASK                   0x4u
2331 #define RCM_RPFC_RSTFLTSS_SHIFT                  2
2332 /* RPFW Bit Fields */
2333 #define RCM_RPFW_RSTFLTSEL_MASK                  0x1Fu
2334 #define RCM_RPFW_RSTFLTSEL_SHIFT                 0
2335 #define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
2336
2337 /**
2338  * @}
2339  */ /* end of group RCM_Register_Masks */
2340
2341
2342 /* RCM - Peripheral instance base addresses */
2343 /** Peripheral RCM base address */
2344 #define RCM_BASE                                 (0x4007F000u)
2345 /** Peripheral RCM base pointer */
2346 #define RCM                                      ((RCM_Type *)RCM_BASE)
2347 /** Array initializer of RCM peripheral base pointers */
2348 #define RCM_BASES                                { RCM }
2349
2350 /**
2351  * @}
2352  */ /* end of group RCM_Peripheral_Access_Layer */
2353
2354
2355 /* ----------------------------------------------------------------------------
2356    -- ROM Peripheral Access Layer
2357    ---------------------------------------------------------------------------- */
2358
2359 /**
2360  * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
2361  * @{
2362  */
2363
2364 /** ROM - Register Layout Typedef */
2365 typedef struct {
2366   __I  uint32_t ENTRY[3];                          /**< Entry, array offset: 0x0, array step: 0x4 */
2367   __I  uint32_t TABLEMARK;                         /**< End of Table Marker Register, offset: 0xC */
2368        uint8_t RESERVED_0[4028];
2369   __I  uint32_t SYSACCESS;                         /**< System Access Register, offset: 0xFCC */
2370   __I  uint32_t PERIPHID4;                         /**< Peripheral ID Register, offset: 0xFD0 */
2371   __I  uint32_t PERIPHID5;                         /**< Peripheral ID Register, offset: 0xFD4 */
2372   __I  uint32_t PERIPHID6;                         /**< Peripheral ID Register, offset: 0xFD8 */
2373   __I  uint32_t PERIPHID7;                         /**< Peripheral ID Register, offset: 0xFDC */
2374   __I  uint32_t PERIPHID0;                         /**< Peripheral ID Register, offset: 0xFE0 */
2375   __I  uint32_t PERIPHID1;                         /**< Peripheral ID Register, offset: 0xFE4 */
2376   __I  uint32_t PERIPHID2;                         /**< Peripheral ID Register, offset: 0xFE8 */
2377   __I  uint32_t PERIPHID3;                         /**< Peripheral ID Register, offset: 0xFEC */
2378   __I  uint32_t COMPID[4];                         /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
2379 } ROM_Type;
2380
2381 /* ----------------------------------------------------------------------------
2382    -- ROM Register Masks
2383    ---------------------------------------------------------------------------- */
2384
2385 /**
2386  * @addtogroup ROM_Register_Masks ROM Register Masks
2387  * @{
2388  */
2389
2390 /* ENTRY Bit Fields */
2391 #define ROM_ENTRY_ENTRY_MASK                     0xFFFFFFFFu
2392 #define ROM_ENTRY_ENTRY_SHIFT                    0
2393 #define ROM_ENTRY_ENTRY(x)                       (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
2394 /* TABLEMARK Bit Fields */
2395 #define ROM_TABLEMARK_MARK_MASK                  0xFFFFFFFFu
2396 #define ROM_TABLEMARK_MARK_SHIFT                 0
2397 #define ROM_TABLEMARK_MARK(x)                    (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
2398 /* SYSACCESS Bit Fields */
2399 #define ROM_SYSACCESS_SYSACCESS_MASK             0xFFFFFFFFu
2400 #define ROM_SYSACCESS_SYSACCESS_SHIFT            0
2401 #define ROM_SYSACCESS_SYSACCESS(x)               (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
2402 /* PERIPHID4 Bit Fields */
2403 #define ROM_PERIPHID4_PERIPHID_MASK              0xFFFFFFFFu
2404 #define ROM_PERIPHID4_PERIPHID_SHIFT             0
2405 #define ROM_PERIPHID4_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
2406 /* PERIPHID5 Bit Fields */
2407 #define ROM_PERIPHID5_PERIPHID_MASK              0xFFFFFFFFu
2408 #define ROM_PERIPHID5_PERIPHID_SHIFT             0
2409 #define ROM_PERIPHID5_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
2410 /* PERIPHID6 Bit Fields */
2411 #define ROM_PERIPHID6_PERIPHID_MASK              0xFFFFFFFFu
2412 #define ROM_PERIPHID6_PERIPHID_SHIFT             0
2413 #define ROM_PERIPHID6_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
2414 /* PERIPHID7 Bit Fields */
2415 #define ROM_PERIPHID7_PERIPHID_MASK              0xFFFFFFFFu
2416 #define ROM_PERIPHID7_PERIPHID_SHIFT             0
2417 #define ROM_PERIPHID7_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
2418 /* PERIPHID0 Bit Fields */
2419 #define ROM_PERIPHID0_PERIPHID_MASK              0xFFFFFFFFu
2420 #define ROM_PERIPHID0_PERIPHID_SHIFT             0
2421 #define ROM_PERIPHID0_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
2422 /* PERIPHID1 Bit Fields */
2423 #define ROM_PERIPHID1_PERIPHID_MASK              0xFFFFFFFFu
2424 #define ROM_PERIPHID1_PERIPHID_SHIFT             0
2425 #define ROM_PERIPHID1_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
2426 /* PERIPHID2 Bit Fields */
2427 #define ROM_PERIPHID2_PERIPHID_MASK              0xFFFFFFFFu
2428 #define ROM_PERIPHID2_PERIPHID_SHIFT             0
2429 #define ROM_PERIPHID2_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
2430 /* PERIPHID3 Bit Fields */
2431 #define ROM_PERIPHID3_PERIPHID_MASK              0xFFFFFFFFu
2432 #define ROM_PERIPHID3_PERIPHID_SHIFT             0
2433 #define ROM_PERIPHID3_PERIPHID(x)                (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
2434 /* COMPID Bit Fields */
2435 #define ROM_COMPID_COMPID_MASK                   0xFFFFFFFFu
2436 #define ROM_COMPID_COMPID_SHIFT                  0
2437 #define ROM_COMPID_COMPID(x)                     (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
2438
2439 /**
2440  * @}
2441  */ /* end of group ROM_Register_Masks */
2442
2443
2444 /* ROM - Peripheral instance base addresses */
2445 /** Peripheral ROM base address */
2446 #define ROM_BASE                                 (0xF0002000u)
2447 /** Peripheral ROM base pointer */
2448 #define ROM                                      ((ROM_Type *)ROM_BASE)
2449 /** Array initializer of ROM peripheral base pointers */
2450 #define ROM_BASES                                { ROM }
2451
2452 /**
2453  * @}
2454  */ /* end of group ROM_Peripheral_Access_Layer */
2455
2456
2457 /* ----------------------------------------------------------------------------
2458    -- RTC Peripheral Access Layer
2459    ---------------------------------------------------------------------------- */
2460
2461 /**
2462  * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
2463  * @{
2464  */
2465
2466 /** RTC - Register Layout Typedef */
2467 typedef struct {
2468   __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
2469   __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
2470   __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
2471   __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
2472   __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
2473   __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
2474   __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
2475   __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
2476 } RTC_Type;
2477
2478 /* ----------------------------------------------------------------------------
2479    -- RTC Register Masks
2480    ---------------------------------------------------------------------------- */
2481
2482 /**
2483  * @addtogroup RTC_Register_Masks RTC Register Masks
2484  * @{
2485  */
2486
2487 /* TSR Bit Fields */
2488 #define RTC_TSR_TSR_MASK                         0xFFFFFFFFu
2489 #define RTC_TSR_TSR_SHIFT                        0
2490 #define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
2491 /* TPR Bit Fields */
2492 #define RTC_TPR_TPR_MASK                         0xFFFFu
2493 #define RTC_TPR_TPR_SHIFT                        0
2494 #define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
2495 /* TAR Bit Fields */
2496 #define RTC_TAR_TAR_MASK                         0xFFFFFFFFu
2497 #define RTC_TAR_TAR_SHIFT                        0
2498 #define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
2499 /* TCR Bit Fields */
2500 #define RTC_TCR_TCR_MASK                         0xFFu
2501 #define RTC_TCR_TCR_SHIFT                        0
2502 #define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
2503 #define RTC_TCR_CIR_MASK                         0xFF00u
2504 #define RTC_TCR_CIR_SHIFT                        8
2505 #define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
2506 #define RTC_TCR_TCV_MASK                         0xFF0000u
2507 #define RTC_TCR_TCV_SHIFT                        16
2508 #define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
2509 #define RTC_TCR_CIC_MASK                         0xFF000000u
2510 #define RTC_TCR_CIC_SHIFT                        24
2511 #define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
2512 /* CR Bit Fields */
2513 #define RTC_CR_SWR_MASK                          0x1u
2514 #define RTC_CR_SWR_SHIFT                         0
2515 #define RTC_CR_WPE_MASK                          0x2u
2516 #define RTC_CR_WPE_SHIFT                         1
2517 #define RTC_CR_SUP_MASK                          0x4u
2518 #define RTC_CR_SUP_SHIFT                         2
2519 #define RTC_CR_UM_MASK                           0x8u
2520 #define RTC_CR_UM_SHIFT                          3
2521 #define RTC_CR_OSCE_MASK                         0x100u
2522 #define RTC_CR_OSCE_SHIFT                        8
2523 #define RTC_CR_CLKO_MASK                         0x200u
2524 #define RTC_CR_CLKO_SHIFT                        9
2525 #define RTC_CR_SC16P_MASK                        0x400u
2526 #define RTC_CR_SC16P_SHIFT                       10
2527 #define RTC_CR_SC8P_MASK                         0x800u
2528 #define RTC_CR_SC8P_SHIFT                        11
2529 #define RTC_CR_SC4P_MASK                         0x1000u
2530 #define RTC_CR_SC4P_SHIFT                        12
2531 #define RTC_CR_SC2P_MASK                         0x2000u
2532 #define RTC_CR_SC2P_SHIFT                        13
2533 /* SR Bit Fields */
2534 #define RTC_SR_TIF_MASK                          0x1u
2535 #define RTC_SR_TIF_SHIFT                         0
2536 #define RTC_SR_TOF_MASK                          0x2u
2537 #define RTC_SR_TOF_SHIFT                         1
2538 #define RTC_SR_TAF_MASK                          0x4u
2539 #define RTC_SR_TAF_SHIFT                         2
2540 #define RTC_SR_TCE_MASK                          0x10u
2541 #define RTC_SR_TCE_SHIFT                         4
2542 /* LR Bit Fields */
2543 #define RTC_LR_TCL_MASK                          0x8u
2544 #define RTC_LR_TCL_SHIFT                         3
2545 #define RTC_LR_CRL_MASK                          0x10u
2546 #define RTC_LR_CRL_SHIFT                         4
2547 #define RTC_LR_SRL_MASK                          0x20u
2548 #define RTC_LR_SRL_SHIFT                         5
2549 #define RTC_LR_LRL_MASK                          0x40u
2550 #define RTC_LR_LRL_SHIFT                         6
2551 /* IER Bit Fields */
2552 #define RTC_IER_TIIE_MASK                        0x1u
2553 #define RTC_IER_TIIE_SHIFT                       0
2554 #define RTC_IER_TOIE_MASK                        0x2u
2555 #define RTC_IER_TOIE_SHIFT                       1
2556 #define RTC_IER_TAIE_MASK                        0x4u
2557 #define RTC_IER_TAIE_SHIFT                       2
2558 #define RTC_IER_TSIE_MASK                        0x10u
2559 #define RTC_IER_TSIE_SHIFT                       4
2560 #define RTC_IER_WPON_MASK                        0x80u
2561 #define RTC_IER_WPON_SHIFT                       7
2562
2563 /**
2564  * @}
2565  */ /* end of group RTC_Register_Masks */
2566
2567
2568 /* RTC - Peripheral instance base addresses */
2569 /** Peripheral RTC base address */
2570 #define RTC_BASE                                 (0x4003D000u)
2571 /** Peripheral RTC base pointer */
2572 #define RTC                                      ((RTC_Type *)RTC_BASE)
2573 /** Array initializer of RTC peripheral base pointers */
2574 #define RTC_BASES                                { RTC }
2575
2576 /**
2577  * @}
2578  */ /* end of group RTC_Peripheral_Access_Layer */
2579
2580
2581 /* ----------------------------------------------------------------------------
2582    -- SIM Peripheral Access Layer
2583    ---------------------------------------------------------------------------- */
2584
2585 /**
2586  * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
2587  * @{
2588  */
2589
2590 /** SIM - Register Layout Typedef */
2591 typedef struct {
2592   __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
2593   __I  uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
2594        uint8_t RESERVED_0[4092];
2595   __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
2596        uint8_t RESERVED_1[4];
2597   __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
2598   __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
2599        uint8_t RESERVED_2[4];
2600   __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
2601        uint8_t RESERVED_3[8];
2602   __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
2603        uint8_t RESERVED_4[12];
2604   __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
2605   __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
2606   __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
2607   __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
2608   __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
2609        uint8_t RESERVED_5[4];
2610   __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
2611   __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
2612        uint8_t RESERVED_6[4];
2613   __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
2614   __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
2615   __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
2616        uint8_t RESERVED_7[156];
2617   __IO uint32_t COPC;                              /**< COP Control Register, offset: 0x1100 */
2618   __O  uint32_t SRVCOP;                            /**< Service COP Register, offset: 0x1104 */
2619 } SIM_Type;
2620
2621 /* ----------------------------------------------------------------------------
2622    -- SIM Register Masks
2623    ---------------------------------------------------------------------------- */
2624
2625 /**
2626  * @addtogroup SIM_Register_Masks SIM Register Masks
2627  * @{
2628  */
2629
2630 /* SOPT1 Bit Fields */
2631 #define SIM_SOPT1_OSC32KSEL_MASK                 0xC0000u
2632 #define SIM_SOPT1_OSC32KSEL_SHIFT                18
2633 #define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
2634 /* SOPT2 Bit Fields */
2635 #define SIM_SOPT2_RTCCLKOUTSEL_MASK              0x10u
2636 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             4
2637 #define SIM_SOPT2_CLKOUTSEL_MASK                 0xE0u
2638 #define SIM_SOPT2_CLKOUTSEL_SHIFT                5
2639 #define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
2640 #define SIM_SOPT2_TPMSRC_MASK                    0x3000000u
2641 #define SIM_SOPT2_TPMSRC_SHIFT                   24
2642 #define SIM_SOPT2_TPMSRC(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
2643 #define SIM_SOPT2_UART0SRC_MASK                  0xC000000u
2644 #define SIM_SOPT2_UART0SRC_SHIFT                 26
2645 #define SIM_SOPT2_UART0SRC(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
2646 /* SOPT4 Bit Fields */
2647 #define SIM_SOPT4_TPM1CH0SRC_MASK                0x40000u
2648 #define SIM_SOPT4_TPM1CH0SRC_SHIFT               18
2649 #define SIM_SOPT4_TPM0CLKSEL_MASK                0x1000000u
2650 #define SIM_SOPT4_TPM0CLKSEL_SHIFT               24
2651 #define SIM_SOPT4_TPM1CLKSEL_MASK                0x2000000u
2652 #define SIM_SOPT4_TPM1CLKSEL_SHIFT               25
2653 /* SOPT5 Bit Fields */
2654 #define SIM_SOPT5_UART0TXSRC_MASK                0x1u
2655 #define SIM_SOPT5_UART0TXSRC_SHIFT               0
2656 #define SIM_SOPT5_UART0RXSRC_MASK                0x4u
2657 #define SIM_SOPT5_UART0RXSRC_SHIFT               2
2658 #define SIM_SOPT5_UART0ODE_MASK                  0x10000u
2659 #define SIM_SOPT5_UART0ODE_SHIFT                 16
2660 /* SOPT7 Bit Fields */
2661 #define SIM_SOPT7_ADC0TRGSEL_MASK                0xFu
2662 #define SIM_SOPT7_ADC0TRGSEL_SHIFT               0
2663 #define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
2664 #define SIM_SOPT7_ADC0PRETRGSEL_MASK             0x10u
2665 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            4
2666 #define SIM_SOPT7_ADC0ALTTRGEN_MASK              0x80u
2667 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             7
2668 /* SDID Bit Fields */
2669 #define SIM_SDID_PINID_MASK                      0xFu
2670 #define SIM_SDID_PINID_SHIFT                     0
2671 #define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
2672 #define SIM_SDID_DIEID_MASK                      0xF80u
2673 #define SIM_SDID_DIEID_SHIFT                     7
2674 #define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
2675 #define SIM_SDID_REVID_MASK                      0xF000u
2676 #define SIM_SDID_REVID_SHIFT                     12
2677 #define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
2678 #define SIM_SDID_SRAMSIZE_MASK                   0xF0000u
2679 #define SIM_SDID_SRAMSIZE_SHIFT                  16
2680 #define SIM_SDID_SRAMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
2681 #define SIM_SDID_SERIESID_MASK                   0xF00000u
2682 #define SIM_SDID_SERIESID_SHIFT                  20
2683 #define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
2684 #define SIM_SDID_SUBFAMID_MASK                   0xF000000u
2685 #define SIM_SDID_SUBFAMID_SHIFT                  24
2686 #define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
2687 #define SIM_SDID_FAMID_MASK                      0xF0000000u
2688 #define SIM_SDID_FAMID_SHIFT                     28
2689 #define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
2690 /* SCGC4 Bit Fields */
2691 #define SIM_SCGC4_I2C0_MASK                      0x40u
2692 #define SIM_SCGC4_I2C0_SHIFT                     6
2693 #define SIM_SCGC4_UART0_MASK                     0x400u
2694 #define SIM_SCGC4_UART0_SHIFT                    10
2695 #define SIM_SCGC4_CMP_MASK                       0x80000u
2696 #define SIM_SCGC4_CMP_SHIFT                      19
2697 #define SIM_SCGC4_SPI0_MASK                      0x400000u
2698 #define SIM_SCGC4_SPI0_SHIFT                     22
2699 /* SCGC5 Bit Fields */
2700 #define SIM_SCGC5_LPTMR_MASK                     0x1u
2701 #define SIM_SCGC5_LPTMR_SHIFT                    0
2702 #define SIM_SCGC5_TSI_MASK                       0x20u
2703 #define SIM_SCGC5_TSI_SHIFT                      5
2704 #define SIM_SCGC5_PORTA_MASK                     0x200u
2705 #define SIM_SCGC5_PORTA_SHIFT                    9
2706 #define SIM_SCGC5_PORTB_MASK                     0x400u
2707 #define SIM_SCGC5_PORTB_SHIFT                    10
2708 /* SCGC6 Bit Fields */
2709 #define SIM_SCGC6_FTF_MASK                       0x1u
2710 #define SIM_SCGC6_FTF_SHIFT                      0
2711 #define SIM_SCGC6_DMAMUX_MASK                    0x2u
2712 #define SIM_SCGC6_DMAMUX_SHIFT                   1
2713 #define SIM_SCGC6_PIT_MASK                       0x800000u
2714 #define SIM_SCGC6_PIT_SHIFT                      23
2715 #define SIM_SCGC6_TPM0_MASK                      0x1000000u
2716 #define SIM_SCGC6_TPM0_SHIFT                     24
2717 #define SIM_SCGC6_TPM1_MASK                      0x2000000u
2718 #define SIM_SCGC6_TPM1_SHIFT                     25
2719 #define SIM_SCGC6_ADC0_MASK                      0x8000000u
2720 #define SIM_SCGC6_ADC0_SHIFT                     27
2721 #define SIM_SCGC6_RTC_MASK                       0x20000000u
2722 #define SIM_SCGC6_RTC_SHIFT                      29
2723 #define SIM_SCGC6_DAC0_MASK                      0x80000000u
2724 #define SIM_SCGC6_DAC0_SHIFT                     31
2725 /* SCGC7 Bit Fields */
2726 #define SIM_SCGC7_DMA_MASK                       0x100u
2727 #define SIM_SCGC7_DMA_SHIFT                      8
2728 /* CLKDIV1 Bit Fields */
2729 #define SIM_CLKDIV1_OUTDIV4_MASK                 0x70000u
2730 #define SIM_CLKDIV1_OUTDIV4_SHIFT                16
2731 #define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
2732 #define SIM_CLKDIV1_OUTDIV1_MASK                 0xF0000000u
2733 #define SIM_CLKDIV1_OUTDIV1_SHIFT                28
2734 #define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
2735 /* FCFG1 Bit Fields */
2736 #define SIM_FCFG1_FLASHDIS_MASK                  0x1u
2737 #define SIM_FCFG1_FLASHDIS_SHIFT                 0
2738 #define SIM_FCFG1_FLASHDOZE_MASK                 0x2u
2739 #define SIM_FCFG1_FLASHDOZE_SHIFT                1
2740 #define SIM_FCFG1_PFSIZE_MASK                    0xF000000u
2741 #define SIM_FCFG1_PFSIZE_SHIFT                   24
2742 #define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
2743 /* FCFG2 Bit Fields */
2744 #define SIM_FCFG2_MAXADDR0_MASK                  0x7F000000u
2745 #define SIM_FCFG2_MAXADDR0_SHIFT                 24
2746 #define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
2747 /* UIDMH Bit Fields */
2748 #define SIM_UIDMH_UID_MASK                       0xFFFFu
2749 #define SIM_UIDMH_UID_SHIFT                      0
2750 #define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
2751 /* UIDML Bit Fields */
2752 #define SIM_UIDML_UID_MASK                       0xFFFFFFFFu
2753 #define SIM_UIDML_UID_SHIFT                      0
2754 #define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
2755 /* UIDL Bit Fields */
2756 #define SIM_UIDL_UID_MASK                        0xFFFFFFFFu
2757 #define SIM_UIDL_UID_SHIFT                       0
2758 #define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
2759 /* COPC Bit Fields */
2760 #define SIM_COPC_COPW_MASK                       0x1u
2761 #define SIM_COPC_COPW_SHIFT                      0
2762 #define SIM_COPC_COPCLKS_MASK                    0x2u
2763 #define SIM_COPC_COPCLKS_SHIFT                   1
2764 #define SIM_COPC_COPT_MASK                       0xCu
2765 #define SIM_COPC_COPT_SHIFT                      2
2766 #define SIM_COPC_COPT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
2767 /* SRVCOP Bit Fields */
2768 #define SIM_SRVCOP_SRVCOP_MASK                   0xFFu
2769 #define SIM_SRVCOP_SRVCOP_SHIFT                  0
2770 #define SIM_SRVCOP_SRVCOP(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
2771
2772 /**
2773  * @}
2774  */ /* end of group SIM_Register_Masks */
2775
2776
2777 /* SIM - Peripheral instance base addresses */
2778 /** Peripheral SIM base address */
2779 #define SIM_BASE                                 (0x40047000u)
2780 /** Peripheral SIM base pointer */
2781 #define SIM                                      ((SIM_Type *)SIM_BASE)
2782 /** Array initializer of SIM peripheral base pointers */
2783 #define SIM_BASES                                { SIM }
2784
2785 /**
2786  * @}
2787  */ /* end of group SIM_Peripheral_Access_Layer */
2788
2789
2790 /* ----------------------------------------------------------------------------
2791    -- SMC Peripheral Access Layer
2792    ---------------------------------------------------------------------------- */
2793
2794 /**
2795  * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
2796  * @{
2797  */
2798
2799 /** SMC - Register Layout Typedef */
2800 typedef struct {
2801   __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
2802   __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
2803   __IO uint8_t STOPCTRL;                           /**< Stop Control Register, offset: 0x2 */
2804   __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
2805 } SMC_Type;
2806
2807 /* ----------------------------------------------------------------------------
2808    -- SMC Register Masks
2809    ---------------------------------------------------------------------------- */
2810
2811 /**
2812  * @addtogroup SMC_Register_Masks SMC Register Masks
2813  * @{
2814  */
2815
2816 /* PMPROT Bit Fields */
2817 #define SMC_PMPROT_AVLLS_MASK                    0x2u
2818 #define SMC_PMPROT_AVLLS_SHIFT                   1
2819 #define SMC_PMPROT_ALLS_MASK                     0x8u
2820 #define SMC_PMPROT_ALLS_SHIFT                    3
2821 #define SMC_PMPROT_AVLP_MASK                     0x20u
2822 #define SMC_PMPROT_AVLP_SHIFT                    5
2823 /* PMCTRL Bit Fields */
2824 #define SMC_PMCTRL_STOPM_MASK                    0x7u
2825 #define SMC_PMCTRL_STOPM_SHIFT                   0
2826 #define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
2827 #define SMC_PMCTRL_STOPA_MASK                    0x8u
2828 #define SMC_PMCTRL_STOPA_SHIFT                   3
2829 #define SMC_PMCTRL_RUNM_MASK                     0x60u
2830 #define SMC_PMCTRL_RUNM_SHIFT                    5
2831 #define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
2832 /* STOPCTRL Bit Fields */
2833 #define SMC_STOPCTRL_VLLSM_MASK                  0x7u
2834 #define SMC_STOPCTRL_VLLSM_SHIFT                 0
2835 #define SMC_STOPCTRL_VLLSM(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
2836 #define SMC_STOPCTRL_PORPO_MASK                  0x20u
2837 #define SMC_STOPCTRL_PORPO_SHIFT                 5
2838 #define SMC_STOPCTRL_PSTOPO_MASK                 0xC0u
2839 #define SMC_STOPCTRL_PSTOPO_SHIFT                6
2840 #define SMC_STOPCTRL_PSTOPO(x)                   (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
2841 /* PMSTAT Bit Fields */
2842 #define SMC_PMSTAT_PMSTAT_MASK                   0x7Fu
2843 #define SMC_PMSTAT_PMSTAT_SHIFT                  0
2844 #define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
2845
2846 /**
2847  * @}
2848  */ /* end of group SMC_Register_Masks */
2849
2850
2851 /* SMC - Peripheral instance base addresses */
2852 /** Peripheral SMC base address */
2853 #define SMC_BASE                                 (0x4007E000u)
2854 /** Peripheral SMC base pointer */
2855 #define SMC                                      ((SMC_Type *)SMC_BASE)
2856 /** Array initializer of SMC peripheral base pointers */
2857 #define SMC_BASES                                { SMC }
2858
2859 /**
2860  * @}
2861  */ /* end of group SMC_Peripheral_Access_Layer */
2862
2863
2864 /* ----------------------------------------------------------------------------
2865    -- SPI Peripheral Access Layer
2866    ---------------------------------------------------------------------------- */
2867
2868 /**
2869  * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
2870  * @{
2871  */
2872
2873 /** SPI - Register Layout Typedef */
2874 typedef struct {
2875   __IO uint8_t C1;                                 /**< SPI control register 1, offset: 0x0 */
2876   __IO uint8_t C2;                                 /**< SPI control register 2, offset: 0x1 */
2877   __IO uint8_t BR;                                 /**< SPI baud rate register, offset: 0x2 */
2878   __I  uint8_t S;                                  /**< SPI status register, offset: 0x3 */
2879        uint8_t RESERVED_0[1];
2880   __IO uint8_t D;                                  /**< SPI data register, offset: 0x5 */
2881        uint8_t RESERVED_1[1];
2882   __IO uint8_t M;                                  /**< SPI match register, offset: 0x7 */
2883 } SPI_Type;
2884
2885 /* ----------------------------------------------------------------------------
2886    -- SPI Register Masks
2887    ---------------------------------------------------------------------------- */
2888
2889 /**
2890  * @addtogroup SPI_Register_Masks SPI Register Masks
2891  * @{
2892  */
2893
2894 /* C1 Bit Fields */
2895 #define SPI_C1_LSBFE_MASK                        0x1u
2896 #define SPI_C1_LSBFE_SHIFT                       0
2897 #define SPI_C1_SSOE_MASK                         0x2u
2898 #define SPI_C1_SSOE_SHIFT                        1
2899 #define SPI_C1_CPHA_MASK                         0x4u
2900 #define SPI_C1_CPHA_SHIFT                        2
2901 #define SPI_C1_CPOL_MASK                         0x8u
2902 #define SPI_C1_CPOL_SHIFT                        3
2903 #define SPI_C1_MSTR_MASK                         0x10u
2904 #define SPI_C1_MSTR_SHIFT                        4
2905 #define SPI_C1_SPTIE_MASK                        0x20u
2906 #define SPI_C1_SPTIE_SHIFT                       5
2907 #define SPI_C1_SPE_MASK                          0x40u
2908 #define SPI_C1_SPE_SHIFT                         6
2909 #define SPI_C1_SPIE_MASK                         0x80u
2910 #define SPI_C1_SPIE_SHIFT                        7
2911 /* C2 Bit Fields */
2912 #define SPI_C2_SPC0_MASK                         0x1u
2913 #define SPI_C2_SPC0_SHIFT                        0
2914 #define SPI_C2_SPISWAI_MASK                      0x2u
2915 #define SPI_C2_SPISWAI_SHIFT                     1
2916 #define SPI_C2_RXDMAE_MASK                       0x4u
2917 #define SPI_C2_RXDMAE_SHIFT                      2
2918 #define SPI_C2_BIDIROE_MASK                      0x8u
2919 #define SPI_C2_BIDIROE_SHIFT                     3
2920 #define SPI_C2_MODFEN_MASK                       0x10u
2921 #define SPI_C2_MODFEN_SHIFT                      4
2922 #define SPI_C2_TXDMAE_MASK                       0x20u
2923 #define SPI_C2_TXDMAE_SHIFT                      5
2924 #define SPI_C2_SPMIE_MASK                        0x80u
2925 #define SPI_C2_SPMIE_SHIFT                       7
2926 /* BR Bit Fields */
2927 #define SPI_BR_SPR_MASK                          0xFu
2928 #define SPI_BR_SPR_SHIFT                         0
2929 #define SPI_BR_SPR(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
2930 #define SPI_BR_SPPR_MASK                         0x70u
2931 #define SPI_BR_SPPR_SHIFT                        4
2932 #define SPI_BR_SPPR(x)                           (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
2933 /* S Bit Fields */
2934 #define SPI_S_MODF_MASK                          0x10u
2935 #define SPI_S_MODF_SHIFT                         4
2936 #define SPI_S_SPTEF_MASK                         0x20u
2937 #define SPI_S_SPTEF_SHIFT                        5
2938 #define SPI_S_SPMF_MASK                          0x40u
2939 #define SPI_S_SPMF_SHIFT                         6
2940 #define SPI_S_SPRF_MASK                          0x80u
2941 #define SPI_S_SPRF_SHIFT                         7
2942 /* D Bit Fields */
2943 #define SPI_D_Bits_MASK                          0xFFu
2944 #define SPI_D_Bits_SHIFT                         0
2945 #define SPI_D_Bits(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
2946 /* M Bit Fields */
2947 #define SPI_M_Bits_MASK                          0xFFu
2948 #define SPI_M_Bits_SHIFT                         0
2949 #define SPI_M_Bits(x)                            (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
2950
2951 /**
2952  * @}
2953  */ /* end of group SPI_Register_Masks */
2954
2955
2956 /* SPI - Peripheral instance base addresses */
2957 /** Peripheral SPI0 base address */
2958 #define SPI0_BASE                                (0x40076000u)
2959 /** Peripheral SPI0 base pointer */
2960 #define SPI0                                     ((SPI_Type *)SPI0_BASE)
2961 /** Array initializer of SPI peripheral base pointers */
2962 #define SPI_BASES                                { SPI0 }
2963
2964 /**
2965  * @}
2966  */ /* end of group SPI_Peripheral_Access_Layer */
2967
2968
2969 /* ----------------------------------------------------------------------------
2970    -- TPM Peripheral Access Layer
2971    ---------------------------------------------------------------------------- */
2972
2973 /**
2974  * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
2975  * @{
2976  */
2977
2978 /** TPM - Register Layout Typedef */
2979 typedef struct {
2980   __IO uint32_t SC;                                /**< Status and Control, offset: 0x0 */
2981   __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
2982   __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
2983   struct {                                         /* offset: 0xC, array step: 0x8 */
2984     __IO uint32_t CnSC;                              /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
2985     __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
2986   } CONTROLS[6];
2987        uint8_t RESERVED_0[20];
2988   __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x50 */
2989        uint8_t RESERVED_1[48];
2990   __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
2991 } TPM_Type;
2992
2993 /* ----------------------------------------------------------------------------
2994    -- TPM Register Masks
2995    ---------------------------------------------------------------------------- */
2996
2997 /**
2998  * @addtogroup TPM_Register_Masks TPM Register Masks
2999  * @{
3000  */
3001
3002 /* SC Bit Fields */
3003 #define TPM_SC_PS_MASK                           0x7u
3004 #define TPM_SC_PS_SHIFT                          0
3005 #define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
3006 #define TPM_SC_CMOD_MASK                         0x18u
3007 #define TPM_SC_CMOD_SHIFT                        3
3008 #define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
3009 #define TPM_SC_CPWMS_MASK                        0x20u
3010 #define TPM_SC_CPWMS_SHIFT                       5
3011 #define TPM_SC_TOIE_MASK                         0x40u
3012 #define TPM_SC_TOIE_SHIFT                        6
3013 #define TPM_SC_TOF_MASK                          0x80u
3014 #define TPM_SC_TOF_SHIFT                         7
3015 #define TPM_SC_DMA_MASK                          0x100u
3016 #define TPM_SC_DMA_SHIFT                         8
3017 /* CNT Bit Fields */
3018 #define TPM_CNT_COUNT_MASK                       0xFFFFu
3019 #define TPM_CNT_COUNT_SHIFT                      0
3020 #define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
3021 /* MOD Bit Fields */
3022 #define TPM_MOD_MOD_MASK                         0xFFFFu
3023 #define TPM_MOD_MOD_SHIFT                        0
3024 #define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
3025 /* CnSC Bit Fields */
3026 #define TPM_CnSC_DMA_MASK                        0x1u
3027 #define TPM_CnSC_DMA_SHIFT                       0
3028 #define TPM_CnSC_ELSA_MASK                       0x4u
3029 #define TPM_CnSC_ELSA_SHIFT                      2
3030 #define TPM_CnSC_ELSB_MASK                       0x8u
3031 #define TPM_CnSC_ELSB_SHIFT                      3
3032 #define TPM_CnSC_MSA_MASK                        0x10u
3033 #define TPM_CnSC_MSA_SHIFT                       4
3034 #define TPM_CnSC_MSB_MASK                        0x20u
3035 #define TPM_CnSC_MSB_SHIFT                       5
3036 #define TPM_CnSC_CHIE_MASK                       0x40u
3037 #define TPM_CnSC_CHIE_SHIFT                      6
3038 #define TPM_CnSC_CHF_MASK                        0x80u
3039 #define TPM_CnSC_CHF_SHIFT                       7
3040 /* CnV Bit Fields */
3041 #define TPM_CnV_VAL_MASK                         0xFFFFu
3042 #define TPM_CnV_VAL_SHIFT                        0
3043 #define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
3044 /* STATUS Bit Fields */
3045 #define TPM_STATUS_CH0F_MASK                     0x1u
3046 #define TPM_STATUS_CH0F_SHIFT                    0
3047 #define TPM_STATUS_CH1F_MASK                     0x2u
3048 #define TPM_STATUS_CH1F_SHIFT                    1
3049 #define TPM_STATUS_CH2F_MASK                     0x4u
3050 #define TPM_STATUS_CH2F_SHIFT                    2
3051 #define TPM_STATUS_CH3F_MASK                     0x8u
3052 #define TPM_STATUS_CH3F_SHIFT                    3
3053 #define TPM_STATUS_CH4F_MASK                     0x10u
3054 #define TPM_STATUS_CH4F_SHIFT                    4
3055 #define TPM_STATUS_CH5F_MASK                     0x20u
3056 #define TPM_STATUS_CH5F_SHIFT                    5
3057 #define TPM_STATUS_TOF_MASK                      0x100u
3058 #define TPM_STATUS_TOF_SHIFT                     8
3059 /* CONF Bit Fields */
3060 #define TPM_CONF_DOZEEN_MASK                     0x20u
3061 #define TPM_CONF_DOZEEN_SHIFT                    5
3062 #define TPM_CONF_DBGMODE_MASK                    0xC0u
3063 #define TPM_CONF_DBGMODE_SHIFT                   6
3064 #define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
3065 #define TPM_CONF_GTBEEN_MASK                     0x200u
3066 #define TPM_CONF_GTBEEN_SHIFT                    9
3067 #define TPM_CONF_CSOT_MASK                       0x10000u
3068 #define TPM_CONF_CSOT_SHIFT                      16
3069 #define TPM_CONF_CSOO_MASK                       0x20000u
3070 #define TPM_CONF_CSOO_SHIFT                      17
3071 #define TPM_CONF_CROT_MASK                       0x40000u
3072 #define TPM_CONF_CROT_SHIFT                      18
3073 #define TPM_CONF_TRGSEL_MASK                     0xF000000u
3074 #define TPM_CONF_TRGSEL_SHIFT                    24
3075 #define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
3076
3077 /**
3078  * @}
3079  */ /* end of group TPM_Register_Masks */
3080
3081
3082 /* TPM - Peripheral instance base addresses */
3083 /** Peripheral TPM0 base address */
3084 #define TPM0_BASE                                (0x40038000u)
3085 /** Peripheral TPM0 base pointer */
3086 #define TPM0                                     ((TPM_Type *)TPM0_BASE)
3087 /** Peripheral TPM1 base address */
3088 #define TPM1_BASE                                (0x40039000u)
3089 /** Peripheral TPM1 base pointer */
3090 #define TPM1                                     ((TPM_Type *)TPM1_BASE)
3091 /** Array initializer of TPM peripheral base pointers */
3092 #define TPM_BASES                                { TPM0, TPM1 }
3093
3094 /**
3095  * @}
3096  */ /* end of group TPM_Peripheral_Access_Layer */
3097
3098
3099 /* ----------------------------------------------------------------------------
3100    -- TSI Peripheral Access Layer
3101    ---------------------------------------------------------------------------- */
3102
3103 /**
3104  * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
3105  * @{
3106  */
3107
3108 /** TSI - Register Layout Typedef */
3109 typedef struct {
3110   __IO uint32_t GENCS;                             /**< TSI General Control and Status Register, offset: 0x0 */
3111   __IO uint32_t DATA;                              /**< TSI DATA Register, offset: 0x4 */
3112   __IO uint32_t TSHD;                              /**< TSI Threshold Register, offset: 0x8 */
3113 } TSI_Type;
3114
3115 /* ----------------------------------------------------------------------------
3116    -- TSI Register Masks
3117    ---------------------------------------------------------------------------- */
3118
3119 /**
3120  * @addtogroup TSI_Register_Masks TSI Register Masks
3121  * @{
3122  */
3123
3124 /* GENCS Bit Fields */
3125 #define TSI_GENCS_CURSW_MASK                     0x2u
3126 #define TSI_GENCS_CURSW_SHIFT                    1
3127 #define TSI_GENCS_EOSF_MASK                      0x4u
3128 #define TSI_GENCS_EOSF_SHIFT                     2
3129 #define TSI_GENCS_SCNIP_MASK                     0x8u
3130 #define TSI_GENCS_SCNIP_SHIFT                    3
3131 #define TSI_GENCS_STM_MASK                       0x10u
3132 #define TSI_GENCS_STM_SHIFT                      4
3133 #define TSI_GENCS_STPE_MASK                      0x20u
3134 #define TSI_GENCS_STPE_SHIFT                     5
3135 #define TSI_GENCS_TSIIEN_MASK                    0x40u
3136 #define TSI_GENCS_TSIIEN_SHIFT                   6
3137 #define TSI_GENCS_TSIEN_MASK                     0x80u
3138 #define TSI_GENCS_TSIEN_SHIFT                    7
3139 #define TSI_GENCS_NSCN_MASK                      0x1F00u
3140 #define TSI_GENCS_NSCN_SHIFT                     8
3141 #define TSI_GENCS_NSCN(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
3142 #define TSI_GENCS_PS_MASK                        0xE000u
3143 #define TSI_GENCS_PS_SHIFT                       13
3144 #define TSI_GENCS_PS(x)                          (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
3145 #define TSI_GENCS_EXTCHRG_MASK                   0x70000u
3146 #define TSI_GENCS_EXTCHRG_SHIFT                  16
3147 #define TSI_GENCS_EXTCHRG(x)                     (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
3148 #define TSI_GENCS_DVOLT_MASK                     0x180000u
3149 #define TSI_GENCS_DVOLT_SHIFT                    19
3150 #define TSI_GENCS_DVOLT(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
3151 #define TSI_GENCS_REFCHRG_MASK                   0xE00000u
3152 #define TSI_GENCS_REFCHRG_SHIFT                  21
3153 #define TSI_GENCS_REFCHRG(x)                     (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
3154 #define TSI_GENCS_MODE_MASK                      0xF000000u
3155 #define TSI_GENCS_MODE_SHIFT                     24
3156 #define TSI_GENCS_MODE(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
3157 #define TSI_GENCS_ESOR_MASK                      0x10000000u
3158 #define TSI_GENCS_ESOR_SHIFT                     28
3159 #define TSI_GENCS_OUTRGF_MASK                    0x80000000u
3160 #define TSI_GENCS_OUTRGF_SHIFT                   31
3161 /* DATA Bit Fields */
3162 #define TSI_DATA_TSICNT_MASK                     0xFFFFu
3163 #define TSI_DATA_TSICNT_SHIFT                    0
3164 #define TSI_DATA_TSICNT(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
3165 #define TSI_DATA_SWTS_MASK                       0x400000u
3166 #define TSI_DATA_SWTS_SHIFT                      22
3167 #define TSI_DATA_DMAEN_MASK                      0x800000u
3168 #define TSI_DATA_DMAEN_SHIFT                     23
3169 #define TSI_DATA_TSICH_MASK                      0xF0000000u
3170 #define TSI_DATA_TSICH_SHIFT                     28
3171 #define TSI_DATA_TSICH(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
3172 /* TSHD Bit Fields */
3173 #define TSI_TSHD_THRESL_MASK                     0xFFFFu
3174 #define TSI_TSHD_THRESL_SHIFT                    0
3175 #define TSI_TSHD_THRESL(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
3176 #define TSI_TSHD_THRESH_MASK                     0xFFFF0000u
3177 #define TSI_TSHD_THRESH_SHIFT                    16
3178 #define TSI_TSHD_THRESH(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
3179
3180 /**
3181  * @}
3182  */ /* end of group TSI_Register_Masks */
3183
3184
3185 /* TSI - Peripheral instance base addresses */
3186 /** Peripheral TSI0 base address */
3187 #define TSI0_BASE                                (0x40045000u)
3188 /** Peripheral TSI0 base pointer */
3189 #define TSI0                                     ((TSI_Type *)TSI0_BASE)
3190 /** Array initializer of TSI peripheral base pointers */
3191 #define TSI_BASES                                { TSI0 }
3192
3193 /**
3194  * @}
3195  */ /* end of group TSI_Peripheral_Access_Layer */
3196
3197
3198 /* ----------------------------------------------------------------------------
3199    -- UART0 Peripheral Access Layer
3200    ---------------------------------------------------------------------------- */
3201
3202 /**
3203  * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
3204  * @{
3205  */
3206
3207 /** UART0 - Register Layout Typedef */
3208 typedef struct {
3209   __IO uint8_t BDH;                                /**< UART Baud Rate Register High, offset: 0x0 */
3210   __IO uint8_t BDL;                                /**< UART Baud Rate Register Low, offset: 0x1 */
3211   __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
3212   __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
3213   __IO uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
3214   __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
3215   __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
3216   __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
3217   __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
3218   __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
3219   __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
3220   __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
3221 } UART0_Type;
3222
3223 /* ----------------------------------------------------------------------------
3224    -- UART0 Register Masks
3225    ---------------------------------------------------------------------------- */
3226
3227 /**
3228  * @addtogroup UART0_Register_Masks UART0 Register Masks
3229  * @{
3230  */
3231
3232 /* BDH Bit Fields */
3233 #define UART0_BDH_SBR_MASK                       0x1Fu
3234 #define UART0_BDH_SBR_SHIFT                      0
3235 #define UART0_BDH_SBR(x)                         (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
3236 #define UART0_BDH_SBNS_MASK                      0x20u
3237 #define UART0_BDH_SBNS_SHIFT                     5
3238 #define UART0_BDH_RXEDGIE_MASK                   0x40u
3239 #define UART0_BDH_RXEDGIE_SHIFT                  6
3240 #define UART0_BDH_LBKDIE_MASK                    0x80u
3241 #define UART0_BDH_LBKDIE_SHIFT                   7
3242 /* BDL Bit Fields */
3243 #define UART0_BDL_SBR_MASK                       0xFFu
3244 #define UART0_BDL_SBR_SHIFT                      0
3245 #define UART0_BDL_SBR(x)                         (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
3246 /* C1 Bit Fields */
3247 #define UART0_C1_PT_MASK                         0x1u
3248 #define UART0_C1_PT_SHIFT                        0
3249 #define UART0_C1_PE_MASK                         0x2u
3250 #define UART0_C1_PE_SHIFT                        1
3251 #define UART0_C1_ILT_MASK                        0x4u
3252 #define UART0_C1_ILT_SHIFT                       2
3253 #define UART0_C1_WAKE_MASK                       0x8u
3254 #define UART0_C1_WAKE_SHIFT                      3
3255 #define UART0_C1_M_MASK                          0x10u
3256 #define UART0_C1_M_SHIFT                         4
3257 #define UART0_C1_RSRC_MASK                       0x20u
3258 #define UART0_C1_RSRC_SHIFT                      5
3259 #define UART0_C1_DOZEEN_MASK                     0x40u
3260 #define UART0_C1_DOZEEN_SHIFT                    6
3261 #define UART0_C1_LOOPS_MASK                      0x80u
3262 #define UART0_C1_LOOPS_SHIFT                     7
3263 /* C2 Bit Fields */
3264 #define UART0_C2_SBK_MASK                        0x1u
3265 #define UART0_C2_SBK_SHIFT                       0
3266 #define UART0_C2_RWU_MASK                        0x2u
3267 #define UART0_C2_RWU_SHIFT                       1
3268 #define UART0_C2_RE_MASK                         0x4u
3269 #define UART0_C2_RE_SHIFT                        2
3270 #define UART0_C2_TE_MASK                         0x8u
3271 #define UART0_C2_TE_SHIFT                        3
3272 #define UART0_C2_ILIE_MASK                       0x10u
3273 #define UART0_C2_ILIE_SHIFT                      4
3274 #define UART0_C2_RIE_MASK                        0x20u
3275 #define UART0_C2_RIE_SHIFT                       5
3276 #define UART0_C2_TCIE_MASK                       0x40u
3277 #define UART0_C2_TCIE_SHIFT                      6
3278 #define UART0_C2_TIE_MASK                        0x80u
3279 #define UART0_C2_TIE_SHIFT                       7
3280 /* S1 Bit Fields */
3281 #define UART0_S1_PF_MASK                         0x1u
3282 #define UART0_S1_PF_SHIFT                        0
3283 #define UART0_S1_FE_MASK                         0x2u
3284 #define UART0_S1_FE_SHIFT                        1
3285 #define UART0_S1_NF_MASK                         0x4u
3286 #define UART0_S1_NF_SHIFT                        2
3287 #define UART0_S1_OR_MASK                         0x8u
3288 #define UART0_S1_OR_SHIFT                        3
3289 #define UART0_S1_IDLE_MASK                       0x10u
3290 #define UART0_S1_IDLE_SHIFT                      4
3291 #define UART0_S1_RDRF_MASK                       0x20u
3292 #define UART0_S1_RDRF_SHIFT                      5
3293 #define UART0_S1_TC_MASK                         0x40u
3294 #define UART0_S1_TC_SHIFT                        6
3295 #define UART0_S1_TDRE_MASK                       0x80u
3296 #define UART0_S1_TDRE_SHIFT                      7
3297 /* S2 Bit Fields */
3298 #define UART0_S2_RAF_MASK                        0x1u
3299 #define UART0_S2_RAF_SHIFT                       0
3300 #define UART0_S2_LBKDE_MASK                      0x2u
3301 #define UART0_S2_LBKDE_SHIFT                     1
3302 #define UART0_S2_BRK13_MASK                      0x4u
3303 #define UART0_S2_BRK13_SHIFT                     2
3304 #define UART0_S2_RWUID_MASK                      0x8u
3305 #define UART0_S2_RWUID_SHIFT                     3
3306 #define UART0_S2_RXINV_MASK                      0x10u
3307 #define UART0_S2_RXINV_SHIFT                     4
3308 #define UART0_S2_MSBF_MASK                       0x20u
3309 #define UART0_S2_MSBF_SHIFT                      5
3310 #define UART0_S2_RXEDGIF_MASK                    0x40u
3311 #define UART0_S2_RXEDGIF_SHIFT                   6
3312 #define UART0_S2_LBKDIF_MASK                     0x80u
3313 #define UART0_S2_LBKDIF_SHIFT                    7
3314 /* C3 Bit Fields */
3315 #define UART0_C3_PEIE_MASK                       0x1u
3316 #define UART0_C3_PEIE_SHIFT                      0
3317 #define UART0_C3_FEIE_MASK                       0x2u
3318 #define UART0_C3_FEIE_SHIFT                      1
3319 #define UART0_C3_NEIE_MASK                       0x4u
3320 #define UART0_C3_NEIE_SHIFT                      2
3321 #define UART0_C3_ORIE_MASK                       0x8u
3322 #define UART0_C3_ORIE_SHIFT                      3
3323 #define UART0_C3_TXINV_MASK                      0x10u
3324 #define UART0_C3_TXINV_SHIFT                     4
3325 #define UART0_C3_TXDIR_MASK                      0x20u
3326 #define UART0_C3_TXDIR_SHIFT                     5
3327 #define UART0_C3_R9T8_MASK                       0x40u
3328 #define UART0_C3_R9T8_SHIFT                      6
3329 #define UART0_C3_R8T9_MASK                       0x80u
3330 #define UART0_C3_R8T9_SHIFT                      7
3331 /* D Bit Fields */
3332 #define UART0_D_R0T0_MASK                        0x1u
3333 #define UART0_D_R0T0_SHIFT                       0
3334 #define UART0_D_R1T1_MASK                        0x2u
3335 #define UART0_D_R1T1_SHIFT                       1
3336 #define UART0_D_R2T2_MASK                        0x4u
3337 #define UART0_D_R2T2_SHIFT                       2
3338 #define UART0_D_R3T3_MASK                        0x8u
3339 #define UART0_D_R3T3_SHIFT                       3
3340 #define UART0_D_R4T4_MASK                        0x10u
3341 #define UART0_D_R4T4_SHIFT                       4
3342 #define UART0_D_R5T5_MASK                        0x20u
3343 #define UART0_D_R5T5_SHIFT                       5
3344 #define UART0_D_R6T6_MASK                        0x40u
3345 #define UART0_D_R6T6_SHIFT                       6
3346 #define UART0_D_R7T7_MASK                        0x80u
3347 #define UART0_D_R7T7_SHIFT                       7
3348 /* MA1 Bit Fields */
3349 #define UART0_MA1_MA_MASK                        0xFFu
3350 #define UART0_MA1_MA_SHIFT                       0
3351 #define UART0_MA1_MA(x)                          (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
3352 /* MA2 Bit Fields */
3353 #define UART0_MA2_MA_MASK                        0xFFu
3354 #define UART0_MA2_MA_SHIFT                       0
3355 #define UART0_MA2_MA(x)                          (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
3356 /* C4 Bit Fields */
3357 #define UART0_C4_OSR_MASK                        0x1Fu
3358 #define UART0_C4_OSR_SHIFT                       0
3359 #define UART0_C4_OSR(x)                          (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
3360 #define UART0_C4_M10_MASK                        0x20u
3361 #define UART0_C4_M10_SHIFT                       5
3362 #define UART0_C4_MAEN2_MASK                      0x40u
3363 #define UART0_C4_MAEN2_SHIFT                     6
3364 #define UART0_C4_MAEN1_MASK                      0x80u
3365 #define UART0_C4_MAEN1_SHIFT                     7
3366 /* C5 Bit Fields */
3367 #define UART0_C5_RESYNCDIS_MASK                  0x1u
3368 #define UART0_C5_RESYNCDIS_SHIFT                 0
3369 #define UART0_C5_BOTHEDGE_MASK                   0x2u
3370 #define UART0_C5_BOTHEDGE_SHIFT                  1
3371 #define UART0_C5_RDMAE_MASK                      0x20u
3372 #define UART0_C5_RDMAE_SHIFT                     5
3373 #define UART0_C5_TDMAE_MASK                      0x80u
3374 #define UART0_C5_TDMAE_SHIFT                     7
3375
3376 /**
3377  * @}
3378  */ /* end of group UART0_Register_Masks */
3379
3380
3381 /* UART0 - Peripheral instance base addresses */
3382 /** Peripheral UART0 base address */
3383 #define UART0_BASE                               (0x4006A000u)
3384 /** Peripheral UART0 base pointer */
3385 #define UART0                                    ((UART0_Type *)UART0_BASE)
3386 /** Array initializer of UART0 peripheral base pointers */
3387 #define UART0_BASES                              { UART0 }
3388
3389 /**
3390  * @}
3391  */ /* end of group UART0_Peripheral_Access_Layer */
3392
3393
3394 /*
3395 ** End of section using anonymous unions
3396 */
3397
3398 #if defined(__ARMCC_VERSION)
3399   #pragma pop
3400 #elif defined(__CWCC__)
3401   #pragma pop
3402 #elif defined(__GNUC__)
3403   /* leave anonymous unions enabled */
3404 #elif defined(__IAR_SYSTEMS_ICC__)
3405   #pragma language=default
3406 #else
3407   #error Not supported compiler type
3408 #endif
3409
3410 /**
3411  * @}
3412  */ /* end of group Peripheral_access_layer */
3413
3414
3415 /* ----------------------------------------------------------------------------
3416    -- Backward Compatibility
3417    ---------------------------------------------------------------------------- */
3418
3419 /**
3420  * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
3421  * @{
3422  */
3423
3424 #define DMA_REQC_ARR_DMAC_MASK                   This_symbol_has_been_deprecated
3425 #define DMA_REQC_ARR_DMAC_SHIFT                  This_symbol_has_been_deprecated
3426 #define DMA_REQC_ARR_DMAC(x)                     This_symbol_has_been_deprecated
3427 #define DMA_REQC_ARR_CFSM_MASK                   This_symbol_has_been_deprecated
3428 #define DMA_REQC_ARR_CFSM_SHIFT                  This_symbol_has_been_deprecated
3429 #define DMA_REQC0                                This_symbol_has_been_deprecated
3430 #define DMA_REQC1                                This_symbol_has_been_deprecated
3431 #define DMA_REQC2                                This_symbol_has_been_deprecated
3432 #define DMA_REQC3                                This_symbol_has_been_deprecated
3433 #define MCG_C6_CME0_MASK                         MCG_C6_CME_MASK
3434 #define MCG_C6_CME0_SHIFT                        MCG_C6_CME_SHIFT
3435 #define MCM_MATCR_ATC0_MASK                      This_symbol_has_been_deprecated
3436 #define MCM_MATCR_ATC0_SHIFT                     This_symbol_has_been_deprecated
3437 #define MCM_MATCR_ATC0(x)                        This_symbol_has_been_deprecated
3438 #define MCM_MATCR_RO0_MASK                       This_symbol_has_been_deprecated
3439 #define MCM_MATCR_RO0_SHIFT                      This_symbol_has_been_deprecated
3440 #define MCM_MATCR_ATC1_MASK                      This_symbol_has_been_deprecated
3441 #define MCM_MATCR_ATC1_SHIFT                     This_symbol_has_been_deprecated
3442 #define MCM_MATCR_ATC1(x)                        This_symbol_has_been_deprecated
3443 #define MCM_MATCR_RO1_MASK                       This_symbol_has_been_deprecated
3444 #define MCM_MATCR_RO1_SHIFT                      This_symbol_has_been_deprecated
3445 #define MCM_MATCR_ATC2_MASK                      This_symbol_has_been_deprecated
3446 #define MCM_MATCR_ATC2_SHIFT                     This_symbol_has_been_deprecated
3447 #define MCM_MATCR_ATC2(x)                        This_symbol_has_been_deprecated
3448 #define MCM_MATCR_RO2_MASK                       This_symbol_has_been_deprecated
3449 #define MCM_MATCR_RO2_SHIFT                      This_symbol_has_been_deprecated
3450 #define MCM_MATCR_ATC3_MASK                      This_symbol_has_been_deprecated
3451 #define MCM_MATCR_ATC3_SHIFT                     This_symbol_has_been_deprecated
3452 #define MCM_MATCR_ATC3(x)                        This_symbol_has_been_deprecated
3453 #define MCM_MATCR_RO3_MASK                       This_symbol_has_been_deprecated
3454 #define MCM_MATCR_RO3_SHIFT                      This_symbol_has_been_deprecated
3455 #define SIM_FCFG2_MAXADDR_MASK                   SIM_FCFG2_MAXADDR0_MASK
3456 #define SIM_FCFG2_MAXADDR_SHIFT                  SIM_FCFG2_MAXADDR0_SHIFT
3457 #define SIM_FCFG2_MAXADDR                        SIM_FCFG2_MAXADDR0
3458 #define SPI_C2_SPLPIE_MASK                       This_symbol_has_been_deprecated
3459 #define SPI_C2_SPLPIE_SHIFT                      This_symbol_has_been_deprecated
3460 #define UARTLP_Type                              UART0_Type
3461 #define UARTLP_BDH_REG                           UART0_BDH_REG
3462 #define UARTLP_BDL_REG                           UART0_BDL_REG
3463 #define UARTLP_C1_REG                            UART0_C1_REG
3464 #define UARTLP_C2_REG                            UART0_C2_REG
3465 #define UARTLP_S1_REG                            UART0_S1_REG
3466 #define UARTLP_S2_REG                            UART0_S2_REG
3467 #define UARTLP_C3_REG                            UART0_C3_REG
3468 #define UARTLP_D_REG                             UART0_D_REG
3469 #define UARTLP_MA1_REG                           UART0_MA1_REG
3470 #define UARTLP_MA2_REG                           UART0_MA2_REG
3471 #define UARTLP_C4_REG                            UART0_C4_REG
3472 #define UARTLP_C5_REG                            UART0_C5_REG
3473 #define UARTLP_BDH_SBR_MASK                      UART0_BDH_SBR_MASK
3474 #define UARTLP_BDH_SBR_SHIFT                     UART0_BDH_SBR_SHIFT
3475 #define UARTLP_BDH_SBR(x)                        UART0_BDH_SBR(x)
3476 #define UARTLP_BDH_SBNS_MASK                     UART0_BDH_SBNS_MASK
3477 #define UARTLP_BDH_SBNS_SHIFT                    UART0_BDH_SBNS_SHIFT
3478 #define UARTLP_BDH_RXEDGIE_MASK                  UART0_BDH_RXEDGIE_MASK
3479 #define UARTLP_BDH_RXEDGIE_SHIFT                 UART0_BDH_RXEDGIE_SHIFT
3480 #define UARTLP_BDH_LBKDIE_MASK                   UART0_BDH_LBKDIE_MASK
3481 #define UARTLP_BDH_LBKDIE_SHIFT                  UART0_BDH_LBKDIE_SHIFT
3482 #define UARTLP_BDL_SBR_MASK                      UART0_BDL_SBR_MASK
3483 #define UARTLP_BDL_SBR_SHIFT                     UART0_BDL_SBR_SHIFT
3484 #define UARTLP_BDL_SBR(x)                        UART0_BDL_SBR(x)
3485 #define UARTLP_C1_PT_MASK                        UART0_C1_PT_MASK
3486 #define UARTLP_C1_PT_SHIFT                       UART0_C1_PT_SHIFT
3487 #define UARTLP_C1_PE_MASK                        UART0_C1_PE_MASK
3488 #define UARTLP_C1_PE_SHIFT                       UART0_C1_PE_SHIFT
3489 #define UARTLP_C1_ILT_MASK                       UART0_C1_ILT_MASK
3490 #define UARTLP_C1_ILT_SHIFT                      UART0_C1_ILT_SHIFT
3491 #define UARTLP_C1_WAKE_MASK                      UART0_C1_WAKE_MASK
3492 #define UARTLP_C1_WAKE_SHIFT                     UART0_C1_WAKE_SHIFT
3493 #define UARTLP_C1_M_MASK                         UART0_C1_M_MASK
3494 #define UARTLP_C1_M_SHIFT                        UART0_C1_M_SHIFT
3495 #define UARTLP_C1_RSRC_MASK                      UART0_C1_RSRC_MASK
3496 #define UARTLP_C1_RSRC_SHIFT                     UART0_C1_RSRC_SHIFT
3497 #define UARTLP_C1_DOZEEN_MASK                    UART0_C1_DOZEEN_MASK
3498 #define UARTLP_C1_DOZEEN_SHIFT                   UART0_C1_DOZEEN_SHIFT
3499 #define UARTLP_C1_LOOPS_MASK                     UART0_C1_LOOPS_MASK
3500 #define UARTLP_C1_LOOPS_SHIFT                    UART0_C1_LOOPS_SHIFT
3501 #define UARTLP_C2_SBK_MASK                       UART0_C2_SBK_MASK
3502 #define UARTLP_C2_SBK_SHIFT                      UART0_C2_SBK_SHIFT
3503 #define UARTLP_C2_RWU_MASK                       UART0_C2_RWU_MASK
3504 #define UARTLP_C2_RWU_SHIFT                      UART0_C2_RWU_SHIFT
3505 #define UARTLP_C2_RE_MASK                        UART0_C2_RE_MASK
3506 #define UARTLP_C2_RE_SHIFT                       UART0_C2_RE_SHIFT
3507 #define UARTLP_C2_TE_MASK                        UART0_C2_TE_MASK
3508 #define UARTLP_C2_TE_SHIFT                       UART0_C2_TE_SHIFT
3509 #define UARTLP_C2_ILIE_MASK                      UART0_C2_ILIE_MASK
3510 #define UARTLP_C2_ILIE_SHIFT                     UART0_C2_ILIE_SHIFT
3511 #define UARTLP_C2_RIE_MASK                       UART0_C2_RIE_MASK
3512 #define UARTLP_C2_RIE_SHIFT                      UART0_C2_RIE_SHIFT
3513 #define UARTLP_C2_TCIE_MASK                      UART0_C2_TCIE_MASK
3514 #define UARTLP_C2_TCIE_SHIFT                     UART0_C2_TCIE_SHIFT
3515 #define UARTLP_C2_TIE_MASK                       UART0_C2_TIE_MASK
3516 #define UARTLP_C2_TIE_SHIFT                      UART0_C2_TIE_SHIFT
3517 #define UARTLP_S1_PF_MASK                        UART0_S1_PF_MASK
3518 #define UARTLP_S1_PF_SHIFT                       UART0_S1_PF_SHIFT
3519 #define UARTLP_S1_FE_MASK                        UART0_S1_FE_MASK
3520 #define UARTLP_S1_FE_SHIFT                       UART0_S1_FE_SHIFT
3521 #define UARTLP_S1_NF_MASK                        UART0_S1_NF_MASK
3522 #define UARTLP_S1_NF_SHIFT                       UART0_S1_NF_SHIFT
3523 #define UARTLP_S1_OR_MASK                        UART0_S1_OR_MASK
3524 #define UARTLP_S1_OR_SHIFT                       UART0_S1_OR_SHIFT
3525 #define UARTLP_S1_IDLE_MASK                      UART0_S1_IDLE_MASK
3526 #define UARTLP_S1_IDLE_SHIFT                     UART0_S1_IDLE_SHIFT
3527 #define UARTLP_S1_RDRF_MASK                      UART0_S1_RDRF_MASK
3528 #define UARTLP_S1_RDRF_SHIFT                     UART0_S1_RDRF_SHIFT
3529 #define UARTLP_S1_TC_MASK                        UART0_S1_TC_MASK
3530 #define UARTLP_S1_TC_SHIFT                       UART0_S1_TC_SHIFT
3531 #define UARTLP_S1_TDRE_MASK                      UART0_S1_TDRE_MASK
3532 #define UARTLP_S1_TDRE_SHIFT                     UART0_S1_TDRE_SHIFT
3533 #define UARTLP_S2_RAF_MASK                       UART0_S2_RAF_MASK
3534 #define UARTLP_S2_RAF_SHIFT                      UART0_S2_RAF_SHIFT
3535 #define UARTLP_S2_LBKDE_MASK                     UART0_S2_LBKDE_MASK
3536 #define UARTLP_S2_LBKDE_SHIFT                    UART0_S2_LBKDE_SHIFT
3537 #define UARTLP_S2_BRK13_MASK                     UART0_S2_BRK13_MASK
3538 #define UARTLP_S2_BRK13_SHIFT                    UART0_S2_BRK13_SHIFT
3539 #define UARTLP_S2_RWUID_MASK                     UART0_S2_RWUID_MASK
3540 #define UARTLP_S2_RWUID_SHIFT                    UART0_S2_RWUID_SHIFT
3541 #define UARTLP_S2_RXINV_MASK                     UART0_S2_RXINV_MASK
3542 #define UARTLP_S2_RXINV_SHIFT                    UART0_S2_RXINV_SHIFT
3543 #define UARTLP_S2_MSBF_MASK                      UART0_S2_MSBF_MASK
3544 #define UARTLP_S2_MSBF_SHIFT                     UART0_S2_MSBF_SHIFT
3545 #define UARTLP_S2_RXEDGIF_MASK                   UART0_S2_RXEDGIF_MASK
3546 #define UARTLP_S2_RXEDGIF_SHIFT                  UART0_S2_RXEDGIF_SHIFT
3547 #define UARTLP_S2_LBKDIF_MASK                    UART0_S2_LBKDIF_MASK
3548 #define UARTLP_S2_LBKDIF_SHIFT                   UART0_S2_LBKDIF_SHIFT
3549 #define UARTLP_C3_PEIE_MASK                      UART0_C3_PEIE_MASK
3550 #define UARTLP_C3_PEIE_SHIFT                     UART0_C3_PEIE_SHIFT
3551 #define UARTLP_C3_FEIE_MASK                      UART0_C3_FEIE_MASK
3552 #define UARTLP_C3_FEIE_SHIFT                     UART0_C3_FEIE_SHIFT
3553 #define UARTLP_C3_NEIE_MASK                      UART0_C3_NEIE_MASK
3554 #define UARTLP_C3_NEIE_SHIFT                     UART0_C3_NEIE_SHIFT
3555 #define UARTLP_C3_ORIE_MASK                      UART0_C3_ORIE_MASK
3556 #define UARTLP_C3_ORIE_SHIFT                     UART0_C3_ORIE_SHIFT
3557 #define UARTLP_C3_TXINV_MASK                     UART0_C3_TXINV_MASK
3558 #define UARTLP_C3_TXINV_SHIFT                    UART0_C3_TXINV_SHIFT
3559 #define UARTLP_C3_TXDIR_MASK                     UART0_C3_TXDIR_MASK
3560 #define UARTLP_C3_TXDIR_SHIFT                    UART0_C3_TXDIR_SHIFT
3561 #define UARTLP_C3_R9T8_MASK                      UART0_C3_R9T8_MASK
3562 #define UARTLP_C3_R9T8_SHIFT                     UART0_C3_R9T8_SHIFT
3563 #define UARTLP_C3_R8T9_MASK                      UART0_C3_R8T9_MASK
3564 #define UARTLP_C3_R8T9_SHIFT                     UART0_C3_R8T9_SHIFT
3565 #define UARTLP_D_R0T0_MASK                       UART0_D_R0T0_MASK
3566 #define UARTLP_D_R0T0_SHIFT                      UART0_D_R0T0_SHIFT
3567 #define UARTLP_D_R1T1_MASK                       UART0_D_R1T1_MASK
3568 #define UARTLP_D_R1T1_SHIFT                      UART0_D_R1T1_SHIFT
3569 #define UARTLP_D_R2T2_MASK                       UART0_D_R2T2_MASK
3570 #define UARTLP_D_R2T2_SHIFT                      UART0_D_R2T2_SHIFT
3571 #define UARTLP_D_R3T3_MASK                       UART0_D_R3T3_MASK
3572 #define UARTLP_D_R3T3_SHIFT                      UART0_D_R3T3_SHIFT
3573 #define UARTLP_D_R4T4_MASK                       UART0_D_R4T4_MASK
3574 #define UARTLP_D_R4T4_SHIFT                      UART0_D_R4T4_SHIFT
3575 #define UARTLP_D_R5T5_MASK                       UART0_D_R5T5_MASK
3576 #define UARTLP_D_R5T5_SHIFT                      UART0_D_R5T5_SHIFT
3577 #define UARTLP_D_R6T6_MASK                       UART0_D_R6T6_MASK
3578 #define UARTLP_D_R6T6_SHIFT                      UART0_D_R6T6_SHIFT
3579 #define UARTLP_D_R7T7_MASK                       UART0_D_R7T7_MASK
3580 #define UARTLP_D_R7T7_SHIFT                      UART0_D_R7T7_SHIFT
3581 #define UARTLP_MA1_MA_MASK                       UART0_MA1_MA_MASK
3582 #define UARTLP_MA1_MA_SHIFT                      UART0_MA1_MA_SHIFT
3583 #define UARTLP_MA1_MA(x)                         UART0_MA1_MA(x)
3584 #define UARTLP_MA2_MA_MASK                       UART0_MA2_MA_MASK
3585 #define UARTLP_MA2_MA_SHIFT                      UART0_MA2_MA_SHIFT
3586 #define UARTLP_MA2_MA(x)                         UART0_MA2_MA(x)
3587 #define UARTLP_C4_OSR_MASK                       UART0_C4_OSR_MASK
3588 #define UARTLP_C4_OSR_SHIFT                      UART0_C4_OSR_SHIFT
3589 #define UARTLP_C4_OSR(x)                         UART0_C4_OSR(x)
3590 #define UARTLP_C4_M10_MASK                       UART0_C4_M10_MASK
3591 #define UARTLP_C4_M10_SHIFT                      UART0_C4_M10_SHIFT
3592 #define UARTLP_C4_MAEN2_MASK                     UART0_C4_MAEN2_MASK
3593 #define UARTLP_C4_MAEN2_SHIFT                    UART0_C4_MAEN2_SHIFT
3594 #define UARTLP_C4_MAEN1_MASK                     UART0_C4_MAEN1_MASK
3595 #define UARTLP_C4_MAEN1_SHIFT                    UART0_C4_MAEN1_SHIFT
3596 #define UARTLP_C5_RESYNCDIS_MASK                 UART0_C5_RESYNCDIS_MASK
3597 #define UARTLP_C5_RESYNCDIS_SHIFT                UART0_C5_RESYNCDIS_SHIFT
3598 #define UARTLP_C5_BOTHEDGE_MASK                  UART0_C5_BOTHEDGE_MASK
3599 #define UARTLP_C5_BOTHEDGE_SHIFT                 UART0_C5_BOTHEDGE_SHIFT
3600 #define UARTLP_C5_RDMAE_MASK                     UART0_C5_RDMAE_MASK
3601 #define UARTLP_C5_RDMAE_SHIFT                    UART0_C5_RDMAE_SHIFT
3602 #define UARTLP_C5_TDMAE_MASK                     UART0_C5_TDMAE_MASK
3603 #define UARTLP_C5_TDMAE_SHIFT                    UART0_C5_TDMAE_SHIFT
3604 #define UARTLP_BASES                             UARTLP_BASES
3605
3606 /**
3607  * @}
3608  */ /* end of group Backward_Compatibility_Symbols */
3609
3610
3611 #endif  /* #if !defined(MKL05Z4_H_) */
3612
3613 /* MKL05Z4.h, eof. */