tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12.s

   1 ;/*****************************************************************************
   2 ; * @file:    startup_MK22F12.s
   3 ; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
   4 ; *           MK22F12
   5 ; * @version: 1.5
   6 ; * @date:    2013-5-16
   7 ; *
   8 ; * Copyright: 1997 - 2013 Freescale Semiconductor, Inc. All Rights Reserved.
   9 ;*
  10 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
  11 ; *
  12 ; *****************************************************************************/
  13
  14
  15 __initial_sp        EQU     0x20010000  ; Top of RAM
  16
  17                 PRESERVE8
  18                 THUMB
  19
  20
  21 ; Vector Table Mapped to Address 0 at Reset
  22
  23                 AREA    RESET, DATA, READONLY
  24                 EXPORT  __Vectors
  25                 EXPORT  __Vectors_End
  26                 EXPORT  __Vectors_Size
  27
  28 __Vectors       DCD     __initial_sp  ; Top of Stack
  29                 DCD     Reset_Handler  ; Reset Handler
  30                 DCD     NMI_Handler  ; NMI Handler
  31                 DCD     HardFault_Handler  ; Hard Fault Handler
  32                 DCD     MemManage_Handler  ; MPU Fault Handler
  33                 DCD     BusFault_Handler  ; Bus Fault Handler
  34                 DCD     UsageFault_Handler  ; Usage Fault Handler
  35                 DCD     0  ; Reserved
  36                 DCD     0  ; Reserved
  37                 DCD     0  ; Reserved
  38                 DCD     0  ; Reserved
  39                 DCD     SVC_Handler  ; SVCall Handler
  40                 DCD     DebugMon_Handler  ; Debug Monitor Handler
  41                 DCD     0  ; Reserved
  42                 DCD     PendSV_Handler  ; PendSV Handler
  43                 DCD     SysTick_Handler  ; SysTick Handler
  44
  45                 ; External Interrupts
  46                 DCD     DMA0_IRQHandler  ; DMA Channel 0 Transfer Complete
  47                 DCD     DMA1_IRQHandler  ; DMA Channel 1 Transfer Complete
  48                 DCD     DMA2_IRQHandler  ; DMA Channel 2 Transfer Complete
  49                 DCD     DMA3_IRQHandler  ; DMA Channel 3 Transfer Complete
  50                 DCD     DMA4_IRQHandler  ; DMA Channel 4 Transfer Complete
  51                 DCD     DMA5_IRQHandler  ; DMA Channel 5 Transfer Complete
  52                 DCD     DMA6_IRQHandler  ; DMA Channel 6 Transfer Complete
  53                 DCD     DMA7_IRQHandler  ; DMA Channel 7 Transfer Complete
  54                 DCD     DMA8_IRQHandler  ; DMA Channel 8 Transfer Complete
  55                 DCD     DMA9_IRQHandler  ; DMA Channel 9 Transfer Complete
  56                 DCD     DMA10_IRQHandler  ; DMA Channel 10 Transfer Complete
  57                 DCD     DMA11_IRQHandler  ; DMA Channel 11 Transfer Complete
  58                 DCD     DMA12_IRQHandler  ; DMA Channel 12 Transfer Complete
  59                 DCD     DMA13_IRQHandler  ; DMA Channel 13 Transfer Complete
  60                 DCD     DMA14_IRQHandler  ; DMA Channel 14 Transfer Complete
  61                 DCD     DMA15_IRQHandler  ; DMA Channel 15 Transfer Complete
  62                 DCD     DMA_Error_IRQHandler  ; DMA Error Interrupt
  63                 DCD     MCM_IRQHandler  ; Normal Interrupt
  64                 DCD     FTFE_IRQHandler  ; FTFE Command complete interrupt
  65                 DCD     Read_Collision_IRQHandler  ; Read Collision Interrupt
  66                 DCD     LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
  67                 DCD     LLW_IRQHandler  ; Low Leakage Wakeup
  68                 DCD     Watchdog_IRQHandler  ; WDOG Interrupt
  69                 DCD     Reserved39_IRQHandler  ; Reserved Interrupt 39
  70                 DCD     I2C0_IRQHandler  ; I2C0 interrupt
  71                 DCD     I2C1_IRQHandler  ; I2C1 interrupt
  72                 DCD     SPI0_IRQHandler  ; SPI0 Interrupt
  73                 DCD     SPI1_IRQHandler  ; SPI1 Interrupt
  74                 DCD     I2S0_Tx_IRQHandler  ; I2S0 transmit interrupt
  75                 DCD     I2S0_Rx_IRQHandler  ; I2S0 receive interrupt
  76                 DCD     UART0_LON_IRQHandler  ; UART0 LON interrupt
  77                 DCD     UART0_RX_TX_IRQHandler  ; UART0 Receive/Transmit interrupt
  78                 DCD     UART0_ERR_IRQHandler  ; UART0 Error interrupt
  79                 DCD     UART1_RX_TX_IRQHandler  ; UART1 Receive/Transmit interrupt
  80                 DCD     UART1_ERR_IRQHandler  ; UART1 Error interrupt
  81                 DCD     UART2_RX_TX_IRQHandler  ; UART2 Receive/Transmit interrupt
  82                 DCD     UART2_ERR_IRQHandler  ; UART2 Error interrupt
  83                 DCD     UART3_RX_TX_IRQHandler  ; UART3 Receive/Transmit interrupt
  84                 DCD     UART3_ERR_IRQHandler  ; UART3 Error interrupt
  85                 DCD     ADC0_IRQHandler  ; ADC0 interrupt
  86                 DCD     CMP0_IRQHandler  ; CMP0 interrupt
  87                 DCD     CMP1_IRQHandler  ; CMP1 interrupt
  88                 DCD     FTM0_IRQHandler  ; FTM0 fault, overflow and channels interrupt
  89                 DCD     FTM1_IRQHandler  ; FTM1 fault, overflow and channels interrupt
  90                 DCD     FTM2_IRQHandler  ; FTM2 fault, overflow and channels interrupt
  91                 DCD     CMT_IRQHandler  ; CMT interrupt
  92                 DCD     RTC_IRQHandler  ; RTC interrupt
  93                 DCD     RTC_Seconds_IRQHandler  ; RTC seconds interrupt
  94                 DCD     PIT0_IRQHandler  ; PIT timer channel 0 interrupt
  95                 DCD     PIT1_IRQHandler  ; PIT timer channel 1 interrupt
  96                 DCD     PIT2_IRQHandler  ; PIT timer channel 2 interrupt
  97                 DCD     PIT3_IRQHandler  ; PIT timer channel 3 interrupt
  98                 DCD     PDB0_IRQHandler  ; PDB0 Interrupt
  99                 DCD     USB0_IRQHandler  ; USB0 interrupt
 100                 DCD     USBDCD_IRQHandler  ; USBDCD Interrupt
 101                 DCD     Reserved71_IRQHandler  ; Reserved interrupt 71
 102                 DCD     DAC0_IRQHandler  ; DAC0 interrupt
 103                 DCD     MCG_IRQHandler  ; MCG Interrupt
 104                 DCD     LPTimer_IRQHandler  ; LPTimer interrupt
 105                 DCD     PORTA_IRQHandler  ; Port A interrupt
 106                 DCD     PORTB_IRQHandler  ; Port B interrupt
 107                 DCD     PORTC_IRQHandler  ; Port C interrupt
 108                 DCD     PORTD_IRQHandler  ; Port D interrupt
 109                 DCD     PORTE_IRQHandler  ; Port E interrupt
 110                 DCD     SWI_IRQHandler  ; Software interrupt
 111                 DCD     SPI2_IRQHandler  ; SPI2 Interrupt
 112                 DCD     UART4_RX_TX_IRQHandler  ; UART4 Receive/Transmit interrupt
 113                 DCD     UART4_ERR_IRQHandler  ; UART4 Error interrupt
 114                 DCD     UART5_RX_TX_IRQHandler  ; UART5 Receive/Transmit interrupt
 115                 DCD     UART5_ERR_IRQHandler  ; UART5 Error interrupt
 116                 DCD     CMP2_IRQHandler  ; CMP2 interrupt
 117                 DCD     FTM3_IRQHandler  ; FTM3 fault, overflow and channels interrupt
 118                 DCD     DAC1_IRQHandler  ; DAC1 interrupt
 119                 DCD     ADC1_IRQHandler  ; ADC1 interrupt
 120                 DCD     I2C2_IRQHandler  ; I2C2 interrupt
 121                 DCD     CAN0_ORed_Message_buffer_IRQHandler  ; CAN0 OR'd message buffers interrupt
 122                 DCD     CAN0_Bus_Off_IRQHandler  ; CAN0 bus off interrupt
 123                 DCD     CAN0_Error_IRQHandler  ; CAN0 error interrupt
 124                 DCD     CAN0_Tx_Warning_IRQHandler  ; CAN0 Tx warning interrupt
 125                 DCD     CAN0_Rx_Warning_IRQHandler  ; CAN0 Rx warning interrupt
 126                 DCD     CAN0_Wake_Up_IRQHandler  ; CAN0 wake up interrupt
 127                 DCD     SDHC_IRQHandler  ; SDHC interrupt
 128                 DCD     DefaultISR  ; 98
 129                 DCD     DefaultISR  ; 99
 130                 DCD     DefaultISR  ; 100
 131                 DCD     DefaultISR  ; 101
 132                 DCD     DefaultISR  ; 102
 133                 DCD     DefaultISR  ; 103
 134                 DCD     DefaultISR  ; 104
 135                 DCD     DefaultISR  ; 105
 136                 DCD     DefaultISR  ; 106
 137                 DCD     DefaultISR  ; 107
 138                 DCD     DefaultISR  ; 108
 139                 DCD     DefaultISR  ; 109
 140                 DCD     DefaultISR  ; 110
 141                 DCD     DefaultISR  ; 111
 142                 DCD     DefaultISR  ; 112
 143                 DCD     DefaultISR  ; 113
 144                 DCD     DefaultISR  ; 114
 145                 DCD     DefaultISR  ; 115
 146                 DCD     DefaultISR  ; 116
 147                 DCD     DefaultISR  ; 117
 148                 DCD     DefaultISR  ; 118
 149                 DCD     DefaultISR  ; 119
 150                 DCD     DefaultISR  ; 120
 151                 DCD     DefaultISR  ; 121
 152                 DCD     DefaultISR  ; 122
 153                 DCD     DefaultISR  ; 123
 154                 DCD     DefaultISR  ; 124
 155                 DCD     DefaultISR  ; 125
 156                 DCD     DefaultISR  ; 126
 157                 DCD     DefaultISR  ; 127
 158                 DCD     DefaultISR  ; 128
 159                 DCD     DefaultISR  ; 129
 160                 DCD     DefaultISR  ; 130
 161                 DCD     DefaultISR  ; 131
 162                 DCD     DefaultISR  ; 132
 163                 DCD     DefaultISR  ; 133
 164                 DCD     DefaultISR  ; 134
 165                 DCD     DefaultISR  ; 135
 166                 DCD     DefaultISR  ; 136
 167                 DCD     DefaultISR  ; 137
 168                 DCD     DefaultISR  ; 138
 169                 DCD     DefaultISR  ; 139
 170                 DCD     DefaultISR  ; 140
 171                 DCD     DefaultISR  ; 141
 172                 DCD     DefaultISR  ; 142
 173                 DCD     DefaultISR  ; 143
 174                 DCD     DefaultISR  ; 144
 175                 DCD     DefaultISR  ; 145
 176                 DCD     DefaultISR  ; 146
 177                 DCD     DefaultISR  ; 147
 178                 DCD     DefaultISR  ; 148
 179                 DCD     DefaultISR  ; 149
 180                 DCD     DefaultISR  ; 150
 181                 DCD     DefaultISR  ; 151
 182                 DCD     DefaultISR  ; 152
 183                 DCD     DefaultISR  ; 153
 184                 DCD     DefaultISR  ; 154
 185                 DCD     DefaultISR  ; 155
 186                 DCD     DefaultISR  ; 156
 187                 DCD     DefaultISR  ; 157
 188                 DCD     DefaultISR  ; 158
 189                 DCD     DefaultISR  ; 159
 190                 DCD     DefaultISR  ; 160
 191                 DCD     DefaultISR  ; 161
 192                 DCD     DefaultISR  ; 162
 193                 DCD     DefaultISR  ; 163
 194                 DCD     DefaultISR  ; 164
 195                 DCD     DefaultISR  ; 165
 196                 DCD     DefaultISR  ; 166
 197                 DCD     DefaultISR  ; 167
 198                 DCD     DefaultISR  ; 168
 199                 DCD     DefaultISR  ; 169
 200                 DCD     DefaultISR  ; 170
 201                 DCD     DefaultISR  ; 171
 202                 DCD     DefaultISR  ; 172
 203                 DCD     DefaultISR  ; 173
 204                 DCD     DefaultISR  ; 174
 205                 DCD     DefaultISR  ; 175
 206                 DCD     DefaultISR  ; 176
 207                 DCD     DefaultISR  ; 177
 208                 DCD     DefaultISR  ; 178
 209                 DCD     DefaultISR  ; 179
 210                 DCD     DefaultISR  ; 180
 211                 DCD     DefaultISR  ; 181
 212                 DCD     DefaultISR  ; 182
 213                 DCD     DefaultISR  ; 183
 214                 DCD     DefaultISR  ; 184
 215                 DCD     DefaultISR  ; 185
 216                 DCD     DefaultISR  ; 186
 217                 DCD     DefaultISR  ; 187
 218                 DCD     DefaultISR  ; 188
 219                 DCD     DefaultISR  ; 189
 220                 DCD     DefaultISR  ; 190
 221                 DCD     DefaultISR  ; 191
 222                 DCD     DefaultISR  ; 192
 223                 DCD     DefaultISR  ; 193
 224                 DCD     DefaultISR  ; 194
 225                 DCD     DefaultISR  ; 195
 226                 DCD     DefaultISR  ; 196
 227                 DCD     DefaultISR  ; 197
 228                 DCD     DefaultISR  ; 198
 229                 DCD     DefaultISR  ; 199
 230                 DCD     DefaultISR  ; 200
 231                 DCD     DefaultISR  ; 201
 232                 DCD     DefaultISR  ; 202
 233                 DCD     DefaultISR  ; 203
 234                 DCD     DefaultISR  ; 204
 235                 DCD     DefaultISR  ; 205
 236                 DCD     DefaultISR  ; 206
 237                 DCD     DefaultISR  ; 207
 238                 DCD     DefaultISR  ; 208
 239                 DCD     DefaultISR  ; 209
 240                 DCD     DefaultISR  ; 210
 241                 DCD     DefaultISR  ; 211
 242                 DCD     DefaultISR  ; 212
 243                 DCD     DefaultISR  ; 213
 244                 DCD     DefaultISR  ; 214
 245                 DCD     DefaultISR  ; 215
 246                 DCD     DefaultISR  ; 216
 247                 DCD     DefaultISR  ; 217
 248                 DCD     DefaultISR  ; 218
 249                 DCD     DefaultISR  ; 219
 250                 DCD     DefaultISR  ; 220
 251                 DCD     DefaultISR  ; 221
 252                 DCD     DefaultISR  ; 222
 253                 DCD     DefaultISR  ; 223
 254                 DCD     DefaultISR  ; 224
 255                 DCD     DefaultISR  ; 225
 256                 DCD     DefaultISR  ; 226
 257                 DCD     DefaultISR  ; 227
 258                 DCD     DefaultISR  ; 228
 259                 DCD     DefaultISR  ; 229
 260                 DCD     DefaultISR  ; 230
 261                 DCD     DefaultISR  ; 231
 262                 DCD     DefaultISR  ; 232
 263                 DCD     DefaultISR  ; 233
 264                 DCD     DefaultISR  ; 234
 265                 DCD     DefaultISR  ; 235
 266                 DCD     DefaultISR  ; 236
 267                 DCD     DefaultISR  ; 237
 268                 DCD     DefaultISR  ; 238
 269                 DCD     DefaultISR  ; 239
 270                 DCD     DefaultISR  ; 240
 271                 DCD     DefaultISR  ; 241
 272                 DCD     DefaultISR  ; 242
 273                 DCD     DefaultISR  ; 243
 274                 DCD     DefaultISR  ; 244
 275                 DCD     DefaultISR  ; 245
 276                 DCD     DefaultISR  ; 246
 277                 DCD     DefaultISR  ; 247
 278                 DCD     DefaultISR  ; 248
 279                 DCD     DefaultISR  ; 249
 280                 DCD     DefaultISR  ; 250
 281                 DCD     DefaultISR  ; 251
 282                 DCD     DefaultISR  ; 252
 283                 DCD     DefaultISR  ; 253
 284                 DCD     DefaultISR  ; 254
 285                 DCD     DefaultISR  ; 255
 286 __Vectors_End
 287
 288 __Vectors_Size  EQU     __Vectors_End - __Vectors
 289
 290 ; <h> Flash Configuration
 291 ;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
 292 ;   <i> and security information that allows the MCU to restrict acces to the FTFL module.
 293 ;   <h> Backdoor Comparison Key
 294 ;     <o0>  Backdoor Key 0  <0x0-0xFF:2>
 295 ;     <o1>  Backdoor Key 1  <0x0-0xFF:2>
 296 ;     <o2>  Backdoor Key 2  <0x0-0xFF:2>
 297 ;     <o3>  Backdoor Key 3  <0x0-0xFF:2>
 298 ;     <o4>  Backdoor Key 4  <0x0-0xFF:2>
 299 ;     <o5>  Backdoor Key 5  <0x0-0xFF:2>
 300 ;     <o6>  Backdoor Key 6  <0x0-0xFF:2>
 301 ;     <o7>  Backdoor Key 7  <0x0-0xFF:2>
 302 BackDoorK0      EQU     0xFF
 303 BackDoorK1      EQU     0xFF
 304 BackDoorK2      EQU     0xFF
 305 BackDoorK3      EQU     0xFF
 306 BackDoorK4      EQU     0xFF
 307 BackDoorK5      EQU     0xFF
 308 BackDoorK6      EQU     0xFF
 309 BackDoorK7      EQU     0xFF
 310 ;   </h>
 311 ;   <h> Program flash protection bytes (FPROT)
 312 ;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
 313 ;     <i> Each bit protects a 1/32 region of the program flash memory.
 314 ;     <h> FPROT0
 315 ;       <i> Program flash protection bytes
 316 ;       <i> 1/32 - 8/32 region
 317 ;       <o.0>   FPROT0.0
 318 ;       <o.1>   FPROT0.1
 319 ;       <o.2>   FPROT0.2
 320 ;       <o.3>   FPROT0.3
 321 ;       <o.4>   FPROT0.4
 322 ;       <o.5>   FPROT0.5
 323 ;       <o.6>   FPROT0.6
 324 ;       <o.7>   FPROT0.7
 325 nFPROT0         EQU     0x00
 326 FPROT0          EQU     nFPROT0:EOR:0xFF
 327 ;     </h>
 328 ;     <h> FPROT1
 329 ;       <i> Program Flash Region Protect Register 1
 330 ;       <i> 9/32 - 16/32 region
 331 ;       <o.0>   FPROT1.0
 332 ;       <o.1>   FPROT1.1
 333 ;       <o.2>   FPROT1.2
 334 ;       <o.3>   FPROT1.3
 335 ;       <o.4>   FPROT1.4
 336 ;       <o.5>   FPROT1.5
 337 ;       <o.6>   FPROT1.6
 338 ;       <o.7>   FPROT1.7
 339 nFPROT1         EQU     0x00
 340 FPROT1          EQU     nFPROT1:EOR:0xFF
 341 ;     </h>
 342 ;     <h> FPROT2
 343 ;       <i> Program Flash Region Protect Register 2
 344 ;       <i> 17/32 - 24/32 region
 345 ;       <o.0>   FPROT2.0
 346 ;       <o.1>   FPROT2.1
 347 ;       <o.2>   FPROT2.2
 348 ;       <o.3>   FPROT2.3
 349 ;       <o.4>   FPROT2.4
 350 ;       <o.5>   FPROT2.5
 351 ;       <o.6>   FPROT2.6
 352 ;       <o.7>   FPROT2.7
 353 nFPROT2         EQU     0x00
 354 FPROT2          EQU     nFPROT2:EOR:0xFF
 355 ;     </h>
 356 ;     <h> FPROT3
 357 ;       <i> Program Flash Region Protect Register 3
 358 ;       <i> 25/32 - 32/32 region
 359 ;       <o.0>   FPROT3.0
 360 ;       <o.1>   FPROT3.1
 361 ;       <o.2>   FPROT3.2
 362 ;       <o.3>   FPROT3.3
 363 ;       <o.4>   FPROT3.4
 364 ;       <o.5>   FPROT3.5
 365 ;       <o.6>   FPROT3.6
 366 ;       <o.7>   FPROT3.7
 367 nFPROT3         EQU     0x00
 368 FPROT3          EQU     nFPROT3:EOR:0xFF
 369 ;     </h>
 370 ;   </h>
 371 ;   <h> Data flash protection byte (FDPROT)
 372 ;     <i> Each bit protects a 1/8 region of the data flash memory.
 373 ;     <i> (Program flash only devices: Reserved)
 374 ;     <o.0>   FDPROT.0
 375 ;     <o.1>   FDPROT.1
 376 ;     <o.2>   FDPROT.2
 377 ;     <o.3>   FDPROT.3
 378 ;     <o.4>   FDPROT.4
 379 ;     <o.5>   FDPROT.5
 380 ;     <o.6>   FDPROT.6
 381 ;     <o.7>   FDPROT.7
 382 nFDPROT         EQU     0x00
 383 FDPROT          EQU     nFDPROT:EOR:0xFF
 384 ;   </h>
 385 ;   <h> EEPROM protection byte (FEPROT)
 386 ;     <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
 387 ;     <i> (Program flash only devices: Reserved)
 388 ;     <o.0>   FEPROT.0
 389 ;     <o.1>   FEPROT.1
 390 ;     <o.2>   FEPROT.2
 391 ;     <o.3>   FEPROT.3
 392 ;     <o.4>   FEPROT.4
 393 ;     <o.5>   FEPROT.5
 394 ;     <o.6>   FEPROT.6
 395 ;     <o.7>   FEPROT.7
 396 nFEPROT         EQU     0x00
 397 FEPROT          EQU     nFEPROT:EOR:0xFF
 398 ;   </h>
 399 ;   <h> Flash nonvolatile option byte (FOPT)
 400 ;     <i> Allows the user to customize the operation of the MCU at boot time.
 401 ;     <o.0>  LPBOOT
 402 ;       <0=> Low-power boot
 403 ;       <1=> normal boot
 404 ;     <o.1>  EZPORT_DIS
 405 ;       <0=> EzPort operation is enabled
 406 ;       <1=> EzPort operation is disabled
 407 FOPT            EQU     0xFF
 408 ;   </h>
 409 ;   <h> Flash security byte (FSEC)
 410 ;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
 411 ;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
 412 ;     <o.0..1> SEC
 413 ;       <2=> MCU security status is unsecure
 414 ;       <3=> MCU security status is secure
 415 ;         <i> Flash Security
 416 ;         <i> This bits define the security state of the MCU.
 417 ;     <o.2..3> FSLACC
 418 ;       <2=> Freescale factory access denied
 419 ;       <3=> Freescale factory access granted
 420 ;         <i> Freescale Failure Analysis Access Code
 421 ;         <i> This bits define the security state of the MCU.
 422 ;     <o.4..5> MEEN
 423 ;       <2=> Mass erase is disabled
 424 ;       <3=> Mass erase is enabled
 425 ;         <i> Mass Erase Enable Bits
 426 ;         <i> Enables and disables mass erase capability of the FTFL module
 427 ;     <o.6..7> KEYEN
 428 ;       <2=> Backdoor key access enabled
 429 ;       <3=> Backdoor key access disabled
 430 ;         <i> Backdoor key Security Enable
 431 ;         <i> These bits enable and disable backdoor key access to the FTFL module.
 432 FSEC            EQU     0xFE
 433 ;   </h>
 434 ; </h>
 435                 IF      :LNOT::DEF:RAM_TARGET
 436                 AREA    |.ARM.__at_0x400|, CODE, READONLY
 437                 DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
 438                 DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
 439                 DCB     FPROT0,     FPROT1,     FPROT2,     FPROT3
 440                 DCB     FSEC,       FOPT,       FEPROT,     FDPROT
 441                 ENDIF
 442
 443                 AREA    |.text|, CODE, READONLY
 444
 445
 446 ; Reset Handler
 447
 448 Reset_Handler   PROC
 449                 EXPORT  Reset_Handler             [WEAK]
 450                 IMPORT  SystemInit
 451                 IMPORT  __main
 452                 LDR     R0, =SystemInit
 453                 BLX     R0
 454                 LDR     R0, =__main
 455                 BX      R0
 456                 ENDP
 457
 458
 459 ; Dummy Exception Handlers (infinite loops which can be modified)
 460
 461 NMI_Handler     PROC
 462                 EXPORT  NMI_Handler               [WEAK]
 463                 B       .
 464                 ENDP
 465 HardFault_Handler\
 466                 PROC
 467                 EXPORT  HardFault_Handler         [WEAK]
 468                 B       .
 469                 ENDP
 470 MemManage_Handler\
 471                 PROC
 472                 EXPORT  MemManage_Handler         [WEAK]
 473                 B       .
 474                 ENDP
 475 BusFault_Handler\
 476                 PROC
 477                 EXPORT  BusFault_Handler          [WEAK]
 478                 B       .
 479                 ENDP
 480 UsageFault_Handler\
 481                 PROC
 482                 EXPORT  UsageFault_Handler        [WEAK]
 483                 B       .
 484                 ENDP
 485 SVC_Handler     PROC
 486                 EXPORT  SVC_Handler               [WEAK]
 487                 B       .
 488                 ENDP
 489 DebugMon_Handler\
 490                 PROC
 491                 EXPORT  DebugMon_Handler          [WEAK]
 492                 B       .
 493                 ENDP
 494 PendSV_Handler  PROC
 495                 EXPORT  PendSV_Handler            [WEAK]
 496                 B       .
 497                 ENDP
 498 SysTick_Handler PROC
 499                 EXPORT  SysTick_Handler           [WEAK]
 500                 B       .
 501                 ENDP
 502
 503 Default_Handler PROC
 504                 EXPORT  DMA0_IRQHandler     [WEAK]
 505                 EXPORT  DMA1_IRQHandler     [WEAK]
 506                 EXPORT  DMA2_IRQHandler     [WEAK]
 507                 EXPORT  DMA3_IRQHandler     [WEAK]
 508                 EXPORT  DMA4_IRQHandler     [WEAK]
 509                 EXPORT  DMA5_IRQHandler     [WEAK]
 510                 EXPORT  DMA6_IRQHandler     [WEAK]
 511                 EXPORT  DMA7_IRQHandler     [WEAK]
 512                 EXPORT  DMA8_IRQHandler     [WEAK]
 513                 EXPORT  DMA9_IRQHandler     [WEAK]
 514                 EXPORT  DMA10_IRQHandler     [WEAK]
 515                 EXPORT  DMA11_IRQHandler     [WEAK]
 516                 EXPORT  DMA12_IRQHandler     [WEAK]
 517                 EXPORT  DMA13_IRQHandler     [WEAK]
 518                 EXPORT  DMA14_IRQHandler     [WEAK]
 519                 EXPORT  DMA15_IRQHandler     [WEAK]
 520                 EXPORT  DMA_Error_IRQHandler     [WEAK]
 521                 EXPORT  MCM_IRQHandler     [WEAK]
 522                 EXPORT  FTFE_IRQHandler     [WEAK]
 523                 EXPORT  Read_Collision_IRQHandler     [WEAK]
 524                 EXPORT  LVD_LVW_IRQHandler     [WEAK]
 525                 EXPORT  LLW_IRQHandler     [WEAK]
 526                 EXPORT  Watchdog_IRQHandler     [WEAK]
 527                 EXPORT  Reserved39_IRQHandler     [WEAK]
 528                 EXPORT  I2C0_IRQHandler     [WEAK]
 529                 EXPORT  I2C1_IRQHandler     [WEAK]
 530                 EXPORT  SPI0_IRQHandler     [WEAK]
 531                 EXPORT  SPI1_IRQHandler     [WEAK]
 532                 EXPORT  I2S0_Tx_IRQHandler     [WEAK]
 533                 EXPORT  I2S0_Rx_IRQHandler     [WEAK]
 534                 EXPORT  UART0_LON_IRQHandler     [WEAK]
 535                 EXPORT  UART0_RX_TX_IRQHandler     [WEAK]
 536                 EXPORT  UART0_ERR_IRQHandler     [WEAK]
 537                 EXPORT  UART1_RX_TX_IRQHandler     [WEAK]
 538                 EXPORT  UART1_ERR_IRQHandler     [WEAK]
 539                 EXPORT  UART2_RX_TX_IRQHandler     [WEAK]
 540                 EXPORT  UART2_ERR_IRQHandler     [WEAK]
 541                 EXPORT  UART3_RX_TX_IRQHandler     [WEAK]
 542                 EXPORT  UART3_ERR_IRQHandler     [WEAK]
 543                 EXPORT  ADC0_IRQHandler     [WEAK]
 544                 EXPORT  CMP0_IRQHandler     [WEAK]
 545                 EXPORT  CMP1_IRQHandler     [WEAK]
 546                 EXPORT  FTM0_IRQHandler     [WEAK]
 547                 EXPORT  FTM1_IRQHandler     [WEAK]
 548                 EXPORT  FTM2_IRQHandler     [WEAK]
 549                 EXPORT  CMT_IRQHandler     [WEAK]
 550                 EXPORT  RTC_IRQHandler     [WEAK]
 551                 EXPORT  RTC_Seconds_IRQHandler     [WEAK]
 552                 EXPORT  PIT0_IRQHandler     [WEAK]
 553                 EXPORT  PIT1_IRQHandler     [WEAK]
 554                 EXPORT  PIT2_IRQHandler     [WEAK]
 555                 EXPORT  PIT3_IRQHandler     [WEAK]
 556                 EXPORT  PDB0_IRQHandler     [WEAK]
 557                 EXPORT  USB0_IRQHandler     [WEAK]
 558                 EXPORT  USBDCD_IRQHandler     [WEAK]
 559                 EXPORT  Reserved71_IRQHandler     [WEAK]
 560                 EXPORT  DAC0_IRQHandler     [WEAK]
 561                 EXPORT  MCG_IRQHandler     [WEAK]
 562                 EXPORT  LPTimer_IRQHandler     [WEAK]
 563                 EXPORT  PORTA_IRQHandler     [WEAK]
 564                 EXPORT  PORTB_IRQHandler     [WEAK]
 565                 EXPORT  PORTC_IRQHandler     [WEAK]
 566                 EXPORT  PORTD_IRQHandler     [WEAK]
 567                 EXPORT  PORTE_IRQHandler     [WEAK]
 568                 EXPORT  SWI_IRQHandler     [WEAK]
 569                 EXPORT  SPI2_IRQHandler     [WEAK]
 570                 EXPORT  UART4_RX_TX_IRQHandler     [WEAK]
 571                 EXPORT  UART4_ERR_IRQHandler     [WEAK]
 572                 EXPORT  UART5_RX_TX_IRQHandler     [WEAK]
 573                 EXPORT  UART5_ERR_IRQHandler     [WEAK]
 574                 EXPORT  CMP2_IRQHandler     [WEAK]
 575                 EXPORT  FTM3_IRQHandler     [WEAK]
 576                 EXPORT  DAC1_IRQHandler     [WEAK]
 577                 EXPORT  ADC1_IRQHandler     [WEAK]
 578                 EXPORT  I2C2_IRQHandler     [WEAK]
 579                 EXPORT  CAN0_ORed_Message_buffer_IRQHandler     [WEAK]
 580                 EXPORT  CAN0_Bus_Off_IRQHandler     [WEAK]
 581                 EXPORT  CAN0_Error_IRQHandler     [WEAK]
 582                 EXPORT  CAN0_Tx_Warning_IRQHandler     [WEAK]
 583                 EXPORT  CAN0_Rx_Warning_IRQHandler     [WEAK]
 584                 EXPORT  CAN0_Wake_Up_IRQHandler     [WEAK]
 585                 EXPORT  SDHC_IRQHandler     [WEAK]
 586                 EXPORT  DefaultISR                      [WEAK]
 587
 588 DMA0_IRQHandler
 589 DMA1_IRQHandler
 590 DMA2_IRQHandler
 591 DMA3_IRQHandler
 592 DMA4_IRQHandler
 593 DMA5_IRQHandler
 594 DMA6_IRQHandler
 595 DMA7_IRQHandler
 596 DMA8_IRQHandler
 597 DMA9_IRQHandler
 598 DMA10_IRQHandler
 599 DMA11_IRQHandler
 600 DMA12_IRQHandler
 601 DMA13_IRQHandler
 602 DMA14_IRQHandler
 603 DMA15_IRQHandler
 604 DMA_Error_IRQHandler
 605 MCM_IRQHandler
 606 FTFE_IRQHandler
 607 Read_Collision_IRQHandler
 608 LVD_LVW_IRQHandler
 609 LLW_IRQHandler
 610 Watchdog_IRQHandler
 611 Reserved39_IRQHandler
 612 I2C0_IRQHandler
 613 I2C1_IRQHandler
 614 SPI0_IRQHandler
 615 SPI1_IRQHandler
 616 I2S0_Tx_IRQHandler
 617 I2S0_Rx_IRQHandler
 618 UART0_LON_IRQHandler
 619 UART0_RX_TX_IRQHandler
 620 UART0_ERR_IRQHandler
 621 UART1_RX_TX_IRQHandler
 622 UART1_ERR_IRQHandler
 623 UART2_RX_TX_IRQHandler
 624 UART2_ERR_IRQHandler
 625 UART3_RX_TX_IRQHandler
 626 UART3_ERR_IRQHandler
 627 ADC0_IRQHandler
 628 CMP0_IRQHandler
 629 CMP1_IRQHandler
 630 FTM0_IRQHandler
 631 FTM1_IRQHandler
 632 FTM2_IRQHandler
 633 CMT_IRQHandler
 634 RTC_IRQHandler
 635 RTC_Seconds_IRQHandler
 636 PIT0_IRQHandler
 637 PIT1_IRQHandler
 638 PIT2_IRQHandler
 639 PIT3_IRQHandler
 640 PDB0_IRQHandler
 641 USB0_IRQHandler
 642 USBDCD_IRQHandler
 643 Reserved71_IRQHandler
 644 DAC0_IRQHandler
 645 MCG_IRQHandler
 646 LPTimer_IRQHandler
 647 PORTA_IRQHandler
 648 PORTB_IRQHandler
 649 PORTC_IRQHandler
 650 PORTD_IRQHandler
 651 PORTE_IRQHandler
 652 SWI_IRQHandler
 653 SPI2_IRQHandler
 654 UART4_RX_TX_IRQHandler
 655 UART4_ERR_IRQHandler
 656 UART5_RX_TX_IRQHandler
 657 UART5_ERR_IRQHandler
 658 CMP2_IRQHandler
 659 FTM3_IRQHandler
 660 DAC1_IRQHandler
 661 ADC1_IRQHandler
 662 I2C2_IRQHandler
 663 CAN0_ORed_Message_buffer_IRQHandler
 664 CAN0_Bus_Off_IRQHandler
 665 CAN0_Error_IRQHandler
 666 CAN0_Tx_Warning_IRQHandler
 667 CAN0_Rx_Warning_IRQHandler
 668 CAN0_Wake_Up_IRQHandler
 669 SDHC_IRQHandler
 670 DefaultISR
 671
 672                 B       .
 673
 674                 ENDP
 675
 676
 677                 ALIGN
 678                 END
 679