tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_dmacdrv.c

   1 /*******************************************************************************
   2 * DISCLAIMER
   3 * This software is supplied by Renesas Electronics Corporation and is only
   4 * intended for use with Renesas products. No other uses are authorized. This
   5 * software is owned by Renesas Electronics Corporation and is protected under
   6 * all applicable laws, including copyright laws.
   7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
   8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
   9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
  10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
  11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
  12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
  13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
  14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
  15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
  16 * Renesas reserves the right, without notice, to make changes to this software
  17 * and to discontinue the availability of this software. By using this software,
  18 * you agree to the additional terms and conditions found by accessing the
  19 * following link:
  20 * http://www.renesas.com/disclaimer
  21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
  22 *******************************************************************************/
  23 /*******************************************************************************
  24 * File Name    : usb1_host_dmacdrv.c
  25 * $Rev: 1116 $
  26 * $Date:: 2014-07-09 16:29:19 +0900#$
  27 * Device(s)    : RZ/A1H
  28 * Tool-Chain   :
  29 * OS           : None
  30 * H/W Platform :
  31 * Description  : RZ/A1H R7S72100 USB Sample Program
  32 * Operation    :
  33 * Limitations  :
  34 *******************************************************************************/
  35
  36
  37 /*******************************************************************************
  38 Includes   <System Includes> , "Project Includes"
  39 *******************************************************************************/
  40 #include "r_typedefs.h"
  41 #include "iodefine.h"
  42 #include "rza_io_regrw.h"
  43 #include "usb1_host_dmacdrv.h"
  44
  45
  46 /*******************************************************************************
  47 Typedef definitions
  48 *******************************************************************************/
  49
  50
  51 /*******************************************************************************
  52 Macro definitions
  53 *******************************************************************************/
  54 #define DMAC_INDEFINE   (255)       /* Macro definition when REQD bit is not used */
  55
  56 /* ==== Request setting information for on-chip peripheral module ==== */
  57 typedef enum dmac_peri_req_reg_type
  58 {
  59     DMAC_REQ_MID,
  60     DMAC_REQ_RID,
  61     DMAC_REQ_AM,
  62     DMAC_REQ_LVL,
  63     DMAC_REQ_REQD
  64 } dmac_peri_req_reg_type_t;
  65
  66
  67 /*******************************************************************************
  68 Imported global variables and functions (from other files)
  69 *******************************************************************************/
  70
  71
  72 /*******************************************************************************
  73 Exported global variables and functions (to be accessed by other files)
  74 *******************************************************************************/
  75
  76
  77 /*******************************************************************************
  78 Private global variables and functions
  79 *******************************************************************************/
  80 /* ==== Prototype declaration ==== */
  81
  82 /* ==== Global variable ==== */
  83 /* On-chip peripheral module request setting table */
  84 static const uint8_t usb1_host_dmac_peri_req_init_table[8][5] =
  85 {
  86   /* MID,RID, AM,LVL,REQD */
  87     { 32,  3,  2,  1,  1},      /* USB_0 channel 0 transmit FIFO empty */
  88     { 32,  3,  2,  1,  0},      /* USB_0 channel 0 receive FIFO full   */
  89     { 33,  3,  2,  1,  1},      /* USB_0 channel 1 transmit FIFO empty */
  90     { 33,  3,  2,  1,  0},      /* USB_0 channel 1 receive FIFO full   */
  91     { 34,  3,  2,  1,  1},      /* USB_1 channel 0 transmit FIFO empty */
  92     { 34,  3,  2,  1,  0},      /* USB_1 channel 0 receive FIFO full   */
  93     { 35,  3,  2,  1,  1},      /* USB_1 channel 1 transmit FIFO empty */
  94     { 35,  3,  2,  1,  0},      /* USB_1 channel 1 receive FIFO full   */
  95 };
  96
  97
  98 /*******************************************************************************
  99 * Function Name: usb1_host_DMAC3_PeriReqInit
 100 * Description  : Sets the register mode for DMA mode and the on-chip peripheral
 101 *              : module request for transfer request for DMAC channel 3.
 102 *              : Executes DMAC initial setting using the DMA information
 103 *              : specified by the argument *trans_info and the enabled/disabled
 104 *              : continuous transfer specified by the argument continuation.
 105 *              : Registers DMAC channel 3 interrupt handler function and sets
 106 *              : the interrupt priority level. Then enables transfer completion
 107 *              : interrupt.
 108 * Arguments    : dmac_transinfo_t * trans_info : Setting information to DMAC
 109 *              :                               : register
 110 *              : uint32_t dmamode      : DMA mode (only for DMAC_MODE_REGISTER)
 111 *              : uint32_t continuation : Set continuous transfer to be valid
 112 *              :                       : after DMA transfer has been completed
 113 *              :         DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
 114 *              :         DMAC_SAMPLE_SINGLE       : Do not execute continuous
 115 *              :                                  : transfer
 116 *              : uint32_t request_factor : Factor for on-chip peripheral module
 117 *              :                         : request
 118 *              :         DMAC_REQ_OSTM0TINT : OSTM_0 compare match
 119 *              :         DMAC_REQ_OSTM1TINT : OSTM_1 compare match
 120 *              :         DMAC_REQ_TGI0A     : MTU2_0 input capture/compare match
 121 *              :                 :
 122 *              : uint32_t req_direction : Setting value of CHCFG_n register
 123 *              :                        : REQD bit
 124 * Return Value : none
 125 *******************************************************************************/
 126 void usb1_host_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
 127                               uint32_t request_factor, uint32_t req_direction)
 128 {
 129     /* ==== Register mode ==== */
 130     if (DMAC_MODE_REGISTER == dmamode)
 131     {
 132         /* ==== Next0 register set ==== */
 133         DMAC3.N0SA_n = trans_info->src_addr;        /* Start address of transfer source      */
 134         DMAC3.N0DA_n = trans_info->dst_addr;        /* Start address of transfer destination */
 135         DMAC3.N0TB_n = trans_info->count;           /* Total transfer byte count             */
 136
 137         /* DAD : Transfer destination address counting direction */
 138         /* SAD : Transfer source address counting direction      */
 139         /* DDS : Transfer destination transfer size              */
 140         /* SDS : Transfer source transfer size                   */
 141         RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 142                             trans_info->daddr_dir,
 143                             DMAC3_CHCFG_n_DAD_SHIFT,
 144                             DMAC3_CHCFG_n_DAD);
 145         RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 146                             trans_info->saddr_dir,
 147                             DMAC3_CHCFG_n_SAD_SHIFT,
 148                             DMAC3_CHCFG_n_SAD);
 149         RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 150                             trans_info->dst_size,
 151                             DMAC3_CHCFG_n_DDS_SHIFT,
 152                             DMAC3_CHCFG_n_DDS);
 153         RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 154                             trans_info->src_size,
 155                             DMAC3_CHCFG_n_SDS_SHIFT,
 156                             DMAC3_CHCFG_n_SDS);
 157
 158         /* DMS  : Register mode                            */
 159         /* RSEL : Select Next0 register set                */
 160         /* SBE  : No discharge of buffer data when aborted */
 161         /* DEM  : No DMA interrupt mask                    */
 162         RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 163                             0,
 164                             DMAC3_CHCFG_n_DMS_SHIFT,
 165                             DMAC3_CHCFG_n_DMS);
 166         RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 167                             0,
 168                             DMAC3_CHCFG_n_RSEL_SHIFT,
 169                             DMAC3_CHCFG_n_RSEL);
 170         RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 171                             0,
 172                             DMAC3_CHCFG_n_SBE_SHIFT,
 173                             DMAC3_CHCFG_n_SBE);
 174         RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 175                             0,
 176                             DMAC3_CHCFG_n_DEM_SHIFT,
 177                             DMAC3_CHCFG_n_DEM);
 178
 179         /* ---- Continuous transfer ---- */
 180         if (DMAC_SAMPLE_CONTINUATION == continuation)
 181         {
 182             /* REN : Execute continuous transfer                         */
 183             /* RSW : Change register set when DMA transfer is completed. */
 184             RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 185                                 1,
 186                                 DMAC3_CHCFG_n_REN_SHIFT,
 187                                 DMAC3_CHCFG_n_REN);
 188             RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 189                                 1,
 190                                 DMAC3_CHCFG_n_RSW_SHIFT,
 191                                 DMAC3_CHCFG_n_RSW);
 192         }
 193         /* ---- Single transfer ---- */
 194         else
 195         {
 196             /* REN : Do not execute continuous transfer                         */
 197             /* RSW : Do not change register set when DMA transfer is completed. */
 198             RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 199                                 0,
 200                                 DMAC3_CHCFG_n_REN_SHIFT,
 201                                 DMAC3_CHCFG_n_REN);
 202             RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 203                                 0,
 204                                 DMAC3_CHCFG_n_RSW_SHIFT,
 205                                 DMAC3_CHCFG_n_RSW);
 206         }
 207
 208         /* TM  : Single transfer                          */
 209         /* SEL : Channel setting                          */
 210         /* HIEN, LOEN : On-chip peripheral module request */
 211         RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 212                             0,
 213                             DMAC3_CHCFG_n_TM_SHIFT,
 214                             DMAC3_CHCFG_n_TM);
 215         RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 216                             3,
 217                             DMAC3_CHCFG_n_SEL_SHIFT,
 218                             DMAC3_CHCFG_n_SEL);
 219         RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 220                             1,
 221                             DMAC3_CHCFG_n_HIEN_SHIFT,
 222                             DMAC3_CHCFG_n_HIEN);
 223         RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 224                             0,
 225                             DMAC3_CHCFG_n_LOEN_SHIFT,
 226                             DMAC3_CHCFG_n_LOEN);
 227
 228         /* ---- Set factor by specified on-chip peripheral module request ---- */
 229         RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 230                             usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
 231                             DMAC3_CHCFG_n_AM_SHIFT,
 232                             DMAC3_CHCFG_n_AM);
 233         RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 234                             usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
 235                             DMAC3_CHCFG_n_LVL_SHIFT,
 236                             DMAC3_CHCFG_n_LVL);
 237         if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
 238         {
 239             RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 240                                 usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
 241                                 DMAC3_CHCFG_n_REQD_SHIFT,
 242                                 DMAC3_CHCFG_n_REQD);
 243         }
 244         else
 245         {
 246             RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
 247                                 req_direction,
 248                                 DMAC3_CHCFG_n_REQD_SHIFT,
 249                                 DMAC3_CHCFG_n_REQD);
 250         }
 251         RZA_IO_RegWrite_32(&DMAC23.DMARS,
 252                             usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
 253                             DMAC23_DMARS_CH3_RID_SHIFT,
 254                             DMAC23_DMARS_CH3_RID);
 255         RZA_IO_RegWrite_32(&DMAC23.DMARS,
 256                             usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
 257                             DMAC23_DMARS_CH3_MID_SHIFT,
 258                             DMAC23_DMARS_CH3_MID);
 259
 260         /* PR : Round robin mode */
 261         RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
 262                             1,
 263                             DMAC07_DCTRL_0_7_PR_SHIFT,
 264                             DMAC07_DCTRL_0_7_PR);
 265     }
 266 }
 267
 268 /*******************************************************************************
 269 * Function Name: usb1_host_DMAC3_Open
 270 * Description  : Enables DMAC channel 3 transfer.
 271 * Arguments    : uint32_t req : DMAC request mode
 272 * Return Value :  0 : Succeeded in enabling DMA transfer
 273 *              : -1 : Failed to enable DMA transfer (due to DMA operation)
 274 *******************************************************************************/
 275 int32_t usb1_host_DMAC3_Open (uint32_t req)
 276 {
 277     int32_t ret;
 278     volatile uint8_t  dummy;
 279
 280     /* Transferable? */
 281     if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
 282                                 DMAC3_CHSTAT_n_EN_SHIFT,
 283                                 DMAC3_CHSTAT_n_EN)) &&
 284         (0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
 285                                 DMAC3_CHSTAT_n_TACT_SHIFT,
 286                                 DMAC3_CHSTAT_n_TACT)))
 287     {
 288         /* Clear Channel Status Register */
 289         RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
 290                             1,
 291                             DMAC3_CHCTRL_n_SWRST_SHIFT,
 292                             DMAC3_CHCTRL_n_SWRST);
 293         dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n,
 294                                 DMAC3_CHCTRL_n_SWRST_SHIFT,
 295                                 DMAC3_CHCTRL_n_SWRST);
 296         /* Enable DMA transfer */
 297         RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
 298                             1,
 299                             DMAC3_CHCTRL_n_SETEN_SHIFT,
 300                             DMAC3_CHCTRL_n_SETEN);
 301
 302         /* ---- Request by software ---- */
 303         if (DMAC_REQ_MODE_SOFT == req)
 304         {
 305             /* DMA transfer Request by software */
 306             RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
 307                                 1,
 308                                 DMAC3_CHCTRL_n_STG_SHIFT,
 309                                 DMAC3_CHCTRL_n_STG);
 310         }
 311
 312         ret = 0;
 313     }
 314     else
 315     {
 316         ret = -1;
 317     }
 318
 319     return ret;
 320 }
 321
 322 /*******************************************************************************
 323 * Function Name: usb1_host_DMAC3_Close
 324 * Description  : Aborts DMAC channel 3 transfer. Returns the remaining transfer
 325 *              : byte count at the time of DMA transfer abort to the argument
 326 *              : *remain.
 327 * Arguments    : uint32_t * remain : Remaining transfer byte count when
 328 *              :                   : DMA transfer is aborted
 329 * Return Value : none
 330 *******************************************************************************/
 331 void usb1_host_DMAC3_Close (uint32_t * remain)
 332 {
 333
 334     /* ==== Abort transfer ==== */
 335     RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
 336                         1,
 337                         DMAC3_CHCTRL_n_CLREN_SHIFT,
 338                         DMAC3_CHCTRL_n_CLREN);
 339
 340     while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
 341                                 DMAC3_CHSTAT_n_TACT_SHIFT,
 342                                 DMAC3_CHSTAT_n_TACT))
 343     {
 344         /* Loop until transfer is aborted */
 345     }
 346
 347     while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
 348                                 DMAC3_CHSTAT_n_EN_SHIFT,
 349                                 DMAC3_CHSTAT_n_EN))
 350     {
 351         /* Loop until 0 is set in EN before checking the remaining transfer byte count */
 352     }
 353     /* ==== Obtain remaining transfer byte count ==== */
 354     *remain = DMAC3.CRTB_n;
 355 }
 356
 357 /*******************************************************************************
 358 * Function Name: usb1_host_DMAC3_Load_Set
 359 * Description  : Sets the transfer source address, transfer destination
 360 *              : address, and total transfer byte count respectively
 361 *              : specified by the argument src_addr, dst_addr, and count to
 362 *              : DMAC channel 3 as DMA transfer information.
 363 *              : Sets the register set selected by the CHCFG_n register
 364 *              : RSEL bit from the Next0 or Next1 register set.
 365 *              : This function should be called when DMA transfer of DMAC
 366 *              : channel 3 is aboted.
 367 * Arguments    : uint32_t src_addr : Transfer source address
 368 *              : uint32_t dst_addr : Transfer destination address
 369 *              : uint32_t count    : Total transfer byte count
 370 * Return Value : none
 371 *******************************************************************************/
 372 void usb1_host_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
 373 {
 374     uint8_t reg_set;
 375
 376     /* Obtain register set in use */
 377     reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
 378                                 DMAC3_CHSTAT_n_SR_SHIFT,
 379                                 DMAC3_CHSTAT_n_SR);
 380
 381     /* ==== Load ==== */
 382     if (0 == reg_set)
 383     {
 384         /* ---- Next0 Register Set ---- */
 385         DMAC3.N0SA_n = src_addr;    /* Start address of transfer source      */
 386         DMAC3.N0DA_n = dst_addr;    /* Start address of transfer destination */
 387         DMAC3.N0TB_n = count;       /* Total transfer byte count             */
 388     }
 389     else
 390     {
 391         /* ---- Next1 Register Set ---- */
 392         DMAC3.N1SA_n = src_addr;    /* Start address of transfer source      */
 393         DMAC3.N1DA_n = dst_addr;    /* Start address of transfer destination */
 394         DMAC3.N1TB_n = count;       /* Total transfer byte count             */
 395      }
 396 }
 397
 398 /*******************************************************************************
 399 * Function Name: usb1_host_DMAC4_PeriReqInit
 400 * Description  : Sets the register mode for DMA mode and the on-chip peripheral
 401 *              : module request for transfer request for DMAC channel 4.
 402 *              : Executes DMAC initial setting using the DMA information
 403 *              : specified by the argument *trans_info and the enabled/disabled
 404 *              : continuous transfer specified by the argument continuation.
 405 *              : Registers DMAC channel 4 interrupt handler function and sets
 406 *              : the interrupt priority level. Then enables transfer completion
 407 *              : interrupt.
 408 * Arguments    : dmac_transinfo_t * trans_info : Setting information to DMAC
 409 *              :                               : register
 410 *              : uint32_t dmamode      : DMA mode (only for DMAC_MODE_REGISTER)
 411 *              : uint32_t continuation : Set continuous transfer to be valid
 412 *              :                       : after DMA transfer has been completed
 413 *              :         DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
 414 *              :         DMAC_SAMPLE_SINGLE       : Do not execute continuous
 415 *              :                                  : transfer
 416 *              : uint32_t request_factor : Factor for on-chip peripheral module
 417 *              :                         : request
 418 *              :         DMAC_REQ_OSTM0TINT : OSTM_0 compare match
 419 *              :         DMAC_REQ_OSTM1TINT : OSTM_1 compare match
 420 *              :         DMAC_REQ_TGI0A     : MTU2_0 input capture/compare match
 421 *              :                 :
 422 *              : uint32_t req_direction : Setting value of CHCFG_n register
 423 *              :                        : REQD bit
 424 * Return Value : none
 425 *******************************************************************************/
 426 void usb1_host_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
 427                               uint32_t request_factor, uint32_t req_direction)
 428 {
 429     /* ==== Register mode ==== */
 430     if (DMAC_MODE_REGISTER == dmamode)
 431     {
 432         /* ==== Next0 register set ==== */
 433         DMAC4.N0SA_n = trans_info->src_addr;        /* Start address of transfer source      */
 434         DMAC4.N0DA_n = trans_info->dst_addr;        /* Start address of transfer destination */
 435         DMAC4.N0TB_n = trans_info->count;           /* Total transfer byte count             */
 436
 437         /* DAD : Transfer destination address counting direction */
 438         /* SAD : Transfer source address counting direction      */
 439         /* DDS : Transfer destination transfer size              */
 440         /* SDS : Transfer source transfer size                   */
 441         RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 442                             trans_info->daddr_dir,
 443                             DMAC4_CHCFG_n_DAD_SHIFT,
 444                             DMAC4_CHCFG_n_DAD);
 445         RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 446                             trans_info->saddr_dir,
 447                             DMAC4_CHCFG_n_SAD_SHIFT,
 448                             DMAC4_CHCFG_n_SAD);
 449         RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 450                             trans_info->dst_size,
 451                             DMAC4_CHCFG_n_DDS_SHIFT,
 452                             DMAC4_CHCFG_n_DDS);
 453         RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 454                             trans_info->src_size,
 455                             DMAC4_CHCFG_n_SDS_SHIFT,
 456                             DMAC4_CHCFG_n_SDS);
 457
 458         /* DMS  : Register mode                            */
 459         /* RSEL : Select Next0 register set                */
 460         /* SBE  : No discharge of buffer data when aborted */
 461         /* DEM  : No DMA interrupt mask                    */
 462         RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 463                             0,
 464                             DMAC4_CHCFG_n_DMS_SHIFT,
 465                             DMAC4_CHCFG_n_DMS);
 466         RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 467                             0,
 468                             DMAC4_CHCFG_n_RSEL_SHIFT,
 469                             DMAC4_CHCFG_n_RSEL);
 470         RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 471                             0,
 472                             DMAC4_CHCFG_n_SBE_SHIFT,
 473                             DMAC4_CHCFG_n_SBE);
 474         RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 475                             0,
 476                             DMAC4_CHCFG_n_DEM_SHIFT,
 477                             DMAC4_CHCFG_n_DEM);
 478
 479         /* ---- Continuous transfer ---- */
 480         if (DMAC_SAMPLE_CONTINUATION == continuation)
 481         {
 482             /* REN : Execute continuous transfer                         */
 483             /* RSW : Change register set when DMA transfer is completed. */
 484             RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 485                                 1,
 486                                 DMAC4_CHCFG_n_REN_SHIFT,
 487                                 DMAC4_CHCFG_n_REN);
 488             RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 489                                 1,
 490                                 DMAC4_CHCFG_n_RSW_SHIFT,
 491                                 DMAC4_CHCFG_n_RSW);
 492         }
 493         /* ---- Single transfer ---- */
 494         else
 495         {
 496             /* REN : Do not execute continuous transfer                         */
 497             /* RSW : Do not change register set when DMA transfer is completed. */
 498             RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 499                                 0,
 500                                 DMAC4_CHCFG_n_REN_SHIFT,
 501                                 DMAC4_CHCFG_n_REN);
 502             RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 503                                 0,
 504                                 DMAC4_CHCFG_n_RSW_SHIFT,
 505                                 DMAC4_CHCFG_n_RSW);
 506         }
 507
 508         /* TM  : Single transfer                          */
 509         /* SEL : Channel setting                          */
 510         /* HIEN, LOEN : On-chip peripheral module request */
 511         RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 512                             0,
 513                             DMAC4_CHCFG_n_TM_SHIFT,
 514                             DMAC4_CHCFG_n_TM);
 515         RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 516                             4,
 517                             DMAC4_CHCFG_n_SEL_SHIFT,
 518                             DMAC4_CHCFG_n_SEL);
 519         RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 520                             1,
 521                             DMAC4_CHCFG_n_HIEN_SHIFT,
 522                             DMAC4_CHCFG_n_HIEN);
 523         RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 524                             0,
 525                             DMAC4_CHCFG_n_LOEN_SHIFT,
 526                             DMAC4_CHCFG_n_LOEN);
 527
 528         /* ---- Set factor by specified on-chip peripheral module request ---- */
 529         RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 530                             usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
 531                             DMAC4_CHCFG_n_AM_SHIFT,
 532                             DMAC4_CHCFG_n_AM);
 533         RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 534                             usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
 535                             DMAC4_CHCFG_n_LVL_SHIFT,
 536                             DMAC4_CHCFG_n_LVL);
 537         if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
 538         {
 539             RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 540                                 usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
 541                                 DMAC4_CHCFG_n_REQD_SHIFT,
 542                                 DMAC4_CHCFG_n_REQD);
 543         }
 544         else
 545         {
 546             RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
 547                                 req_direction,
 548                                 DMAC4_CHCFG_n_REQD_SHIFT,
 549                                 DMAC4_CHCFG_n_REQD);
 550         }
 551         RZA_IO_RegWrite_32(&DMAC45.DMARS,
 552                             usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
 553                             DMAC45_DMARS_CH4_RID_SHIFT,
 554                             DMAC45_DMARS_CH4_RID);
 555         RZA_IO_RegWrite_32(&DMAC45.DMARS,
 556                             usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
 557                             DMAC45_DMARS_CH4_MID_SHIFT,
 558                             DMAC45_DMARS_CH4_MID);
 559
 560         /* PR : Round robin mode */
 561         RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
 562                             1,
 563                             DMAC07_DCTRL_0_7_PR_SHIFT,
 564                             DMAC07_DCTRL_0_7_PR);
 565     }
 566 }
 567
 568 /*******************************************************************************
 569 * Function Name: usb1_host_DMAC4_Open
 570 * Description  : Enables DMAC channel 4 transfer.
 571 * Arguments    : uint32_t req : DMAC request mode
 572 * Return Value :  0 : Succeeded in enabling DMA transfer
 573 *              : -1 : Failed to enable DMA transfer (due to DMA operation)
 574 *******************************************************************************/
 575 int32_t usb1_host_DMAC4_Open (uint32_t req)
 576 {
 577     int32_t ret;
 578     volatile uint8_t  dummy;
 579
 580     /* Transferable? */
 581     if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
 582                                 DMAC4_CHSTAT_n_EN_SHIFT,
 583                                 DMAC4_CHSTAT_n_EN)) &&
 584         (0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
 585                                 DMAC4_CHSTAT_n_TACT_SHIFT,
 586                                 DMAC4_CHSTAT_n_TACT)))
 587     {
 588         /* Clear Channel Status Register */
 589         RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
 590                             1,
 591                             DMAC4_CHCTRL_n_SWRST_SHIFT,
 592                             DMAC4_CHCTRL_n_SWRST);
 593         dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n,
 594                                 DMAC4_CHCTRL_n_SWRST_SHIFT,
 595                                 DMAC4_CHCTRL_n_SWRST);
 596         /* Enable DMA transfer */
 597         RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
 598                             1,
 599                             DMAC4_CHCTRL_n_SETEN_SHIFT,
 600                             DMAC4_CHCTRL_n_SETEN);
 601
 602         /* ---- Request by software ---- */
 603         if (DMAC_REQ_MODE_SOFT == req)
 604         {
 605             /* DMA transfer Request by software */
 606             RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
 607                                 1,
 608                                 DMAC4_CHCTRL_n_STG_SHIFT,
 609                                 DMAC4_CHCTRL_n_STG);
 610         }
 611
 612         ret = 0;
 613     }
 614     else
 615     {
 616         ret = -1;
 617     }
 618
 619     return ret;
 620 }
 621
 622 /*******************************************************************************
 623 * Function Name: usb1_host_DMAC4_Close
 624 * Description  : Aborts DMAC channel 4 transfer. Returns the remaining transfer
 625 *              : byte count at the time of DMA transfer abort to the argument
 626 *              : *remain.
 627 * Arguments    : uint32_t * remain : Remaining transfer byte count when
 628 *              :                   : DMA transfer is aborted
 629 * Return Value : none
 630 *******************************************************************************/
 631 void usb1_host_DMAC4_Close (uint32_t * remain)
 632 {
 633
 634     /* ==== Abort transfer ==== */
 635     RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
 636                         1,
 637                         DMAC4_CHCTRL_n_CLREN_SHIFT,
 638                         DMAC4_CHCTRL_n_CLREN);
 639
 640     while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
 641                                 DMAC4_CHSTAT_n_TACT_SHIFT,
 642                                 DMAC4_CHSTAT_n_TACT))
 643     {
 644         /* Loop until transfer is aborted */
 645     }
 646
 647     while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
 648                                 DMAC4_CHSTAT_n_EN_SHIFT,
 649                                 DMAC4_CHSTAT_n_EN))
 650     {
 651         /* Loop until 0 is set in EN before checking the remaining transfer byte count */
 652     }
 653     /* ==== Obtain remaining transfer byte count ==== */
 654     *remain = DMAC4.CRTB_n;
 655 }
 656
 657 /*******************************************************************************
 658 * Function Name: usb1_host_DMAC4_Load_Set
 659 * Description  : Sets the transfer source address, transfer destination
 660 *              : address, and total transfer byte count respectively
 661 *              : specified by the argument src_addr, dst_addr, and count to
 662 *              : DMAC channel 4 as DMA transfer information.
 663 *              : Sets the register set selected by the CHCFG_n register
 664 *              : RSEL bit from the Next0 or Next1 register set.
 665 *              : This function should be called when DMA transfer of DMAC
 666 *              : channel 4 is aboted.
 667 * Arguments    : uint32_t src_addr : Transfer source address
 668 *              : uint32_t dst_addr : Transfer destination address
 669 *              : uint32_t count    : Total transfer byte count
 670 * Return Value : none
 671 *******************************************************************************/
 672 void usb1_host_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
 673 {
 674     uint8_t reg_set;
 675
 676     /* Obtain register set in use */
 677     reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
 678                                 DMAC4_CHSTAT_n_SR_SHIFT,
 679                                 DMAC4_CHSTAT_n_SR);
 680
 681     /* ==== Load ==== */
 682     if (0 == reg_set)
 683     {
 684         /* ---- Next0 Register Set ---- */
 685         DMAC4.N0SA_n = src_addr;    /* Start address of transfer source      */
 686         DMAC4.N0DA_n = dst_addr;    /* Start address of transfer destination */
 687         DMAC4.N0TB_n = count;       /* Total transfer byte count             */
 688     }
 689     else
 690     {
 691         /* ---- Next1 Register Set ---- */
 692         DMAC4.N1SA_n = src_addr;    /* Start address of transfer source      */
 693         DMAC4.N1DA_n = dst_addr;    /* Start address of transfer destination */
 694         DMAC4.N1TB_n = count;       /* Total transfer byte count             */
 695      }
 696 }
 697
 698 /* End of File */