1 /* Copyright (c) 2010-2011 mbed.org, MIT License
3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
4 * and associated documentation files (the "Software"), to deal in the Software without
5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in all copies or
10 * substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
19 #if defined(TARGET_STM32F4)
22 #include "USBRegs_STM32.h"
25 USBHAL * USBHAL::instance;
27 static volatile int epComplete = 0;
29 static uint32_t bufferEnd = 0;
30 static const uint32_t rxFifoSize = 512;
31 static uint32_t rxFifoCount = 0;
33 static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
35 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
39 USBHAL::USBHAL(void) {
40 NVIC_DisableIRQ(OTG_FS_IRQn);
41 epCallback[0] = &USBHAL::EP1_OUT_callback;
42 epCallback[1] = &USBHAL::EP1_IN_callback;
43 epCallback[2] = &USBHAL::EP2_OUT_callback;
44 epCallback[3] = &USBHAL::EP2_IN_callback;
45 epCallback[4] = &USBHAL::EP3_OUT_callback;
46 epCallback[5] = &USBHAL::EP3_IN_callback;
48 // Enable power and clocking
49 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
51 #if defined(TARGET_STM32F407VG) || defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE)
52 pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
53 pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLDOWN, GPIO_AF10_OTG_FS));
54 pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS));
55 pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
56 pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
58 pin_function(PA_8, STM_PIN_DATA(2, 10));
59 pin_function(PA_9, STM_PIN_DATA(0, 0));
60 pin_function(PA_10, STM_PIN_DATA(2, 10));
61 pin_function(PA_11, STM_PIN_DATA(2, 10));
62 pin_function(PA_12, STM_PIN_DATA(2, 10));
64 // Set ID pin to open drain with pull-up resistor
65 pin_mode(PA_10, OpenDrain);
66 GPIOA->PUPDR &= ~(0x3 << 20);
67 GPIOA->PUPDR |= 1 << 20;
69 // Set VBUS pin to open drain
70 pin_mode(PA_9, OpenDrain);
73 RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
76 OTG_FS->GREGS.GAHBCFG |= (1 << 0);
78 // Turnaround time to maximum value - too small causes packet loss
79 OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
81 // Unmask global interrupts
82 OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
83 (1 << 4) | // RX FIFO not empty
84 (1 << 12); // USB reset
86 OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
87 (1 << 2); // Non-zero-length status OUT handshake
89 OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
90 (1 << 16); // Power Up
93 NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
94 NVIC_SetPriority(OTG_FS_IRQn, 1);
97 USBHAL::~USBHAL(void) {
100 void USBHAL::connect(void) {
101 NVIC_EnableIRQ(OTG_FS_IRQn);
104 void USBHAL::disconnect(void) {
105 NVIC_DisableIRQ(OTG_FS_IRQn);
108 void USBHAL::configureDevice(void) {
112 void USBHAL::unconfigureDevice(void) {
116 void USBHAL::setAddress(uint8_t address) {
117 OTG_FS->DREGS.DCFG |= (address << 4);
121 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
123 uint32_t epIndex = endpoint >> 1;
144 // Generic in or out EP controls
145 uint32_t control = (maxPacket << 0) | // Packet size
146 (1 << 15) | // Active endpoint
147 (type << 18); // Endpoint type
149 if (endpoint & 0x1) { // In Endpoint
150 // Set up the Tx FIFO
151 if (endpoint == EP0IN) {
152 OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
156 OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
159 bufferEnd += maxPacket >> 2;
161 // Set the In EP specific control settings
162 if (endpoint != EP0IN) {
163 control |= (1 << 28); // SD0PID
166 control |= (epIndex << 22) | // TxFIFO index
168 OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
170 // Unmask the interrupt
171 OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
173 else { // Out endpoint
174 // Set the out EP specific control settings
175 control |= (1 << 26); // CNAK
176 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
178 // Unmask the interrupt
179 OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
185 void USBHAL::EP0setup(uint8_t *buffer) {
186 memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
189 void USBHAL::EP0readStage(void) {
192 void USBHAL::EP0read(void) {
195 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
196 uint32_t* buffer32 = (uint32_t *) buffer;
197 uint32_t length = rxFifoCount;
198 for (uint32_t i = 0; i < length; i += 4) {
199 buffer32[i >> 2] = OTG_FS->FIFO[0][0];
206 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
207 endpointWrite(0, buffer, size);
210 void USBHAL::EP0getWriteResult(void) {
213 void USBHAL::EP0stall(void) {
214 // If we stall the out endpoint here then we have problems transferring
215 // and setup requests after the (stalled) get device qualifier requests.
216 // TODO: Find out if this is correct behavior, or whether we are doing
217 // something else wrong
218 stallEndpoint(EP0IN);
219 // stallEndpoint(EP0OUT);
222 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
223 uint32_t epIndex = endpoint >> 1;
224 uint32_t size = (1 << 19) | // 1 packet
225 (maximumSize << 0); // Packet size
226 // if (endpoint == EP0OUT) {
227 size |= (1 << 29); // 1 setup packet
229 OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
230 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
231 (1 << 26); // Clear NAK
233 epComplete &= ~(1 << endpoint);
237 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
238 if (!(epComplete & (1 << endpoint))) {
242 uint32_t* buffer32 = (uint32_t *) buffer;
243 uint32_t length = rxFifoCount;
244 for (uint32_t i = 0; i < length; i += 4) {
245 buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
252 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
253 uint32_t epIndex = endpoint >> 1;
254 OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
255 (size << 0); // Size of packet
256 OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
258 OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
260 while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
262 for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
263 OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
266 epComplete &= ~(1 << endpoint);
271 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
272 if (epComplete & (1 << endpoint)) {
273 epComplete &= ~(1 << endpoint);
280 void USBHAL::stallEndpoint(uint8_t endpoint) {
281 if (endpoint & 0x1) { // In EP
282 OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
286 OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
287 OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
292 void USBHAL::unstallEndpoint(uint8_t endpoint) {
296 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
300 void USBHAL::remoteWakeup(void) {
304 void USBHAL::_usbisr(void) {
309 void USBHAL::usbisr(void) {
310 if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
312 OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
313 OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
314 OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
315 OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
317 OTG_FS->DREGS.DIEPMSK = (1 << 0);
321 // Set the receive FIFO size
322 OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
323 bufferEnd += rxFifoSize >> 2;
325 // Create the endpoints, and wait for setup packets on out EP0
326 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
327 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
328 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
330 OTG_FS->GREGS.GINTSTS = (1 << 12);
333 if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
334 uint32_t status = OTG_FS->GREGS.GRXSTSP;
336 uint32_t endpoint = (status & 0xF) << 1;
337 uint32_t length = (status >> 4) & 0x7FF;
338 uint32_t type = (status >> 17) & 0xF;
340 rxFifoCount = length;
344 for (uint32_t i=0; i<length; i+=4) {
345 setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
353 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
358 if (endpoint == EP0OUT) {
362 epComplete |= (1 << endpoint);
363 if ((instance->*(epCallback[endpoint - 2]))()) {
364 epComplete &= (1 << endpoint);
369 for (uint32_t i=0; i<rxFifoCount; i+=4) {
370 (void) OTG_FS->FIFO[0][0];
372 OTG_FS->GREGS.GINTSTS = (1 << 4);
375 if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
376 // Loop through the in endpoints
377 for (uint32_t i=0; i<4; i++) {
378 if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
380 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
381 // If the Tx FIFO is empty on EP0 we need to send a further
382 // packet, so call EP0in()
386 // Clear the interrupt
387 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
388 // Stop firing Tx empty interrupts
389 // Will get turned on again if another write is called
390 OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
393 // If the transfer is complete
394 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
395 epComplete |= (1 << (1 + (i << 1)));
396 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
400 OTG_FS->GREGS.GINTSTS = (1 << 18);
403 if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
404 SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
405 OTG_FS->GREGS.GINTSTS = (1 << 3);