1 /*******************************************************************************
3 * This software is supplied by Renesas Electronics Corporation and is only
4 * intended for use with Renesas products. No other uses are authorized. This
5 * software is owned by Renesas Electronics Corporation and is protected under
6 * all applicable laws, including copyright laws.
7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16 * Renesas reserves the right, without notice, to make changes to this software
17 * and to discontinue the availability of this software. By using this software,
18 * you agree to the additional terms and conditions found by accessing the
20 * http://www.renesas.com/disclaimer
21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
22 *******************************************************************************/
23 /*******************************************************************************
24 * File Name : usb0_function_dmacdrv.c
26 * $Date:: 2014-07-09 16:29:19 +0900#$
31 * Description : RZ/A1H R7S72100 USB Sample Program
34 *******************************************************************************/
37 /*******************************************************************************
38 Includes <System Includes> , "Project Includes"
39 *******************************************************************************/
41 #include "r_typedefs.h"
43 #include "rza_io_regrw.h"
44 #include "usb0_function_dmacdrv.h"
47 /*******************************************************************************
49 *******************************************************************************/
52 /*******************************************************************************
54 *******************************************************************************/
55 #define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
57 /* ==== Request setting information for on-chip peripheral module ==== */
58 typedef enum dmac_peri_req_reg_type
65 } dmac_peri_req_reg_type_t;
68 /*******************************************************************************
69 Imported global variables and functions (from other files)
70 *******************************************************************************/
73 /*******************************************************************************
74 Exported global variables and functions (to be accessed by other files)
75 *******************************************************************************/
78 /*******************************************************************************
79 Private global variables and functions
80 *******************************************************************************/
81 /* ==== Prototype declaration ==== */
83 /* ==== Global variable ==== */
84 /* On-chip peripheral module request setting table */
85 static const uint8_t usb0_function_dmac_peri_req_init_table[8][5] =
87 /* MID,RID,AM,LVL,REQD */
88 {32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
89 {32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
90 {33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
91 {33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
92 {34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
93 {34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
94 {35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
95 {35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
99 /*******************************************************************************
100 * Function Name: usb0_function_DMAC1_PeriReqInit
101 * Description : Sets the register mode for DMA mode and the on-chip peripheral
102 * : module request for transfer request for DMAC channel 1.
103 * : Executes DMAC initial setting using the DMA information
104 * : specified by the argument *trans_info and the enabled/disabled
105 * : continuous transfer specified by the argument continuation.
106 * : Registers DMAC channel 1 interrupt handler function and sets
107 * : the interrupt priority level. Then enables transfer completion
109 * Arguments : dmac_transinfo_t *trans_info : Setting information to DMAC register
110 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
111 * : uint32_t continuation : Set continuous transfer to be valid
112 * : after DMA transfer has been completed
113 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
114 * : DMAC_SAMPLE_SINGLE : Do not execute continuous transfer
115 * : uint32_t request_factor : Factor for on-chip peripheral module request
116 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
117 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
118 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
120 * : uint32_t req_direction: Setting value of CHCFG_n register REQD bit
121 * Return Value : none
122 *******************************************************************************/
123 void usb0_function_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info,
124 uint32_t dmamode, uint32_t continuation,
125 uint32_t request_factor, uint32_t req_direction)
127 /* ==== Register mode ==== */
128 if (DMAC_MODE_REGISTER == dmamode)
130 /* ==== Next0 register set ==== */
131 DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
132 DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
133 DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */
135 /* DAD : Transfer destination address counting direction */
136 /* SAD : Transfer source address counting direction */
137 /* DDS : Transfer destination transfer size */
138 /* SDS : Transfer source transfer size */
139 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
140 trans_info->daddr_dir,
141 DMAC1_CHCFG_n_DAD_SHIFT,
143 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
144 trans_info->saddr_dir,
145 DMAC1_CHCFG_n_SAD_SHIFT,
147 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
148 trans_info->dst_size,
149 DMAC1_CHCFG_n_DDS_SHIFT,
151 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
152 trans_info->src_size,
153 DMAC1_CHCFG_n_SDS_SHIFT,
156 /* DMS : Register mode */
157 /* RSEL : Select Next0 register set */
158 /* SBE : No discharge of buffer data when aborted */
159 /* DEM : No DMA interrupt mask */
160 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
162 DMAC1_CHCFG_n_DMS_SHIFT,
164 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
166 DMAC1_CHCFG_n_RSEL_SHIFT,
168 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
170 DMAC1_CHCFG_n_SBE_SHIFT,
172 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
174 DMAC1_CHCFG_n_DEM_SHIFT,
177 /* ---- Continuous transfer ---- */
178 if (DMAC_SAMPLE_CONTINUATION == continuation)
180 /* REN : Execute continuous transfer */
181 /* RSW : Change register set when DMA transfer is completed. */
182 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
184 DMAC1_CHCFG_n_REN_SHIFT,
186 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
188 DMAC1_CHCFG_n_RSW_SHIFT,
191 /* ---- Single transfer ---- */
194 /* REN : Do not execute continuous transfer */
195 /* RSW : Do not change register set when DMA transfer is completed. */
196 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
198 DMAC1_CHCFG_n_REN_SHIFT,
200 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
202 DMAC1_CHCFG_n_RSW_SHIFT,
206 /* TM : Single transfer */
207 /* SEL : Channel setting */
208 /* HIEN, LOEN : On-chip peripheral module request */
209 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
211 DMAC1_CHCFG_n_TM_SHIFT,
213 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
215 DMAC1_CHCFG_n_SEL_SHIFT,
217 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
219 DMAC1_CHCFG_n_HIEN_SHIFT,
221 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
223 DMAC1_CHCFG_n_LOEN_SHIFT,
226 /* ---- Set factor by specified on-chip peripheral module request ---- */
227 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
228 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
229 DMAC1_CHCFG_n_AM_SHIFT,
231 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
232 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
233 DMAC1_CHCFG_n_LVL_SHIFT,
236 if (usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
238 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
239 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
240 DMAC1_CHCFG_n_REQD_SHIFT,
245 RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
247 DMAC1_CHCFG_n_REQD_SHIFT,
251 RZA_IO_RegWrite_32(&DMAC01.DMARS,
252 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
253 DMAC01_DMARS_CH1_RID_SHIFT,
254 DMAC01_DMARS_CH1_RID);
255 RZA_IO_RegWrite_32(&DMAC01.DMARS,
256 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
257 DMAC01_DMARS_CH1_MID_SHIFT,
258 DMAC01_DMARS_CH1_MID);
260 /* PR : Round robin mode */
261 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
263 DMAC07_DCTRL_0_7_PR_SHIFT,
264 DMAC07_DCTRL_0_7_PR);
268 /*******************************************************************************
269 * Function Name: usb0_function_DMAC1_Open
270 * Description : Enables DMAC channel 1 transfer.
271 * Arguments : uint32_t req : DMAC request mode
272 * Return Value : 0 : Succeeded in enabling DMA transfer
273 * : -1 : Failed to enable DMA transfer (due to DMA operation)
274 *******************************************************************************/
275 int32_t usb0_function_DMAC1_Open (uint32_t req)
278 volatile uint8_t dummy;
281 if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
282 DMAC1_CHSTAT_n_EN_SHIFT,
283 DMAC1_CHSTAT_n_EN)) &&
284 (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
285 DMAC1_CHSTAT_n_TACT_SHIFT,
286 DMAC1_CHSTAT_n_TACT)))
288 /* Clear Channel Status Register */
289 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
291 DMAC1_CHCTRL_n_SWRST_SHIFT,
292 DMAC1_CHCTRL_n_SWRST);
293 dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n,
294 DMAC1_CHCTRL_n_SWRST_SHIFT,
295 DMAC1_CHCTRL_n_SWRST);
296 /* Enable DMA transfer */
297 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
299 DMAC1_CHCTRL_n_SETEN_SHIFT,
300 DMAC1_CHCTRL_n_SETEN);
302 /* ---- Request by software ---- */
303 if (DMAC_REQ_MODE_SOFT == req)
305 /* DMA transfer Request by software */
306 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
308 DMAC1_CHCTRL_n_STG_SHIFT,
322 /*******************************************************************************
323 * Function Name: usb0_function_DMAC1_Close
324 * Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer
325 * : byte count at the time of DMA transfer abort to the argument
327 * Arguments : uint32_t * remain : Remaining transfer byte count when
328 * : : DMA transfer is aborted
329 * Return Value : none
330 *******************************************************************************/
331 void usb0_function_DMAC1_Close (uint32_t * remain)
334 /* ==== Abort transfer ==== */
335 RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
337 DMAC1_CHCTRL_n_CLREN_SHIFT,
338 DMAC1_CHCTRL_n_CLREN);
340 while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
341 DMAC1_CHSTAT_n_TACT_SHIFT,
342 DMAC1_CHSTAT_n_TACT))
344 /* Loop until transfer is aborted */
347 while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
348 DMAC1_CHSTAT_n_EN_SHIFT,
351 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
353 /* ==== Obtain remaining transfer byte count ==== */
354 *remain = DMAC1.CRTB_n;
357 /*******************************************************************************
358 * Function Name: usb0_function_DMAC1_Load_Set
359 * Description : Sets the transfer source address, transfer destination
360 * : address, and total transfer byte count respectively
361 * : specified by the argument src_addr, dst_addr, and count to
362 * : DMAC channel 1 as DMA transfer information.
363 * : Sets the register set selected by the CHCFG_n register
364 * : RSEL bit from the Next0 or Next1 register set.
365 * : This function should be called when DMA transfer of DMAC
366 * : channel 1 is aboted.
367 * Arguments : uint32_t src_addr : Transfer source address
368 * : uint32_t dst_addr : Transfer destination address
369 * : uint32_t count : Total transfer byte count
370 * Return Value : none
371 *******************************************************************************/
372 void usb0_function_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
376 /* Obtain register set in use */
377 reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
378 DMAC1_CHSTAT_n_SR_SHIFT,
384 /* ---- Next0 Register Set ---- */
385 DMAC1.N0SA_n = src_addr; /* Start address of transfer source */
386 DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */
387 DMAC1.N0TB_n = count; /* Total transfer byte count */
391 /* ---- Next1 Register Set ---- */
392 DMAC1.N1SA_n = src_addr; /* Start address of transfer source */
393 DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */
394 DMAC1.N1TB_n = count; /* Total transfer byte count */
398 /*******************************************************************************
399 * Function Name: usb0_function_DMAC2_PeriReqInit
400 * Description : Sets the register mode for DMA mode and the on-chip peripheral
401 * : module request for transfer request for DMAC channel 2.
402 * : Executes DMAC initial setting using the DMA information
403 * : specified by the argument *trans_info and the enabled/disabled
404 * : continuous transfer specified by the argument continuation.
405 * : Registers DMAC channel 2 interrupt handler function and sets
406 * : the interrupt priority level. Then enables transfer completion
408 * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
410 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
411 * : uint32_t continuation : Set continuous transfer to be valid
412 * : : after DMA transfer has been completed
413 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
414 * : DMAC_SAMPLE_SINGLE : Do not execute continuous
416 * : uint32_t request_factor : Factor for on-chip peripheral module
418 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
419 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
420 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
422 * : uint32_t req_direction : Setting value of CHCFG_n register
424 *******************************************************************************/
425 void usb0_function_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info,
426 uint32_t dmamode, uint32_t continuation,
427 uint32_t request_factor, uint32_t req_direction)
429 /* ==== Register mode ==== */
430 if (DMAC_MODE_REGISTER == dmamode)
432 /* ==== Next0 register set ==== */
433 DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
434 DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
435 DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */
437 /* DAD : Transfer destination address counting direction */
438 /* SAD : Transfer source address counting direction */
439 /* DDS : Transfer destination transfer size */
440 /* SDS : Transfer source transfer size */
441 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
442 trans_info->daddr_dir,
443 DMAC2_CHCFG_n_DAD_SHIFT,
445 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
446 trans_info->saddr_dir,
447 DMAC2_CHCFG_n_SAD_SHIFT,
449 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
450 trans_info->dst_size,
451 DMAC2_CHCFG_n_DDS_SHIFT,
453 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
454 trans_info->src_size,
455 DMAC2_CHCFG_n_SDS_SHIFT,
458 /* DMS : Register mode */
459 /* RSEL : Select Next0 register set */
460 /* SBE : No discharge of buffer data when aborted */
461 /* DEM : No DMA interrupt mask */
462 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
464 DMAC2_CHCFG_n_DMS_SHIFT,
466 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
468 DMAC2_CHCFG_n_RSEL_SHIFT,
470 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
472 DMAC2_CHCFG_n_SBE_SHIFT,
474 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
476 DMAC2_CHCFG_n_DEM_SHIFT,
479 /* ---- Continuous transfer ---- */
480 if (DMAC_SAMPLE_CONTINUATION == continuation)
482 /* REN : Execute continuous transfer */
483 /* RSW : Change register set when DMA transfer is completed. */
484 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
486 DMAC2_CHCFG_n_REN_SHIFT,
488 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
490 DMAC2_CHCFG_n_RSW_SHIFT,
493 /* ---- Single transfer ---- */
496 /* REN : Do not execute continuous transfer */
497 /* RSW : Do not change register set when DMA transfer is completed. */
498 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
500 DMAC2_CHCFG_n_REN_SHIFT,
502 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
504 DMAC2_CHCFG_n_RSW_SHIFT,
508 /* TM : Single transfer */
509 /* SEL : Channel setting */
510 /* HIEN, LOEN : On-chip peripheral module request */
511 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
513 DMAC2_CHCFG_n_TM_SHIFT,
515 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
517 DMAC2_CHCFG_n_SEL_SHIFT,
519 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
521 DMAC2_CHCFG_n_HIEN_SHIFT,
523 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
525 DMAC2_CHCFG_n_LOEN_SHIFT,
528 /* ---- Set factor by specified on-chip peripheral module request ---- */
529 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
530 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
531 DMAC2_CHCFG_n_AM_SHIFT,
533 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
534 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
535 DMAC2_CHCFG_n_LVL_SHIFT,
537 if (usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
539 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
540 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
541 DMAC2_CHCFG_n_REQD_SHIFT,
546 RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
548 DMAC2_CHCFG_n_REQD_SHIFT,
551 RZA_IO_RegWrite_32(&DMAC23.DMARS,
552 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
553 DMAC23_DMARS_CH2_RID_SHIFT,
554 DMAC23_DMARS_CH2_RID);
555 RZA_IO_RegWrite_32(&DMAC23.DMARS,
556 usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
557 DMAC23_DMARS_CH2_MID_SHIFT,
558 DMAC23_DMARS_CH2_MID);
560 /* PR : Round robin mode */
561 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
563 DMAC07_DCTRL_0_7_PR_SHIFT,
564 DMAC07_DCTRL_0_7_PR);
568 /*******************************************************************************
569 * Function Name: usb0_function_DMAC2_Open
570 * Description : Enables DMAC channel 2 transfer.
571 * Arguments : uint32_t req : DMAC request mode
572 * Return Value : 0 : Succeeded in enabling DMA transfer
573 * : -1 : Failed to enable DMA transfer (due to DMA operation)
574 *******************************************************************************/
575 int32_t usb0_function_DMAC2_Open (uint32_t req)
578 volatile uint8_t dummy;
581 if ((0 == RZA_IO_RegRead_32(&DMAC.CHSTAT_2,
582 DMAC2_CHSTAT_n_EN_SHIFT,
583 DMAC2_CHSTAT_n_EN)) &&
584 (0 == RZA_IO_RegRead_32(&DMAC.CHSTAT_2,
585 DMAC2_CHSTAT_n_TACT_SHIFT,
586 DMAC2_CHSTAT_n_TACT)))
588 /* Clear Channel Status Register */
589 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
591 DMAC2_CHCTRL_n_SWRST_SHIFT,
592 DMAC2_CHCTRL_n_SWRST);
593 dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n,
594 DMAC2_CHCTRL_n_SWRST_SHIFT,
595 DMAC2_CHCTRL_n_SWRST);
596 /* Enable DMA transfer */
597 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
599 DMAC2_CHCTRL_n_SETEN_SHIFT,
600 DMAC2_CHCTRL_n_SETEN);
602 /* ---- Request by software ---- */
603 if (DMAC_REQ_MODE_SOFT == req)
605 /* DMA transfer Request by software */
606 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
608 DMAC2_CHCTRL_n_STG_SHIFT,
622 /*******************************************************************************
623 * Function Name: usb0_function_DMAC2_Close
624 * Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer
625 * : byte count at the time of DMA transfer abort to the argument
627 * Arguments : uint32_t * remain : Remaining transfer byte count when
628 * : : DMA transfer is aborted
629 * Return Value : none
630 *******************************************************************************/
631 void usb0_function_DMAC2_Close (uint32_t * remain)
634 /* ==== Abort transfer ==== */
635 RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
637 DMAC2_CHCTRL_n_CLREN_SHIFT,
638 DMAC2_CHCTRL_n_CLREN);
640 while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
641 DMAC2_CHSTAT_n_TACT_SHIFT,
642 DMAC2_CHSTAT_n_TACT))
644 /* Loop until transfer is aborted */
647 while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
648 DMAC2_CHSTAT_n_EN_SHIFT,
651 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
653 /* ==== Obtain remaining transfer byte count ==== */
654 *remain = DMAC2.CRTB_n;
657 /*******************************************************************************
658 * Function Name: usb0_function_DMAC2_Load_Set
659 * Description : Sets the transfer source address, transfer destination
660 * : address, and total transfer byte count respectively
661 * : specified by the argument src_addr, dst_addr, and count to
662 * : DMAC channel 2 as DMA transfer information.
663 * : Sets the register set selected by the CHCFG_n register
664 * : RSEL bit from the Next0 or Next1 register set.
665 * : This function should be called when DMA transfer of DMAC
666 * : channel 2 is aboted.
667 * Arguments : uint32_t src_addr : Transfer source address
668 * : uint32_t dst_addr : Transfer destination address
669 * : uint32_t count : Total transfer byte count
670 * Return Value : none
671 *******************************************************************************/
672 void usb0_function_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
676 /* Obtain register set in use */
677 reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
678 DMAC2_CHSTAT_n_SR_SHIFT,
684 /* ---- Next0 Register Set ---- */
685 DMAC2.N0SA_n = src_addr; /* Start address of transfer source */
686 DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */
687 DMAC2.N0TB_n = count; /* Total transfer byte count */
691 /* ---- Next1 Register Set ---- */
692 DMAC2.N1SA_n = src_addr; /* Start address of transfer source */
693 DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */
694 DMAC2.N1TB_n = count; /* Total transfer byte count */