1 /* mbed Microcontroller Library
2 * Copyright (c) 2006-2013 ARM Limited
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
17 #include "us_ticker_api.h"
18 #include "PeripheralNames.h"
19 #include "ostm_iodefine.h"
21 #include "RZ_A1_Init.h"
24 #define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn)
25 #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
27 #define US_TICKER_CLOCK_US_DEV (1000000)
29 int us_ticker_inited = 0;
30 static double count_clock = 0;
31 static uint32_t last_read = 0;
32 static uint32_t wrap_arround = 0;
33 static uint64_t ticker_us_last64 = 0;
35 void us_ticker_interrupt(void) {
36 us_ticker_irq_handler();
39 void us_ticker_init(void) {
40 if (us_ticker_inited) return;
43 /* set Counter Clock(us) */
44 if (false == RZ_A1_IsClockMode0()) {
45 count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
47 count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
50 /* Power Control for Peripherals */
51 CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */
54 OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */
55 OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */
57 OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */
60 InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt);
61 GIC_SetPriority(US_TICKER_TIMER_IRQn, 5);
62 GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
65 static uint64_t ticker_read_counter64(void) {
69 if (!us_ticker_inited)
74 if (last_read > cnt_val) {
78 cnt_val64 = ((uint64_t)wrap_arround << 32) + cnt_val;
83 uint32_t us_ticker_read() {
88 check_irq_masked = __disable_irq();
90 cnt_val64 = ticker_read_counter64();
91 us_val64 = (cnt_val64 / count_clock);
92 ticker_us_last64 = us_val64;
94 if (!check_irq_masked) {
99 return (uint32_t)us_val64;
102 void us_ticker_set_interrupt(timestamp_t timestamp) {
104 uint64_t timestamp64;
105 uint64_t set_cmp_val64;
106 volatile uint32_t set_cmp_val;
107 uint64_t count_val_64;
109 /* calc compare mach timestamp */
110 timestamp64 = (ticker_us_last64 & 0xFFFFFFFF00000000) + timestamp;
111 if (timestamp < (ticker_us_last64 & 0x00000000FFFFFFFF)) {
112 /* This event is wrap arround */
113 timestamp64 += 0x100000000;
116 /* calc compare mach timestamp */
117 set_cmp_val64 = timestamp64 * count_clock;
118 set_cmp_val = (uint32_t)(set_cmp_val64 & 0x00000000FFFFFFFF);
119 count_val_64 = ticker_read_counter64();
120 if (set_cmp_val64 <= (count_val_64 + 500)) {
121 GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
122 GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
125 OSTM1CMP = set_cmp_val;
126 GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
129 void us_ticker_disable_interrupt(void) {
130 GIC_DisableIRQ(US_TICKER_TIMER_IRQn);
133 void us_ticker_clear_interrupt(void) {
134 GIC_ClearPendingIRQ(US_TICKER_TIMER_IRQn);