1 /*******************************************************************************
2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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22 * Except as contained in this notice, the name of Maxim Integrated
23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
24 * Products, Inc. Branding Policy.
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29 * property whatsoever. Maxim Integrated Products, Inc. retains all
31 *******************************************************************************
34 #include "mbed_assert.h"
37 #include "i2cm_regs.h"
38 #include "clkman_regs.h"
39 #include "ioman_regs.h"
40 #include "PeripheralPins.h"
42 #define I2C_SLAVE_ADDR_READ_BIT 0x0001
44 #ifndef MXC_I2CM_TX_TIMEOUT
45 #define MXC_I2CM_TX_TIMEOUT 0x5000
48 #ifndef MXC_I2CM_RX_TIMEOUT
49 #define MXC_I2CM_RX_TIMEOUT 0x5000
54 MXC_E_I2CM_SPEED_100KHZ = 0,
56 MXC_E_I2CM_SPEED_400KHZ,
61 /* Clock divider lookup table */
62 static const uint32_t clk_div_table[3][8] = {
63 /* MXC_E_I2CM_SPEED_100KHZ */
65 /* 0: */ 0, /* not supported */
66 /* 1: 6MHz */ (( 3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | ( 7 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
67 /* 2: 8MHz */ (( 4 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (10 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 48 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
68 /* 3: 12MHz */ (( 6 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (17 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 72 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
69 /* 4: 16MHz */ (( 8 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 96 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
70 /* 5: */ 0, /* not supported */
71 /* 6: */ 0, /* not supported */
72 /* 7: 24MHz */ ((12 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (38 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (144 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
74 /* MXC_E_I2CM_SPEED_400KHZ */
76 /* 0: */ 0, /* not supported */
77 /* 1: */ 0, /* not supported */
78 /* 2: */ 0, /* not supported */
79 /* 3: 12MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (1 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (18 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
80 /* 4: 16MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (2 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
81 /* 5: */ 0, /* not supported */
82 /* 6: */ 0, /* not supported */
83 /* 7: 24MHz */ ((3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (5 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
85 /* MXC_E_I2CM_SPEED_1MHZ */
87 /* 0: */ 0, /* not supported */
88 /* 1: */ 0, /* not supported */
89 /* 2: */ 0, /* not supported */
90 /* 3: */ 0, /* not supported */
91 /* 4: */ 0, /* not supported */
92 /* 5: */ 0, /* not supported */
93 /* 6: */ 0, /* not supported */
94 /* 7: 24MHz */ ((1 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (0 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (14 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
98 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
100 // determine the I2C to use
101 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
102 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
103 mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl);
104 MBED_ASSERT((int)i2c != NC);
107 obj->txfifo = (uint16_t*)MXC_I2CM_GET_BASE_TX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c));
108 obj->rxfifo = (uint16_t*)MXC_I2CM_GET_BASE_RX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c));
109 obj->start_pending = 0;
110 obj->stop_pending = 0;
112 // configure the pins
113 pinmap_pinout(sda, PinMap_I2C_SDA);
114 pinmap_pinout(scl, PinMap_I2C_SCL);
117 MXC_CLKMAN->clk_ctrl_6_i2cm = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
120 i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
123 // set default frequency at 100k
124 i2c_frequency(obj, 100000);
126 // set timeout to 255 ms and turn on the auto-stop option
127 i2c->timeout = (0xFF << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS) | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN;
129 // enable tx_fifo and rx_fifo
130 i2c->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN);
133 void i2c_frequency(i2c_t *obj, int hz)
135 // compute clock array index
136 int clki = ((SystemCoreClock + 1500000) / 3000000) - 1;
138 // get clock divider settings from lookup table
139 if ((hz < 400000) && (clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki] > 0)) {
140 obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki];
141 } else if ((hz < 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki] > 0)) {
142 obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki];
143 } else if ((hz >= 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki] > 0)) {
144 obj->i2c->hs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki];
148 static int write_tx_fifo(i2c_t *obj, const uint16_t data)
150 int timeout = MXC_I2CM_TX_TIMEOUT;
152 while (*obj->txfifo) {
153 uint32_t intfl = obj->i2c->intfl;
154 if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
155 return I2C_ERROR_NO_SLAVE;
157 if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
158 return I2C_ERROR_BUS_BUSY;
167 static int wait_tx_in_progress(i2c_t *obj)
169 int timeout = MXC_I2CM_TX_TIMEOUT;
171 while ((obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout);
173 uint32_t intfl = obj->i2c->intfl;
175 if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
177 return I2C_ERROR_NO_SLAVE;
180 if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
182 return I2C_ERROR_BUS_BUSY;
188 int i2c_start(i2c_t *obj)
190 obj->start_pending = 1;
194 int i2c_stop(i2c_t *obj)
196 obj->start_pending = 0;
197 write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP);
199 return wait_tx_in_progress(obj);
202 void i2c_reset(i2c_t *obj)
204 obj->i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
205 obj->i2c->intfl = 0x3FF; // clear all interrupts
206 obj->i2c->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN;
207 obj->start_pending = 0;
210 int i2c_byte_write(i2c_t *obj, int data)
214 // clear all interrupts
215 obj->i2c->intfl = 0x3FF;
217 if (obj->start_pending) {
218 obj->start_pending = 0;
219 data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_START;
221 data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_TXDATA_ACK;
224 if ((err = write_tx_fifo(obj, data)) != 0) {
228 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
233 int i2c_byte_read(i2c_t *obj, int last)
238 // clear all interrupts
239 obj->i2c->intfl = 0x3FF;
242 fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_NACK;
244 fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT;
247 if ((err = write_tx_fifo(obj, fifo_value)) != 0) {
251 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
253 int timeout = MXC_I2CM_RX_TIMEOUT;
254 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
255 (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
256 if ((--timeout < 0) || !(obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
261 if (obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) {
262 obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
269 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
274 if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
278 // clear all interrupts
279 obj->i2c->intfl = 0x3FF;
281 // write the address to the fifo
282 if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address))) != 0) { // start + addr (write)
285 obj->start_pending = 0;
287 // start the transaction
288 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
290 // load as much of the cmd into the FIFO as possible
291 for (i = 0; i < length; i++) {
292 if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != 0) { // cmd (expect ACK)
293 retval = (retval ? retval : err);
299 obj->stop_pending = 0;
300 if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
301 retval = (retval ? retval : err);
304 if ((err = wait_tx_in_progress(obj)) != 0) {
305 retval = (retval ? retval : err);
308 obj->stop_pending = 1;
309 int timeout = MXC_I2CM_TX_TIMEOUT;
310 // Wait for TX fifo to be empty
311 while(!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY) && timeout--) {}
321 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
327 if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
331 // clear all interrupts
332 obj->i2c->intfl = 0x3FF;
334 // start + addr (read)
335 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address | I2C_SLAVE_ADDR_READ_BIT))) != 0) {
338 obj->start_pending = 0;
341 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != 0) {
348 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i - 2)))) != 0) {
353 // start the transaction
354 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
356 if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK)) != 0) { // NACK last data byte
361 if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
366 timeout = MXC_I2CM_RX_TIMEOUT;
369 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
370 (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
371 if ((--timeout < 0) || !(obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
377 timeout = MXC_I2CM_RX_TIMEOUT;
379 obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
381 uint16_t temp = *obj->rxfifo;
383 if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) {
386 data[i++] = (uint8_t) temp;
392 obj->stop_pending = 0;
393 if ((err = wait_tx_in_progress(obj)) != 0) {
394 retval = (retval ? retval : err);
397 obj->stop_pending = 1;