2 ** ###################################################################
3 ** Version: rev. 1.0, 2014-05-14
7 ** Chip specific module features.
9 ** Copyright: 2014 Freescale Semiconductor, Inc.
10 ** All rights reserved.
12 ** Redistribution and use in source and binary forms, with or without modification,
13 ** are permitted provided that the following conditions are met:
15 ** o Redistributions of source code must retain the above copyright notice, this list
16 ** of conditions and the following disclaimer.
18 ** o Redistributions in binary form must reproduce the above copyright notice, this
19 ** list of conditions and the following disclaimer in the documentation and/or
20 ** other materials provided with the distribution.
22 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
23 ** contributors may be used to endorse or promote products derived from this
24 ** software without specific prior written permission.
26 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
27 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
30 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
33 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 ** http: www.freescale.com
38 ** mail: support@freescale.com
41 ** - rev. 1.0 (2014-05-14)
44 ** ###################################################################
47 #if !defined(__FSL_OSC_FEATURES_H__)
48 #define __FSL_OSC_FEATURES_H__
50 #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
51 defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \
52 defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \
53 defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \
54 defined(CPU_MK22FN512VLL12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
55 defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
56 defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \
57 defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \
58 defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \
59 defined(CPU_MKV31F512VLL12)
60 /* @brief Has OSC1 external oscillator. */
61 #define FSL_FEATURE_OSC_HAS_OSC1 (0)
62 /* @brief Has OSC0 external oscillator. */
63 #define FSL_FEATURE_OSC_HAS_OSC0 (0)
64 /* @brief Has OSC external oscillator (without index). */
65 #define FSL_FEATURE_OSC_HAS_OSC (1)
66 /* @brief Number of OSC external oscillators. */
67 #define FSL_FEATURE_OSC_OSC_COUNT (1)
68 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
69 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1)
70 #elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
71 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
72 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
73 defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
74 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
75 defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
76 defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
77 defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || \
78 defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
79 defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || \
80 defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || \
81 defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || \
82 defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || \
83 defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || \
84 defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || \
85 defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || \
86 defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
87 defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || \
88 defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || \
89 defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || \
90 defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || \
91 defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || \
92 defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || \
93 defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || \
94 defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
95 /* @brief Has OSC1 external oscillator. */
96 #define FSL_FEATURE_OSC_HAS_OSC1 (0)
97 /* @brief Has OSC0 external oscillator. */
98 #define FSL_FEATURE_OSC_HAS_OSC0 (1)
99 /* @brief Has OSC external oscillator (without index). */
100 #define FSL_FEATURE_OSC_HAS_OSC (0)
101 /* @brief Number of OSC external oscillators. */
102 #define FSL_FEATURE_OSC_OSC_COUNT (1)
103 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
104 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
105 #elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || \
106 defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \
107 defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
108 defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
109 /* @brief Has OSC1 external oscillator. */
110 #define FSL_FEATURE_OSC_HAS_OSC1 (0)
111 /* @brief Has OSC0 external oscillator. */
112 #define FSL_FEATURE_OSC_HAS_OSC0 (0)
113 /* @brief Has OSC external oscillator (without index). */
114 #define FSL_FEATURE_OSC_HAS_OSC (1)
115 /* @brief Number of OSC external oscillators. */
116 #define FSL_FEATURE_OSC_OSC_COUNT (1)
117 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
118 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
119 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
120 defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
121 /* @brief Has OSC1 external oscillator. */
122 #define FSL_FEATURE_OSC_HAS_OSC1 (1)
123 /* @brief Has OSC0 external oscillator. */
124 #define FSL_FEATURE_OSC_HAS_OSC0 (1)
125 /* @brief Has OSC external oscillator (without index). */
126 #define FSL_FEATURE_OSC_HAS_OSC (0)
127 /* @brief Number of OSC external oscillators. */
128 #define FSL_FEATURE_OSC_OSC_COUNT (2)
129 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
130 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
131 #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \
132 defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4)
133 /* @brief Has OSC1 external oscillator. */
134 #define FSL_FEATURE_OSC_HAS_OSC1 (0)
135 /* @brief Has OSC0 external oscillator. */
136 #define FSL_FEATURE_OSC_HAS_OSC0 (0)
137 /* @brief Has OSC external oscillator (without index). */
138 #define FSL_FEATURE_OSC_HAS_OSC (0)
139 /* @brief Number of OSC external oscillators. */
140 #define FSL_FEATURE_OSC_OSC_COUNT (0)
141 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
142 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
143 #elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \
144 defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \
145 defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \
146 defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \
147 defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15)
148 /* @brief Has OSC1 external oscillator. */
149 #define FSL_FEATURE_OSC_HAS_OSC1 (0)
150 /* @brief Has OSC0 external oscillator. */
151 #define FSL_FEATURE_OSC_HAS_OSC0 (0)
152 /* @brief Has OSC external oscillator (without index). */
153 #define FSL_FEATURE_OSC_HAS_OSC (0)
154 /* @brief Number of OSC external oscillators. */
155 #define FSL_FEATURE_OSC_OSC_COUNT (0)
156 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
157 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1)
159 #error "No valid CPU defined!"
162 #endif /* __FSL_OSC_FEATURES_H__ */
164 /*******************************************************************************
166 ******************************************************************************/