2 ******************************************************************************
3 * @file system_stm32f4xx.c
4 * @author MCD Application Team
7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
9 * This file provides two functions and one global variable to be called from
11 * - SystemInit(): This function is called at startup just after reset and
12 * before branch to main program. This call is made inside
13 * the "startup_stm32f4xx.s" file.
15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
16 * by the user application to setup the SysTick
17 * timer or configure other parameters.
19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
20 * be called whenever the core clock is changed
21 * during program execution.
23 * This file configures the system clock as follows:
24 *-----------------------------------------------------------------------------
25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
26 * | (external 8 MHz clock) | (internal 16 MHz)
28 * | (external 8 MHz xtal) |
29 *-----------------------------------------------------------------------------
30 * SYSCLK(MHz) | 96 | 96
31 *-----------------------------------------------------------------------------
32 * AHBCLK (MHz) | 96 | 96
33 *-----------------------------------------------------------------------------
34 * APB1CLK (MHz) | 48 | 48
35 *-----------------------------------------------------------------------------
36 * APB2CLK (MHz) | 96 | 96
37 *-----------------------------------------------------------------------------
38 * USB capable (48 MHz precise clock) | YES | NO
39 *-----------------------------------------------------------------------------
40 ******************************************************************************
43 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
45 * Redistribution and use in source and binary forms, with or without modification,
46 * are permitted provided that the following conditions are met:
47 * 1. Redistributions of source code must retain the above copyright notice,
48 * this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright notice,
50 * this list of conditions and the following disclaimer in the documentation
51 * and/or other materials provided with the distribution.
52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
53 * may be used to endorse or promote products derived from this software
54 * without specific prior written permission.
56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 ******************************************************************************
74 /** @addtogroup stm32f4xx_system
78 /** @addtogroup STM32F4xx_System_Private_Includes
83 #include "stm32f4xx.h"
86 #if !defined (HSE_VALUE)
87 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
88 #endif /* HSE_VALUE */
90 #if !defined (HSI_VALUE)
91 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
92 #endif /* HSI_VALUE */
98 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
106 /** @addtogroup STM32F4xx_System_Private_Defines
110 /************************* Miscellaneous Configuration ************************/
111 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
112 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
113 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
114 /* #define DATA_IN_ExtSRAM */
115 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
117 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
118 /* #define DATA_IN_ExtSDRAM */
119 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
121 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
122 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
123 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
125 /*!< Uncomment the following line if you need to relocate your vector Table in
127 /* #define VECT_TAB_SRAM */
128 #ifndef VECT_TAB_OFFSET
129 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
130 This value must be a multiple of 0x200. */
132 /******************************************************************************/
138 /** @addtogroup STM32F4xx_System_Private_Macros
142 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
143 #if !defined (USE_PLL_HSE_EXTC)
144 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
146 #if !defined (USE_PLL_HSE_XTAL)
147 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
154 /** @addtogroup STM32F4xx_System_Private_Variables
157 /* This variable is updated in three ways:
158 1) by calling CMSIS function SystemCoreClockUpdate()
159 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
160 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
161 Note: If you use this function to configure the system clock; then there
162 is no need to call the 2 first functions listed above, since SystemCoreClock
163 variable is updated automatically.
165 uint32_t SystemCoreClock = 16000000;
166 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
172 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
176 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
177 static void SystemInit_ExtMemCtl(void);
178 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
180 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
181 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
184 uint8_t SetSysClock_PLL_HSI(void);
190 /** @addtogroup STM32F4xx_System_Private_Functions
195 * @brief Setup the microcontroller system
196 * Initialize the FPU setting, vector table location and External memory
201 void SystemInit(void)
203 /* FPU settings ------------------------------------------------------------*/
204 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
205 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
207 /* Reset the RCC clock configuration to the default reset state ------------*/
209 RCC->CR |= (uint32_t)0x00000001;
211 /* Reset CFGR register */
212 RCC->CFGR = 0x00000000;
214 /* Reset HSEON, CSSON and PLLON bits */
215 RCC->CR &= (uint32_t)0xFEF6FFFF;
217 /* Reset PLLCFGR register */
218 RCC->PLLCFGR = 0x24003010;
220 /* Reset HSEBYP bit */
221 RCC->CR &= (uint32_t)0xFFFBFFFF;
223 /* Disable all interrupts */
224 RCC->CIR = 0x00000000;
226 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
227 SystemInit_ExtMemCtl();
228 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
230 /* Configure the Vector Table location add offset address ------------------*/
232 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
234 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
237 /* Configure the Cube driver */
238 SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
241 /* Configure the System clock source, PLL Multiplier and Divider factors,
242 AHB/APBx prescalers and Flash settings */
245 /* Reset the timer to avoid issues after the RAM initialization */
251 * @brief Update SystemCoreClock variable according to Clock Register Values.
252 * The SystemCoreClock variable contains the core clock (HCLK), it can
253 * be used by the user application to setup the SysTick timer or configure
256 * @note Each time the core clock (HCLK) changes, this function must be called
257 * to update SystemCoreClock variable value. Otherwise, any configuration
258 * based on this variable will be incorrect.
260 * @note - The system frequency computed by this function is not the real
261 * frequency in the chip. It is calculated based on the predefined
262 * constant and the selected clock source:
264 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
266 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
268 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
269 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
271 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
272 * 16 MHz) but the real value may vary depending on the variations
273 * in voltage and temperature.
275 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
276 * depends on the application requirements), user has to ensure that HSE_VALUE
277 * is same as the real frequency of the crystal used. Otherwise, this function
278 * may have wrong result.
280 * - The result of this function could be not correct when using fractional
281 * value for HSE crystal.
286 void SystemCoreClockUpdate(void)
288 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
290 /* Get SYSCLK source -------------------------------------------------------*/
291 tmp = RCC->CFGR & RCC_CFGR_SWS;
295 case 0x00: /* HSI used as system clock source */
296 SystemCoreClock = HSI_VALUE;
298 case 0x04: /* HSE used as system clock source */
299 SystemCoreClock = HSE_VALUE;
301 case 0x08: /* PLL used as system clock source */
303 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
304 SYSCLK = PLL_VCO / PLL_P
306 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
307 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
311 /* HSE used as PLL clock source */
312 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
316 /* HSI used as PLL clock source */
317 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
320 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
321 SystemCoreClock = pllvco/pllp;
324 SystemCoreClock = HSI_VALUE;
327 /* Compute HCLK frequency --------------------------------------------------*/
328 /* Get HCLK prescaler */
329 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
331 SystemCoreClock >>= tmp;
334 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
336 * @brief Setup the external memory controller.
337 * Called in startup_stm32f4xx.s before jump to main.
338 * This function configures the external memories (SRAM/SDRAM)
339 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
343 void SystemInit_ExtMemCtl(void)
345 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
346 #if defined (DATA_IN_ExtSDRAM)
347 register uint32_t tmpreg = 0, timeout = 0xFFFF;
348 register uint32_t index;
350 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
352 RCC->AHB1ENR |= 0x000001F8;
354 /* Connect PDx pins to FMC Alternate function */
355 GPIOD->AFR[0] = 0x000000CC;
356 GPIOD->AFR[1] = 0xCC000CCC;
357 /* Configure PDx pins in Alternate function mode */
358 GPIOD->MODER = 0xA02A000A;
359 /* Configure PDx pins speed to 50 MHz */
360 GPIOD->OSPEEDR = 0xA02A000A;
361 /* Configure PDx pins Output type to push-pull */
362 GPIOD->OTYPER = 0x00000000;
363 /* No pull-up, pull-down for PDx pins */
364 GPIOD->PUPDR = 0x00000000;
366 /* Connect PEx pins to FMC Alternate function */
367 GPIOE->AFR[0] = 0xC00000CC;
368 GPIOE->AFR[1] = 0xCCCCCCCC;
369 /* Configure PEx pins in Alternate function mode */
370 GPIOE->MODER = 0xAAAA800A;
371 /* Configure PEx pins speed to 50 MHz */
372 GPIOE->OSPEEDR = 0xAAAA800A;
373 /* Configure PEx pins Output type to push-pull */
374 GPIOE->OTYPER = 0x00000000;
375 /* No pull-up, pull-down for PEx pins */
376 GPIOE->PUPDR = 0x00000000;
378 /* Connect PFx pins to FMC Alternate function */
379 GPIOF->AFR[0] = 0xCCCCCCCC;
380 GPIOF->AFR[1] = 0xCCCCCCCC;
381 /* Configure PFx pins in Alternate function mode */
382 GPIOF->MODER = 0xAA800AAA;
383 /* Configure PFx pins speed to 50 MHz */
384 GPIOF->OSPEEDR = 0xAA800AAA;
385 /* Configure PFx pins Output type to push-pull */
386 GPIOF->OTYPER = 0x00000000;
387 /* No pull-up, pull-down for PFx pins */
388 GPIOF->PUPDR = 0x00000000;
390 /* Connect PGx pins to FMC Alternate function */
391 GPIOG->AFR[0] = 0xCCCCCCCC;
392 GPIOG->AFR[1] = 0xCCCCCCCC;
393 /* Configure PGx pins in Alternate function mode */
394 GPIOG->MODER = 0xAAAAAAAA;
395 /* Configure PGx pins speed to 50 MHz */
396 GPIOG->OSPEEDR = 0xAAAAAAAA;
397 /* Configure PGx pins Output type to push-pull */
398 GPIOG->OTYPER = 0x00000000;
399 /* No pull-up, pull-down for PGx pins */
400 GPIOG->PUPDR = 0x00000000;
402 /* Connect PHx pins to FMC Alternate function */
403 GPIOH->AFR[0] = 0x00C0CC00;
404 GPIOH->AFR[1] = 0xCCCCCCCC;
405 /* Configure PHx pins in Alternate function mode */
406 GPIOH->MODER = 0xAAAA08A0;
407 /* Configure PHx pins speed to 50 MHz */
408 GPIOH->OSPEEDR = 0xAAAA08A0;
409 /* Configure PHx pins Output type to push-pull */
410 GPIOH->OTYPER = 0x00000000;
411 /* No pull-up, pull-down for PHx pins */
412 GPIOH->PUPDR = 0x00000000;
414 /* Connect PIx pins to FMC Alternate function */
415 GPIOI->AFR[0] = 0xCCCCCCCC;
416 GPIOI->AFR[1] = 0x00000CC0;
417 /* Configure PIx pins in Alternate function mode */
418 GPIOI->MODER = 0x0028AAAA;
419 /* Configure PIx pins speed to 50 MHz */
420 GPIOI->OSPEEDR = 0x0028AAAA;
421 /* Configure PIx pins Output type to push-pull */
422 GPIOI->OTYPER = 0x00000000;
423 /* No pull-up, pull-down for PIx pins */
424 GPIOI->PUPDR = 0x00000000;
426 /*-- FMC Configuration ------------------------------------------------------*/
427 /* Enable the FMC interface clock */
428 RCC->AHB3ENR |= 0x00000001;
430 /* Configure and enable SDRAM bank1 */
431 FMC_Bank5_6->SDCR[0] = 0x000019E0;
432 FMC_Bank5_6->SDTR[0] = 0x01115351;
434 /* SDRAM initialization sequence */
435 /* Clock enable command */
436 FMC_Bank5_6->SDCMR = 0x00000011;
437 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
438 while((tmpreg != 0) && (timeout-- > 0))
440 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
444 for (index = 0; index<1000; index++);
447 FMC_Bank5_6->SDCMR = 0x00000012;
449 while((tmpreg != 0) && (timeout-- > 0))
451 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
454 /* Auto refresh command */
455 FMC_Bank5_6->SDCMR = 0x00000073;
457 while((tmpreg != 0) && (timeout-- > 0))
459 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
462 /* MRD register program */
463 FMC_Bank5_6->SDCMR = 0x00046014;
465 while((tmpreg != 0) && (timeout-- > 0))
467 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
470 /* Set refresh count */
471 tmpreg = FMC_Bank5_6->SDRTR;
472 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
474 /* Disable write protection */
475 tmpreg = FMC_Bank5_6->SDCR[0];
476 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
477 #endif /* DATA_IN_ExtSDRAM */
478 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
480 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
481 #if defined(DATA_IN_ExtSRAM)
482 /*-- GPIOs Configuration -----------------------------------------------------*/
483 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
484 RCC->AHB1ENR |= 0x00000078;
486 /* Connect PDx pins to FMC Alternate function */
487 GPIOD->AFR[0] = 0x00CCC0CC;
488 GPIOD->AFR[1] = 0xCCCCCCCC;
489 /* Configure PDx pins in Alternate function mode */
490 GPIOD->MODER = 0xAAAA0A8A;
491 /* Configure PDx pins speed to 100 MHz */
492 GPIOD->OSPEEDR = 0xFFFF0FCF;
493 /* Configure PDx pins Output type to push-pull */
494 GPIOD->OTYPER = 0x00000000;
495 /* No pull-up, pull-down for PDx pins */
496 GPIOD->PUPDR = 0x00000000;
498 /* Connect PEx pins to FMC Alternate function */
499 GPIOE->AFR[0] = 0xC00CC0CC;
500 GPIOE->AFR[1] = 0xCCCCCCCC;
501 /* Configure PEx pins in Alternate function mode */
502 GPIOE->MODER = 0xAAAA828A;
503 /* Configure PEx pins speed to 100 MHz */
504 GPIOE->OSPEEDR = 0xFFFFC3CF;
505 /* Configure PEx pins Output type to push-pull */
506 GPIOE->OTYPER = 0x00000000;
507 /* No pull-up, pull-down for PEx pins */
508 GPIOE->PUPDR = 0x00000000;
510 /* Connect PFx pins to FMC Alternate function */
511 GPIOF->AFR[0] = 0x00CCCCCC;
512 GPIOF->AFR[1] = 0xCCCC0000;
513 /* Configure PFx pins in Alternate function mode */
514 GPIOF->MODER = 0xAA000AAA;
515 /* Configure PFx pins speed to 100 MHz */
516 GPIOF->OSPEEDR = 0xFF000FFF;
517 /* Configure PFx pins Output type to push-pull */
518 GPIOF->OTYPER = 0x00000000;
519 /* No pull-up, pull-down for PFx pins */
520 GPIOF->PUPDR = 0x00000000;
522 /* Connect PGx pins to FMC Alternate function */
523 GPIOG->AFR[0] = 0x00CCCCCC;
524 GPIOG->AFR[1] = 0x000000C0;
525 /* Configure PGx pins in Alternate function mode */
526 GPIOG->MODER = 0x00085AAA;
527 /* Configure PGx pins speed to 100 MHz */
528 GPIOG->OSPEEDR = 0x000CAFFF;
529 /* Configure PGx pins Output type to push-pull */
530 GPIOG->OTYPER = 0x00000000;
531 /* No pull-up, pull-down for PGx pins */
532 GPIOG->PUPDR = 0x00000000;
534 /*-- FMC/FSMC Configuration --------------------------------------------------*/
535 /* Enable the FMC/FSMC interface clock */
536 RCC->AHB3ENR |= 0x00000001;
538 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
539 /* Configure and enable Bank1_SRAM2 */
540 FMC_Bank1->BTCR[2] = 0x00001011;
541 FMC_Bank1->BTCR[3] = 0x00000201;
542 FMC_Bank1E->BWTR[2] = 0x0fffffff;
543 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
545 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
546 /* Configure and enable Bank1_SRAM2 */
547 FSMC_Bank1->BTCR[2] = 0x00001011;
548 FSMC_Bank1->BTCR[3] = 0x00000201;
549 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
550 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
552 #endif /* DATA_IN_ExtSRAM */
553 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
555 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
558 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
559 * AHB/APBx prescalers and Flash settings
560 * @note This function should be called only once the RCC clock configuration
561 * is reset to the default reset state (done in SystemInit() function).
565 void SetSysClock(void)
567 /* 1- Try to start with HSE and external clock */
568 #if USE_PLL_HSE_EXTC != 0
569 if (SetSysClock_PLL_HSE(1) == 0)
572 /* 2- If fail try to start with HSE and external xtal */
573 #if USE_PLL_HSE_XTAL != 0
574 if (SetSysClock_PLL_HSE(0) == 0)
577 /* 3- If fail start with HSI clock */
578 if (SetSysClock_PLL_HSI() == 0)
582 // [TODO] Put something here to tell the user that a problem occured...
588 /* Output clock on MCO2 pin(PC9) for debugging purpose */
589 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
592 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
593 /******************************************************************************/
594 /* PLL (clocked by HSE) used as System clock source */
595 /******************************************************************************/
596 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
598 RCC_ClkInitTypeDef RCC_ClkInitStruct;
599 RCC_OscInitTypeDef RCC_OscInitStruct;
601 /* The voltage scaling allows optimizing the power consumption when the device is
602 clocked below the maximum system frequency, to update the voltage scaling value
603 regarding system frequency refer to product datasheet. */
605 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
607 /* Enable HSE oscillator and activate PLL with HSE as source */
608 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
611 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
615 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
617 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
618 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
619 RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; // VCO input clock = 1 MHz
620 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 192 MHz (1 MHz * 192)
621 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 96 MHz (192 MHz / 2)
622 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock = 48 MHz (192 MHz / 4)
623 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
628 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
629 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
630 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
631 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
632 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
633 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
634 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
639 /* Output clock on MCO1 pin(PA8) for debugging purpose */
642 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
644 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
650 /******************************************************************************/
651 /* PLL (clocked by HSI) used as System clock source */
652 /******************************************************************************/
653 uint8_t SetSysClock_PLL_HSI(void)
655 RCC_ClkInitTypeDef RCC_ClkInitStruct;
656 RCC_OscInitTypeDef RCC_OscInitStruct;
658 /* The voltage scaling allows optimizing the power consumption when the device is
659 clocked below the maximum system frequency, to update the voltage scaling value
660 regarding system frequency refer to product datasheet. */
662 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
664 /* Enable HSI oscillator and activate PLL with HSI as source */
665 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
666 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
667 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
668 RCC_OscInitStruct.HSICalibrationValue = 16;
669 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
670 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
671 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
672 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 192 MHz (1 MHz * 192)
673 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 96 MHz (192 MHz / 2)
674 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock = 48 MHz (192 MHz / 4) --> Not stable for USB
675 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
680 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
681 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
682 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
683 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
684 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
685 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
686 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
691 /* Output clock on MCO1 pin(PA8) for debugging purpose */
692 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
708 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/