2 ******************************************************************************
3 * @file system_stm32f4xx.c
4 * @author MCD Application Team
7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
9 * This file provides two functions and one global variable to be called from
11 * - SystemInit(): This function is called at startup just after reset and
12 * before branch to main program. This call is made inside
13 * the "startup_stm32f4xx.s" file.
15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
16 * by the user application to setup the SysTick
17 * timer or configure other parameters.
19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
20 * be called whenever the core clock is changed
21 * during program execution.
24 ******************************************************************************
27 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
29 * Redistribution and use in source and binary forms, with or without modification,
30 * are permitted provided that the following conditions are met:
31 * 1. Redistributions of source code must retain the above copyright notice,
32 * this list of conditions and the following disclaimer.
33 * 2. Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following disclaimer in the documentation
35 * and/or other materials provided with the distribution.
36 * 3. Neither the name of STMicroelectronics nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
41 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
43 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
46 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
47 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
49 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 ******************************************************************************
58 /** @addtogroup stm32f4xx_system
62 /** @addtogroup STM32F4xx_System_Private_Includes
67 #include "stm32f4xx.h"
70 #if !defined (HSE_VALUE)
71 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
72 #endif /* HSE_VALUE */
74 #if !defined (HSI_VALUE)
75 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
76 #endif /* HSI_VALUE */
82 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
90 /** @addtogroup STM32F4xx_System_Private_Defines
94 /************************* Miscellaneous Configuration ************************/
95 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
96 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
97 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
98 /* #define DATA_IN_ExtSRAM */
99 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
101 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
102 /* #define DATA_IN_ExtSDRAM */
103 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
105 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
106 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
107 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
109 /*!< Uncomment the following line if you need to relocate your vector Table in
111 /* #define VECT_TAB_SRAM */
112 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
113 This value must be a multiple of 0x200. */
114 /******************************************************************************/
120 /** @addtogroup STM32F4xx_System_Private_Macros
128 /** @addtogroup STM32F4xx_System_Private_Variables
131 /* This variable is updated in three ways:
132 1) by calling CMSIS function SystemCoreClockUpdate()
133 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
134 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
135 Note: If you use this function to configure the system clock; then there
136 is no need to call the 2 first functions listed above, since SystemCoreClock
137 variable is updated automatically.
139 uint32_t SystemCoreClock = 48000000;
140 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
146 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
150 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
151 static void SystemInit_ExtMemCtl(void);
152 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
158 /** @addtogroup STM32F4xx_System_Private_Functions
163 * @brief Setup the microcontroller system
164 * Initialize the FPU setting, vector table location and External memory
169 void SystemInit(void)
171 /* FPU settings ------------------------------------------------------------*/
172 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
173 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
175 /* Reset the RCC clock configuration to the default reset state ------------*/
177 RCC->CR |= (uint32_t)0x00000001;
179 /* Reset CFGR register */
180 RCC->CFGR = 0x00000000;
182 /* Reset HSEON, CSSON and PLLON bits */
183 RCC->CR &= (uint32_t)0xFEF6FFFF;
185 /* Reset PLLCFGR register */
186 RCC->PLLCFGR = 0x24003010;
188 /* Reset HSEBYP bit */
189 RCC->CR &= (uint32_t)0xFFFBFFFF;
191 /* Disable all interrupts */
192 RCC->CIR = 0x00000000;
194 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
195 SystemInit_ExtMemCtl();
196 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
198 /* Configure the Vector Table location add offset address ------------------*/
200 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
202 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
205 /* Configure the Cube driver */
206 SystemCoreClock = 48000000; // At this stage the HSI is used as system clock
209 /* Configure the System clock source, PLL Multiplier and Divider factors,
210 AHB/APBx prescalers and Flash settings */
213 SystemCoreClockUpdate();
215 /* Reset the timer to avoid issues after the RAM initialization */
221 * @brief Update SystemCoreClock variable according to Clock Register Values.
222 * The SystemCoreClock variable contains the core clock (HCLK), it can
223 * be used by the user application to setup the SysTick timer or configure
226 * @note Each time the core clock (HCLK) changes, this function must be called
227 * to update SystemCoreClock variable value. Otherwise, any configuration
228 * based on this variable will be incorrect.
230 * @note - The system frequency computed by this function is not the real
231 * frequency in the chip. It is calculated based on the predefined
232 * constant and the selected clock source:
234 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
236 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
238 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
239 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
241 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
242 * 16 MHz) but the real value may vary depending on the variations
243 * in voltage and temperature.
245 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
246 * depends on the application requirements), user has to ensure that HSE_VALUE
247 * is same as the real frequency of the crystal used. Otherwise, this function
248 * may have wrong result.
250 * - The result of this function could be not correct when using fractional
251 * value for HSE crystal.
256 void SystemCoreClockUpdate(void)
258 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
260 /* Get SYSCLK source -------------------------------------------------------*/
261 tmp = RCC->CFGR & RCC_CFGR_SWS;
265 case 0x00: /* HSI used as system clock source */
266 SystemCoreClock = HSI_VALUE;
268 case 0x04: /* HSE used as system clock source */
269 SystemCoreClock = HSE_VALUE;
271 case 0x08: /* PLL used as system clock source */
273 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
274 SYSCLK = PLL_VCO / PLL_P
276 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
277 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
281 /* HSE used as PLL clock source */
282 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
286 /* HSI used as PLL clock source */
287 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
290 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
291 SystemCoreClock = pllvco/pllp;
294 SystemCoreClock = HSI_VALUE;
297 /* Compute HCLK frequency --------------------------------------------------*/
298 /* Get HCLK prescaler */
299 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
301 SystemCoreClock >>= tmp;
304 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
306 * @brief Setup the external memory controller.
307 * Called in startup_stm32f4xx.s before jump to main.
308 * This function configures the external memories (SRAM/SDRAM)
309 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
313 void SystemInit_ExtMemCtl(void)
315 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
316 #if defined (DATA_IN_ExtSDRAM)
317 register uint32_t tmpreg = 0, timeout = 0xFFFF;
318 register uint32_t index;
320 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
322 RCC->AHB1ENR |= 0x000001F8;
324 /* Connect PDx pins to FMC Alternate function */
325 GPIOD->AFR[0] = 0x000000CC;
326 GPIOD->AFR[1] = 0xCC000CCC;
327 /* Configure PDx pins in Alternate function mode */
328 GPIOD->MODER = 0xA02A000A;
329 /* Configure PDx pins speed to 50 MHz */
330 GPIOD->OSPEEDR = 0xA02A000A;
331 /* Configure PDx pins Output type to push-pull */
332 GPIOD->OTYPER = 0x00000000;
333 /* No pull-up, pull-down for PDx pins */
334 GPIOD->PUPDR = 0x00000000;
336 /* Connect PEx pins to FMC Alternate function */
337 GPIOE->AFR[0] = 0xC00000CC;
338 GPIOE->AFR[1] = 0xCCCCCCCC;
339 /* Configure PEx pins in Alternate function mode */
340 GPIOE->MODER = 0xAAAA800A;
341 /* Configure PEx pins speed to 50 MHz */
342 GPIOE->OSPEEDR = 0xAAAA800A;
343 /* Configure PEx pins Output type to push-pull */
344 GPIOE->OTYPER = 0x00000000;
345 /* No pull-up, pull-down for PEx pins */
346 GPIOE->PUPDR = 0x00000000;
348 /* Connect PFx pins to FMC Alternate function */
349 GPIOF->AFR[0] = 0xCCCCCCCC;
350 GPIOF->AFR[1] = 0xCCCCCCCC;
351 /* Configure PFx pins in Alternate function mode */
352 GPIOF->MODER = 0xAA800AAA;
353 /* Configure PFx pins speed to 50 MHz */
354 GPIOF->OSPEEDR = 0xAA800AAA;
355 /* Configure PFx pins Output type to push-pull */
356 GPIOF->OTYPER = 0x00000000;
357 /* No pull-up, pull-down for PFx pins */
358 GPIOF->PUPDR = 0x00000000;
360 /* Connect PGx pins to FMC Alternate function */
361 GPIOG->AFR[0] = 0xCCCCCCCC;
362 GPIOG->AFR[1] = 0xCCCCCCCC;
363 /* Configure PGx pins in Alternate function mode */
364 GPIOG->MODER = 0xAAAAAAAA;
365 /* Configure PGx pins speed to 50 MHz */
366 GPIOG->OSPEEDR = 0xAAAAAAAA;
367 /* Configure PGx pins Output type to push-pull */
368 GPIOG->OTYPER = 0x00000000;
369 /* No pull-up, pull-down for PGx pins */
370 GPIOG->PUPDR = 0x00000000;
372 /* Connect PHx pins to FMC Alternate function */
373 GPIOH->AFR[0] = 0x00C0CC00;
374 GPIOH->AFR[1] = 0xCCCCCCCC;
375 /* Configure PHx pins in Alternate function mode */
376 GPIOH->MODER = 0xAAAA08A0;
377 /* Configure PHx pins speed to 50 MHz */
378 GPIOH->OSPEEDR = 0xAAAA08A0;
379 /* Configure PHx pins Output type to push-pull */
380 GPIOH->OTYPER = 0x00000000;
381 /* No pull-up, pull-down for PHx pins */
382 GPIOH->PUPDR = 0x00000000;
384 /* Connect PIx pins to FMC Alternate function */
385 GPIOI->AFR[0] = 0xCCCCCCCC;
386 GPIOI->AFR[1] = 0x00000CC0;
387 /* Configure PIx pins in Alternate function mode */
388 GPIOI->MODER = 0x0028AAAA;
389 /* Configure PIx pins speed to 50 MHz */
390 GPIOI->OSPEEDR = 0x0028AAAA;
391 /* Configure PIx pins Output type to push-pull */
392 GPIOI->OTYPER = 0x00000000;
393 /* No pull-up, pull-down for PIx pins */
394 GPIOI->PUPDR = 0x00000000;
396 /*-- FMC Configuration ------------------------------------------------------*/
397 /* Enable the FMC interface clock */
398 RCC->AHB3ENR |= 0x00000001;
400 /* Configure and enable SDRAM bank1 */
401 FMC_Bank5_6->SDCR[0] = 0x000019E0;
402 FMC_Bank5_6->SDTR[0] = 0x01115351;
404 /* SDRAM initialization sequence */
405 /* Clock enable command */
406 FMC_Bank5_6->SDCMR = 0x00000011;
407 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
408 while((tmpreg != 0) && (timeout-- > 0))
410 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
414 for (index = 0; index<1000; index++);
417 FMC_Bank5_6->SDCMR = 0x00000012;
419 while((tmpreg != 0) && (timeout-- > 0))
421 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
424 /* Auto refresh command */
425 FMC_Bank5_6->SDCMR = 0x00000073;
427 while((tmpreg != 0) && (timeout-- > 0))
429 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
432 /* MRD register program */
433 FMC_Bank5_6->SDCMR = 0x00046014;
435 while((tmpreg != 0) && (timeout-- > 0))
437 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
440 /* Set refresh count */
441 tmpreg = FMC_Bank5_6->SDRTR;
442 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
444 /* Disable write protection */
445 tmpreg = FMC_Bank5_6->SDCR[0];
446 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
447 #endif /* DATA_IN_ExtSDRAM */
448 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
450 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
451 #if defined(DATA_IN_ExtSRAM)
452 /*-- GPIOs Configuration -----------------------------------------------------*/
453 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
454 RCC->AHB1ENR |= 0x00000078;
456 /* Connect PDx pins to FMC Alternate function */
457 GPIOD->AFR[0] = 0x00CCC0CC;
458 GPIOD->AFR[1] = 0xCCCCCCCC;
459 /* Configure PDx pins in Alternate function mode */
460 GPIOD->MODER = 0xAAAA0A8A;
461 /* Configure PDx pins speed to 100 MHz */
462 GPIOD->OSPEEDR = 0xFFFF0FCF;
463 /* Configure PDx pins Output type to push-pull */
464 GPIOD->OTYPER = 0x00000000;
465 /* No pull-up, pull-down for PDx pins */
466 GPIOD->PUPDR = 0x00000000;
468 /* Connect PEx pins to FMC Alternate function */
469 GPIOE->AFR[0] = 0xC00CC0CC;
470 GPIOE->AFR[1] = 0xCCCCCCCC;
471 /* Configure PEx pins in Alternate function mode */
472 GPIOE->MODER = 0xAAAA828A;
473 /* Configure PEx pins speed to 100 MHz */
474 GPIOE->OSPEEDR = 0xFFFFC3CF;
475 /* Configure PEx pins Output type to push-pull */
476 GPIOE->OTYPER = 0x00000000;
477 /* No pull-up, pull-down for PEx pins */
478 GPIOE->PUPDR = 0x00000000;
480 /* Connect PFx pins to FMC Alternate function */
481 GPIOF->AFR[0] = 0x00CCCCCC;
482 GPIOF->AFR[1] = 0xCCCC0000;
483 /* Configure PFx pins in Alternate function mode */
484 GPIOF->MODER = 0xAA000AAA;
485 /* Configure PFx pins speed to 100 MHz */
486 GPIOF->OSPEEDR = 0xFF000FFF;
487 /* Configure PFx pins Output type to push-pull */
488 GPIOF->OTYPER = 0x00000000;
489 /* No pull-up, pull-down for PFx pins */
490 GPIOF->PUPDR = 0x00000000;
492 /* Connect PGx pins to FMC Alternate function */
493 GPIOG->AFR[0] = 0x00CCCCCC;
494 GPIOG->AFR[1] = 0x000000C0;
495 /* Configure PGx pins in Alternate function mode */
496 GPIOG->MODER = 0x00085AAA;
497 /* Configure PGx pins speed to 100 MHz */
498 GPIOG->OSPEEDR = 0x000CAFFF;
499 /* Configure PGx pins Output type to push-pull */
500 GPIOG->OTYPER = 0x00000000;
501 /* No pull-up, pull-down for PGx pins */
502 GPIOG->PUPDR = 0x00000000;
504 /*-- FMC/FSMC Configuration --------------------------------------------------*/
505 /* Enable the FMC/FSMC interface clock */
506 RCC->AHB3ENR |= 0x00000001;
508 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
509 /* Configure and enable Bank1_SRAM2 */
510 FMC_Bank1->BTCR[2] = 0x00001011;
511 FMC_Bank1->BTCR[3] = 0x00000201;
512 FMC_Bank1E->BWTR[2] = 0x0fffffff;
513 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
515 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
516 /* Configure and enable Bank1_SRAM2 */
517 FSMC_Bank1->BTCR[2] = 0x00001011;
518 FSMC_Bank1->BTCR[3] = 0x00000201;
519 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
520 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
522 #endif /* DATA_IN_ExtSRAM */
523 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
525 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
528 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
529 * AHB/APBx prescalers and Flash settings
530 * @note This function should be called only once the RCC clock configuration
531 * is reset to the default reset state (done in SystemInit() function).
535 void SetSysClock(void)
537 RCC_ClkInitTypeDef RCC_ClkInitStruct;
538 RCC_OscInitTypeDef RCC_OscInitStruct;
542 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
544 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
545 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
546 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
547 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
548 RCC_OscInitStruct.PLL.PLLM = 26;
549 RCC_OscInitStruct.PLL.PLLN = 192;
550 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
551 RCC_OscInitStruct.PLL.PLLQ = 4;
552 HAL_RCC_OscConfig(&RCC_OscInitStruct);
554 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
555 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
556 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
557 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
558 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
559 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1);
572 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/