2 /****************************************************************************************************//**
5 * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
6 * nRF51 from Nordic Semiconductor.
9 * @date 31. October 2014
11 * @note Generated with SVDConv V2.81d
12 * from CMSIS SVD File 'nRF51.xml' Version 522,
14 * @par Copyright (c) 2013, Nordic Semiconductor ASA
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are met:
20 * * Redistributions of source code must retain the above copyright notice, this
21 * list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
27 * * Neither the name of Nordic Semiconductor ASA nor the names of its
28 * contributors may be used to endorse or promote products derived from
29 * this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
32 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
37 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
38 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 *******************************************************************************************************/
47 /** @addtogroup Nordic Semiconductor
63 /* ------------------------- Interrupt Number Definition ------------------------ */
66 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
67 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
68 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
69 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
70 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
71 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
72 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
73 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
74 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
75 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
76 RADIO_IRQn = 1, /*!< 1 RADIO */
77 UART0_IRQn = 2, /*!< 2 UART0 */
78 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
79 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
80 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
81 ADC_IRQn = 7, /*!< 7 ADC */
82 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
83 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
84 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
85 RTC0_IRQn = 11, /*!< 11 RTC0 */
86 TEMP_IRQn = 12, /*!< 12 TEMP */
87 RNG_IRQn = 13, /*!< 13 RNG */
88 ECB_IRQn = 14, /*!< 14 ECB */
89 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
90 WDT_IRQn = 16, /*!< 16 WDT */
91 RTC1_IRQn = 17, /*!< 17 RTC1 */
92 QDEC_IRQn = 18, /*!< 18 QDEC */
93 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
94 SWI0_IRQn = 20, /*!< 20 SWI0 */
95 SWI1_IRQn = 21, /*!< 21 SWI1 */
96 SWI2_IRQn = 22, /*!< 22 SWI2 */
97 SWI3_IRQn = 23, /*!< 23 SWI3 */
98 SWI4_IRQn = 24, /*!< 24 SWI4 */
99 SWI5_IRQn = 25 /*!< 25 SWI5 */
103 /** @addtogroup Configuration_of_CMSIS
108 /* ================================================================================ */
109 /* ================ Processor and Core Peripheral Section ================ */
110 /* ================================================================================ */
112 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
113 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
114 #define __MPU_PRESENT 0 /*!< MPU present or not */
115 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
116 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
117 /** @} */ /* End of group Configuration_of_CMSIS */
119 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
120 #include "system_nrf51.h" /*!< nRF51 System */
122 /* ================================================================================ */
123 /* ================ Device Specific Peripheral Section ================ */
124 /* ================================================================================ */
127 /** @addtogroup Device_Peripheral_Registers
132 /* ------------------- Start of section using anonymous unions ------------------ */
133 #if defined(__CC_ARM)
136 #elif defined(__ICCARM__)
137 #pragma language=extended
138 #elif defined(__GNUC__)
139 /* anonymous unions are enabled by default */
140 #elif defined(__TMS470__)
141 /* anonymous unions are enabled by default */
142 #elif defined(__TASKING__)
145 #warning Not supported compiler type
150 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
151 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
152 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
153 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
154 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
155 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
159 __IO uint32_t SCK; /*!< Pin select for SCK. */
160 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
161 __IO uint32_t MISO; /*!< Pin select for MISO. */
165 __IO uint32_t PTR; /*!< Data pointer. */
166 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
167 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
171 __IO uint32_t PTR; /*!< Data pointer. */
172 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
173 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
177 __O uint32_t EN; /*!< Enable channel group. */
178 __O uint32_t DIS; /*!< Disable channel group. */
179 } PPI_TASKS_CHG_Type;
182 __IO uint32_t EEP; /*!< Channel event end-point. */
183 __IO uint32_t TEP; /*!< Channel task end-point. */
187 __I uint32_t PART; /*!< Part code */
188 __I uint32_t VARIANT; /*!< Part variant */
189 __I uint32_t PACKAGE; /*!< Package option */
190 __I uint32_t RAM; /*!< RAM variant */
191 __I uint32_t FLASH; /*!< Flash variant */
192 __I uint32_t RESERVED[3]; /*!< Reserved */
196 /* ================================================================================ */
197 /* ================ POWER ================ */
198 /* ================================================================================ */
202 * @brief Power Control. (POWER)
205 typedef struct { /*!< POWER Structure */
206 __I uint32_t RESERVED0[30];
207 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
208 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
209 __I uint32_t RESERVED1[34];
210 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
211 __I uint32_t RESERVED2[126];
212 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
213 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
214 __I uint32_t RESERVED3[61];
215 __IO uint32_t RESETREAS; /*!< Reset reason. */
216 __I uint32_t RESERVED4[9];
217 __I uint32_t RAMSTATUS; /*!< Ram status register. */
218 __I uint32_t RESERVED5[53];
219 __O uint32_t SYSTEMOFF; /*!< System off register. */
220 __I uint32_t RESERVED6[3];
221 __IO uint32_t POFCON; /*!< Power failure configuration. */
222 __I uint32_t RESERVED7[2];
223 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
225 __I uint32_t RESERVED8;
226 __IO uint32_t RAMON; /*!< Ram on/off. */
227 __I uint32_t RESERVED9[7];
228 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
229 is a retained register. */
230 __I uint32_t RESERVED10[3];
231 __IO uint32_t RAMONB; /*!< Ram on/off. */
232 __I uint32_t RESERVED11[8];
233 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
234 __I uint32_t RESERVED12[291];
235 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
239 /* ================================================================================ */
240 /* ================ CLOCK ================ */
241 /* ================================================================================ */
245 * @brief Clock control. (CLOCK)
248 typedef struct { /*!< CLOCK Structure */
249 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
250 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
251 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
252 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
253 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
254 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
255 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
256 __I uint32_t RESERVED0[57];
257 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
258 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
259 __I uint32_t RESERVED1;
260 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
261 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
262 __I uint32_t RESERVED2[124];
263 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
264 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
265 __I uint32_t RESERVED3[63];
266 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
267 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
268 __I uint32_t RESERVED4;
269 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
270 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
271 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
273 __I uint32_t RESERVED5[62];
274 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
275 __I uint32_t RESERVED6[7];
276 __IO uint32_t CTIV; /*!< Calibration timer interval. */
277 __I uint32_t RESERVED7[5];
278 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
282 /* ================================================================================ */
283 /* ================ MPU ================ */
284 /* ================================================================================ */
288 * @brief Memory Protection Unit. (MPU)
291 typedef struct { /*!< MPU Structure */
292 __I uint32_t RESERVED0[330];
293 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
294 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
295 __I uint32_t RESERVED1[52];
296 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
297 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
298 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
299 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
303 /* ================================================================================ */
304 /* ================ PU ================ */
305 /* ================================================================================ */
309 * @brief Patch unit. (PU)
312 typedef struct { /*!< PU Structure */
313 __I uint32_t RESERVED0[448];
314 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
315 __I uint32_t RESERVED1[24];
316 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
317 __I uint32_t RESERVED2[24];
318 __IO uint32_t PATCHEN; /*!< Patch enable register. */
319 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
320 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
324 /* ================================================================================ */
325 /* ================ AMLI ================ */
326 /* ================================================================================ */
330 * @brief AHB Multi-Layer Interface. (AMLI)
333 typedef struct { /*!< AMLI Structure */
334 __I uint32_t RESERVED0[896];
335 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
339 /* ================================================================================ */
340 /* ================ RADIO ================ */
341 /* ================================================================================ */
345 * @brief The radio. (RADIO)
348 typedef struct { /*!< RADIO Structure */
349 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
350 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
351 __O uint32_t TASKS_START; /*!< Start radio. */
352 __O uint32_t TASKS_STOP; /*!< Stop radio. */
353 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
354 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
355 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
356 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
357 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
358 __I uint32_t RESERVED0[55];
359 __IO uint32_t EVENTS_READY; /*!< Ready event. */
360 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
361 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
362 __IO uint32_t EVENTS_END; /*!< End event. */
363 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
364 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
365 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
366 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
367 sample is ready for readout at the RSSISAMPLE register. */
368 __I uint32_t RESERVED1[2];
369 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
370 __I uint32_t RESERVED2[53];
371 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
372 __I uint32_t RESERVED3[64];
373 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
374 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
375 __I uint32_t RESERVED4[61];
376 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
377 __I uint32_t CD; /*!< Carrier detect. */
378 __I uint32_t RXMATCH; /*!< Received address. */
379 __I uint32_t RXCRC; /*!< Received CRC. */
380 __I uint32_t DAI; /*!< Device address match index. */
381 __I uint32_t RESERVED5[60];
382 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
383 __IO uint32_t FREQUENCY; /*!< Frequency. */
384 __IO uint32_t TXPOWER; /*!< Output power. */
385 __IO uint32_t MODE; /*!< Data rate and modulation. */
386 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
387 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
388 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
389 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
390 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
391 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
392 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
393 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
394 __IO uint32_t CRCCNF; /*!< CRC configuration. */
395 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
396 __IO uint32_t CRCINIT; /*!< CRC initial value. */
397 __IO uint32_t TEST; /*!< Test features enable register. */
398 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
399 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
400 __I uint32_t RESERVED6;
401 __I uint32_t STATE; /*!< Current radio state. */
402 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
403 __I uint32_t RESERVED7[2];
404 __IO uint32_t BCC; /*!< Bit counter compare. */
405 __I uint32_t RESERVED8[39];
406 __IO uint32_t DAB[8]; /*!< Device address base segment. */
407 __IO uint32_t DAP[8]; /*!< Device address prefix. */
408 __IO uint32_t DACNF; /*!< Device address match configuration. */
409 __I uint32_t RESERVED9[56];
410 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
411 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
412 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
413 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
414 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
415 __I uint32_t RESERVED10[561];
416 __IO uint32_t POWER; /*!< Peripheral power control. */
420 /* ================================================================================ */
421 /* ================ UART ================ */
422 /* ================================================================================ */
426 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
429 typedef struct { /*!< UART Structure */
430 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
431 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
432 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
433 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
434 __I uint32_t RESERVED0[3];
435 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
436 __I uint32_t RESERVED1[56];
437 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
438 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
439 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
440 __I uint32_t RESERVED2[4];
441 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
442 __I uint32_t RESERVED3;
443 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
444 __I uint32_t RESERVED4[7];
445 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
446 __I uint32_t RESERVED5[46];
447 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
448 __I uint32_t RESERVED6[64];
449 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
450 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
451 __I uint32_t RESERVED7[93];
452 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
453 __I uint32_t RESERVED8[31];
454 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
455 __I uint32_t RESERVED9;
456 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
457 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
458 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
459 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
460 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
461 Once read the character is consumed. If read when no character
462 available, the UART will stop working. */
463 __O uint32_t TXD; /*!< TXD register. */
464 __I uint32_t RESERVED10;
465 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
466 __I uint32_t RESERVED11[17];
467 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
468 __I uint32_t RESERVED12[675];
469 __IO uint32_t POWER; /*!< Peripheral power control. */
473 /* ================================================================================ */
474 /* ================ SPI ================ */
475 /* ================================================================================ */
479 * @brief SPI master 0. (SPI)
482 typedef struct { /*!< SPI Structure */
483 __I uint32_t RESERVED0[66];
484 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
485 __I uint32_t RESERVED1[126];
486 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
487 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
488 __I uint32_t RESERVED2[125];
489 __IO uint32_t ENABLE; /*!< Enable SPI. */
490 __I uint32_t RESERVED3;
491 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
492 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
493 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
494 __I uint32_t RESERVED4;
495 __I uint32_t RXD; /*!< RX data. */
496 __IO uint32_t TXD; /*!< TX data. */
497 __I uint32_t RESERVED5;
498 __IO uint32_t FREQUENCY; /*!< SPI frequency */
499 __I uint32_t RESERVED6[11];
500 __IO uint32_t CONFIG; /*!< Configuration register. */
501 __I uint32_t RESERVED7[681];
502 __IO uint32_t POWER; /*!< Peripheral power control. */
506 /* ================================================================================ */
507 /* ================ TWI ================ */
508 /* ================================================================================ */
512 * @brief Two-wire interface master 0. (TWI)
515 typedef struct { /*!< TWI Structure */
516 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
517 __I uint32_t RESERVED0;
518 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
519 __I uint32_t RESERVED1[2];
520 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
521 __I uint32_t RESERVED2;
522 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
523 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
524 __I uint32_t RESERVED3[56];
525 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
526 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
527 __I uint32_t RESERVED4[4];
528 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
529 __I uint32_t RESERVED5;
530 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
531 __I uint32_t RESERVED6[4];
532 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
533 __I uint32_t RESERVED7[3];
534 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
535 __I uint32_t RESERVED8[45];
536 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
537 __I uint32_t RESERVED9[64];
538 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
539 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
540 __I uint32_t RESERVED10[110];
541 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
542 __I uint32_t RESERVED11[14];
543 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
544 __I uint32_t RESERVED12;
545 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
546 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
547 __I uint32_t RESERVED13[2];
548 __I uint32_t RXD; /*!< RX data register. */
549 __IO uint32_t TXD; /*!< TX data register. */
550 __I uint32_t RESERVED14;
551 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
552 __I uint32_t RESERVED15[24];
553 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
554 __I uint32_t RESERVED16[668];
555 __IO uint32_t POWER; /*!< Peripheral power control. */
559 /* ================================================================================ */
560 /* ================ SPIS ================ */
561 /* ================================================================================ */
565 * @brief SPI slave 1. (SPIS)
568 typedef struct { /*!< SPIS Structure */
569 __I uint32_t RESERVED0[9];
570 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
571 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
572 __I uint32_t RESERVED1[54];
573 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
574 __I uint32_t RESERVED2[8];
575 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
576 __I uint32_t RESERVED3[53];
577 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
578 __I uint32_t RESERVED4[64];
579 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
580 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
581 __I uint32_t RESERVED5[61];
582 __I uint32_t SEMSTAT; /*!< Semaphore status. */
583 __I uint32_t RESERVED6[15];
584 __IO uint32_t STATUS; /*!< Status from last transaction. */
585 __I uint32_t RESERVED7[47];
586 __IO uint32_t ENABLE; /*!< Enable SPIS. */
587 __I uint32_t RESERVED8;
588 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
589 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
590 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
591 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
592 __I uint32_t RESERVED9[7];
593 __IO uint32_t RXDPTR; /*!< RX data pointer. */
594 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
595 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
596 __I uint32_t RESERVED10;
597 __IO uint32_t TXDPTR; /*!< TX data pointer. */
598 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
599 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
600 __I uint32_t RESERVED11;
601 __IO uint32_t CONFIG; /*!< Configuration register. */
602 __I uint32_t RESERVED12;
603 __IO uint32_t DEF; /*!< Default character. */
604 __I uint32_t RESERVED13[24];
605 __IO uint32_t ORC; /*!< Over-read character. */
606 __I uint32_t RESERVED14[654];
607 __IO uint32_t POWER; /*!< Peripheral power control. */
611 /* ================================================================================ */
612 /* ================ SPIM ================ */
613 /* ================================================================================ */
617 * @brief SPI master with easyDMA 1. (SPIM)
620 typedef struct { /*!< SPIM Structure */
621 __I uint32_t RESERVED0[4];
622 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
623 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
624 __I uint32_t RESERVED1;
625 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
626 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
627 __I uint32_t RESERVED2[56];
628 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
629 __I uint32_t RESERVED3[2];
630 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
631 __I uint32_t RESERVED4;
632 __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
633 __I uint32_t RESERVED5;
634 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
635 __I uint32_t RESERVED6[10];
636 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
637 __I uint32_t RESERVED7[44];
638 __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
639 __I uint32_t RESERVED8[64];
640 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
641 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
642 __I uint32_t RESERVED9[125];
643 __IO uint32_t ENABLE; /*!< Enable SPIM. */
644 __I uint32_t RESERVED10;
645 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
646 __I uint32_t RESERVED11;
647 __I uint32_t RXDDATA; /*!< RXD register. */
648 __IO uint32_t TXDDATA; /*!< TXD register. */
649 __I uint32_t RESERVED12;
650 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
651 __I uint32_t RESERVED13[3];
652 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
653 __I uint32_t RESERVED14;
654 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
655 __I uint32_t RESERVED15;
656 __IO uint32_t CONFIG; /*!< Configuration register. */
657 __I uint32_t RESERVED16[26];
658 __IO uint32_t ORC; /*!< Over-read character. */
659 __I uint32_t RESERVED17[654];
660 __IO uint32_t POWER; /*!< Peripheral power control. */
664 /* ================================================================================ */
665 /* ================ GPIOTE ================ */
666 /* ================================================================================ */
670 * @brief GPIO tasks and events. (GPIOTE)
673 typedef struct { /*!< GPIOTE Structure */
674 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
675 __I uint32_t RESERVED0[60];
676 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
677 __I uint32_t RESERVED1[27];
678 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
679 __I uint32_t RESERVED2[97];
680 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
681 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
682 __I uint32_t RESERVED3[129];
683 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
684 __I uint32_t RESERVED4[695];
685 __IO uint32_t POWER; /*!< Peripheral power control. */
689 /* ================================================================================ */
690 /* ================ ADC ================ */
691 /* ================================================================================ */
695 * @brief Analog to digital converter. (ADC)
698 typedef struct { /*!< ADC Structure */
699 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
700 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
701 __I uint32_t RESERVED0[62];
702 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
703 __I uint32_t RESERVED1[128];
704 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
705 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
706 __I uint32_t RESERVED2[61];
707 __I uint32_t BUSY; /*!< ADC busy register. */
708 __I uint32_t RESERVED3[63];
709 __IO uint32_t ENABLE; /*!< ADC enable. */
710 __IO uint32_t CONFIG; /*!< ADC configuration register. */
711 __I uint32_t RESULT; /*!< Result of ADC conversion. */
712 __I uint32_t RESERVED4[700];
713 __IO uint32_t POWER; /*!< Peripheral power control. */
717 /* ================================================================================ */
718 /* ================ TIMER ================ */
719 /* ================================================================================ */
723 * @brief Timer 0. (TIMER)
726 typedef struct { /*!< TIMER Structure */
727 __O uint32_t TASKS_START; /*!< Start Timer. */
728 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
729 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
730 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
731 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
732 __I uint32_t RESERVED0[11];
733 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
734 __I uint32_t RESERVED1[60];
735 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
736 __I uint32_t RESERVED2[44];
737 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
738 __I uint32_t RESERVED3[64];
739 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
740 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
741 __I uint32_t RESERVED4[126];
742 __IO uint32_t MODE; /*!< Timer Mode selection. */
743 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
744 __I uint32_t RESERVED5;
745 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
746 clock frequency is divided by 2^SCALE. */
747 __I uint32_t RESERVED6[11];
748 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
749 __I uint32_t RESERVED7[683];
750 __IO uint32_t POWER; /*!< Peripheral power control. */
754 /* ================================================================================ */
755 /* ================ RTC ================ */
756 /* ================================================================================ */
760 * @brief Real time counter 0. (RTC)
763 typedef struct { /*!< RTC Structure */
764 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
765 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
766 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
767 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
768 __I uint32_t RESERVED0[60];
769 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
770 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
771 __I uint32_t RESERVED1[14];
772 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
773 __I uint32_t RESERVED2[109];
774 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
775 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
776 __I uint32_t RESERVED3[13];
777 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
778 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
779 the value of EVTEN. */
780 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
781 gives the value of EVTEN. */
782 __I uint32_t RESERVED4[110];
783 __I uint32_t COUNTER; /*!< Current COUNTER value. */
784 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
785 Must be written when RTC is STOPed. */
786 __I uint32_t RESERVED5[13];
787 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
788 __I uint32_t RESERVED6[683];
789 __IO uint32_t POWER; /*!< Peripheral power control. */
793 /* ================================================================================ */
794 /* ================ TEMP ================ */
795 /* ================================================================================ */
799 * @brief Temperature Sensor. (TEMP)
802 typedef struct { /*!< TEMP Structure */
803 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
804 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
805 __I uint32_t RESERVED0[62];
806 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
807 __I uint32_t RESERVED1[128];
808 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
809 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
810 __I uint32_t RESERVED2[127];
811 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
812 __I uint32_t RESERVED3[700];
813 __IO uint32_t POWER; /*!< Peripheral power control. */
817 /* ================================================================================ */
818 /* ================ RNG ================ */
819 /* ================================================================================ */
823 * @brief Random Number Generator. (RNG)
826 typedef struct { /*!< RNG Structure */
827 __O uint32_t TASKS_START; /*!< Start the random number generator. */
828 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
829 __I uint32_t RESERVED0[62];
830 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
831 __I uint32_t RESERVED1[63];
832 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
833 __I uint32_t RESERVED2[64];
834 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
835 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
836 __I uint32_t RESERVED3[126];
837 __IO uint32_t CONFIG; /*!< Configuration register. */
838 __I uint32_t VALUE; /*!< RNG random number. */
839 __I uint32_t RESERVED4[700];
840 __IO uint32_t POWER; /*!< Peripheral power control. */
844 /* ================================================================================ */
845 /* ================ ECB ================ */
846 /* ================================================================================ */
850 * @brief AES ECB Mode Encryption. (ECB)
853 typedef struct { /*!< ECB Structure */
854 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
855 will not initiate a new encryption and the ERRORECB event will
857 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
858 this will will trigger the ERRORECB event. */
859 __I uint32_t RESERVED0[62];
860 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
861 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
863 __I uint32_t RESERVED1[127];
864 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
865 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
866 __I uint32_t RESERVED2[126];
867 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
868 __I uint32_t RESERVED3[701];
869 __IO uint32_t POWER; /*!< Peripheral power control. */
873 /* ================================================================================ */
874 /* ================ AAR ================ */
875 /* ================================================================================ */
879 * @brief Accelerated Address Resolver. (AAR)
882 typedef struct { /*!< AAR Structure */
883 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
885 __I uint32_t RESERVED0;
886 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
887 __I uint32_t RESERVED1[61];
888 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
889 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
890 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
891 __I uint32_t RESERVED2[126];
892 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
893 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
894 __I uint32_t RESERVED3[61];
895 __I uint32_t STATUS; /*!< Resolution status. */
896 __I uint32_t RESERVED4[63];
897 __IO uint32_t ENABLE; /*!< Enable AAR. */
898 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
899 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
900 __I uint32_t RESERVED5;
901 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
902 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
903 during resolution. A minimum of 3 bytes must be reserved. */
904 __I uint32_t RESERVED6[697];
905 __IO uint32_t POWER; /*!< Peripheral power control. */
909 /* ================================================================================ */
910 /* ================ CCM ================ */
911 /* ================================================================================ */
915 * @brief AES CCM Mode Encryption. (CCM)
918 typedef struct { /*!< CCM Structure */
919 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
920 itself when completed. */
921 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
923 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
924 __I uint32_t RESERVED0[61];
925 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
926 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
927 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
928 __I uint32_t RESERVED1[61];
929 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
930 __I uint32_t RESERVED2[64];
931 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
932 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
933 __I uint32_t RESERVED3[61];
934 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
935 __I uint32_t RESERVED4[63];
936 __IO uint32_t ENABLE; /*!< CCM enable. */
937 __IO uint32_t MODE; /*!< Operation mode. */
938 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
939 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
940 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
941 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
942 during resolution. A minimum of 43 bytes must be reserved. */
943 __I uint32_t RESERVED5[697];
944 __IO uint32_t POWER; /*!< Peripheral power control. */
948 /* ================================================================================ */
949 /* ================ WDT ================ */
950 /* ================================================================================ */
954 * @brief Watchdog Timer. (WDT)
957 typedef struct { /*!< WDT Structure */
958 __O uint32_t TASKS_START; /*!< Start the watchdog. */
959 __I uint32_t RESERVED0[63];
960 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
961 __I uint32_t RESERVED1[128];
962 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
963 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
964 __I uint32_t RESERVED2[61];
965 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
966 __I uint32_t REQSTATUS; /*!< Request status. */
967 __I uint32_t RESERVED3[63];
968 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
969 __IO uint32_t RREN; /*!< Reload request enable. */
970 __IO uint32_t CONFIG; /*!< Configuration register. */
971 __I uint32_t RESERVED4[60];
972 __O uint32_t RR[8]; /*!< Reload requests registers. */
973 __I uint32_t RESERVED5[631];
974 __IO uint32_t POWER; /*!< Peripheral power control. */
978 /* ================================================================================ */
979 /* ================ QDEC ================ */
980 /* ================================================================================ */
984 * @brief Rotary decoder. (QDEC)
987 typedef struct { /*!< QDEC Structure */
988 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
989 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
990 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
991 and clears the ACC registers. */
992 __I uint32_t RESERVED0[61];
993 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
994 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
995 ACC register different than zero. */
996 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
997 __I uint32_t RESERVED1[61];
998 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
999 __I uint32_t RESERVED2[64];
1000 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
1001 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
1002 __I uint32_t RESERVED3[125];
1003 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
1004 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
1005 __IO uint32_t SAMPLEPER; /*!< Sample period. */
1006 __I int32_t SAMPLE; /*!< Motion sample value. */
1007 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
1008 __I int32_t ACC; /*!< Accumulated valid transitions register. */
1009 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
1011 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
1012 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
1013 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
1014 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
1015 __I uint32_t RESERVED4[5];
1016 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
1017 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
1018 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
1020 __I uint32_t RESERVED5[684];
1021 __IO uint32_t POWER; /*!< Peripheral power control. */
1025 /* ================================================================================ */
1026 /* ================ LPCOMP ================ */
1027 /* ================================================================================ */
1031 * @brief Low power comparator. (LPCOMP)
1034 typedef struct { /*!< LPCOMP Structure */
1035 __O uint32_t TASKS_START; /*!< Start the comparator. */
1036 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
1037 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
1038 __I uint32_t RESERVED0[61];
1039 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
1040 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
1041 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
1042 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
1043 __I uint32_t RESERVED1[60];
1044 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
1045 __I uint32_t RESERVED2[64];
1046 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
1047 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
1048 __I uint32_t RESERVED3[61];
1049 __I uint32_t RESULT; /*!< Result of last compare. */
1050 __I uint32_t RESERVED4[63];
1051 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
1052 __IO uint32_t PSEL; /*!< Input pin select. */
1053 __IO uint32_t REFSEL; /*!< Reference select. */
1054 __IO uint32_t EXTREFSEL; /*!< External reference select. */
1055 __I uint32_t RESERVED5[4];
1056 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
1057 __I uint32_t RESERVED6[694];
1058 __IO uint32_t POWER; /*!< Peripheral power control. */
1062 /* ================================================================================ */
1063 /* ================ SWI ================ */
1064 /* ================================================================================ */
1068 * @brief SW Interrupts. (SWI)
1071 typedef struct { /*!< SWI Structure */
1072 __I uint32_t UNUSED; /*!< Unused. */
1076 /* ================================================================================ */
1077 /* ================ NVMC ================ */
1078 /* ================================================================================ */
1082 * @brief Non Volatile Memory Controller. (NVMC)
1085 typedef struct { /*!< NVMC Structure */
1086 __I uint32_t RESERVED0[256];
1087 __I uint32_t READY; /*!< Ready flag. */
1088 __I uint32_t RESERVED1[64];
1089 __IO uint32_t CONFIG; /*!< Configuration register. */
1090 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
1091 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
1092 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
1093 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
1097 /* ================================================================================ */
1098 /* ================ PPI ================ */
1099 /* ================================================================================ */
1103 * @brief PPI controller. (PPI)
1106 typedef struct { /*!< PPI Structure */
1107 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
1108 __I uint32_t RESERVED0[312];
1109 __IO uint32_t CHEN; /*!< Channel enable. */
1110 __IO uint32_t CHENSET; /*!< Channel enable set. */
1111 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
1112 __I uint32_t RESERVED1;
1113 PPI_CH_Type CH[16]; /*!< PPI Channel. */
1114 __I uint32_t RESERVED2[156];
1115 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
1119 /* ================================================================================ */
1120 /* ================ FICR ================ */
1121 /* ================================================================================ */
1125 * @brief Factory Information Configuration. (FICR)
1128 typedef struct { /*!< FICR Structure */
1129 __I uint32_t RESERVED0[4];
1130 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
1131 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
1132 __I uint32_t RESERVED1[4];
1133 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
1134 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
1135 __I uint32_t RESERVED2;
1136 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
1139 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
1140 kept for backward compatinility purposes. Use SIZERAMBLOCKS
1142 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
1144 __I uint32_t RESERVED3[5];
1145 __I uint32_t CONFIGID; /*!< Configuration identifier. */
1146 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
1147 __I uint32_t RESERVED4[6];
1148 __I uint32_t ER[4]; /*!< Encryption root. */
1149 __I uint32_t IR[4]; /*!< Identity root. */
1150 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
1151 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
1152 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
1153 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
1155 __I uint32_t RESERVED5[10];
1156 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
1158 FICR_INFO_Type INFO; /*!< Device info */
1162 /* ================================================================================ */
1163 /* ================ UICR ================ */
1164 /* ================================================================================ */
1168 * @brief User Information Configuration. (UICR)
1171 typedef struct { /*!< UICR Structure */
1172 __IO uint32_t CLENR0; /*!< Length of code region 0. */
1173 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
1174 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
1175 __I uint32_t RESERVED0;
1176 __I uint32_t FWID; /*!< Firmware ID. */
1177 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
1181 /* ================================================================================ */
1182 /* ================ GPIO ================ */
1183 /* ================================================================================ */
1187 * @brief General purpose input and output. (GPIO)
1190 typedef struct { /*!< GPIO Structure */
1191 __I uint32_t RESERVED0[321];
1192 __IO uint32_t OUT; /*!< Write GPIO port. */
1193 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
1194 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
1195 __I uint32_t IN; /*!< Read GPIO port. */
1196 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
1197 __IO uint32_t DIRSET; /*!< DIR set register. */
1198 __IO uint32_t DIRCLR; /*!< DIR clear register. */
1199 __I uint32_t RESERVED1[120];
1200 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
1204 /* -------------------- End of section using anonymous unions ------------------- */
1205 #if defined(__CC_ARM)
1207 #elif defined(__ICCARM__)
1208 /* leave anonymous unions enabled */
1209 #elif defined(__GNUC__)
1210 /* anonymous unions are enabled by default */
1211 #elif defined(__TMS470__)
1212 /* anonymous unions are enabled by default */
1213 #elif defined(__TASKING__)
1214 #pragma warning restore
1216 #warning Not supported compiler type
1222 /* ================================================================================ */
1223 /* ================ Peripheral memory map ================ */
1224 /* ================================================================================ */
1226 #define NRF_POWER_BASE 0x40000000UL
1227 #define NRF_CLOCK_BASE 0x40000000UL
1228 #define NRF_MPU_BASE 0x40000000UL
1229 #define NRF_PU_BASE 0x40000000UL
1230 #define NRF_AMLI_BASE 0x40000000UL
1231 #define NRF_RADIO_BASE 0x40001000UL
1232 #define NRF_UART0_BASE 0x40002000UL
1233 #define NRF_SPI0_BASE 0x40003000UL
1234 #define NRF_TWI0_BASE 0x40003000UL
1235 #define NRF_SPI1_BASE 0x40004000UL
1236 #define NRF_TWI1_BASE 0x40004000UL
1237 #define NRF_SPIS1_BASE 0x40004000UL
1238 #define NRF_SPIM1_BASE 0x40004000UL
1239 #define NRF_GPIOTE_BASE 0x40006000UL
1240 #define NRF_ADC_BASE 0x40007000UL
1241 #define NRF_TIMER0_BASE 0x40008000UL
1242 #define NRF_TIMER1_BASE 0x40009000UL
1243 #define NRF_TIMER2_BASE 0x4000A000UL
1244 #define NRF_RTC0_BASE 0x4000B000UL
1245 #define NRF_TEMP_BASE 0x4000C000UL
1246 #define NRF_RNG_BASE 0x4000D000UL
1247 #define NRF_ECB_BASE 0x4000E000UL
1248 #define NRF_AAR_BASE 0x4000F000UL
1249 #define NRF_CCM_BASE 0x4000F000UL
1250 #define NRF_WDT_BASE 0x40010000UL
1251 #define NRF_RTC1_BASE 0x40011000UL
1252 #define NRF_QDEC_BASE 0x40012000UL
1253 #define NRF_LPCOMP_BASE 0x40013000UL
1254 #define NRF_SWI_BASE 0x40014000UL
1255 #define NRF_NVMC_BASE 0x4001E000UL
1256 #define NRF_PPI_BASE 0x4001F000UL
1257 #define NRF_FICR_BASE 0x10000000UL
1258 #define NRF_UICR_BASE 0x10001000UL
1259 #define NRF_GPIO_BASE 0x50000000UL
1262 /* ================================================================================ */
1263 /* ================ Peripheral declaration ================ */
1264 /* ================================================================================ */
1266 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
1267 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
1268 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
1269 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
1270 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
1271 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
1272 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
1273 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
1274 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
1275 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
1276 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
1277 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
1278 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
1279 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
1280 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
1281 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
1282 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
1283 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
1284 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
1285 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
1286 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
1287 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
1288 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
1289 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
1290 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
1291 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
1292 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
1293 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
1294 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
1295 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
1296 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
1297 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
1298 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
1299 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
1302 /** @} */ /* End of group Device_Peripheral_Registers */
1303 /** @} */ /* End of group nRF51 */
1304 /** @} */ /* End of group Nordic Semiconductor */
1311 #endif /* nRF51_H */
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