1 /*******************************************************************************
3 * This software is supplied by Renesas Electronics Corporation and is only
4 * intended for use with Renesas products. No other uses are authorized. This
5 * software is owned by Renesas Electronics Corporation and is protected under
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7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16 * Renesas reserves the right, without notice, to make changes to this software
17 * and to discontinue the availability of this software. By using this software,
18 * you agree to the additional terms and conditions found by accessing the
20 * http://www.renesas.com/disclaimer
21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
22 *******************************************************************************/
23 /*******************************************************************************
24 * File Name : usb1_host_dmacdrv.c
26 * $Date:: 2014-07-09 16:29:19 +0900#$
31 * Description : RZ/A1H R7S72100 USB Sample Program
34 *******************************************************************************/
37 /*******************************************************************************
38 Includes <System Includes> , "Project Includes"
39 *******************************************************************************/
40 #include "r_typedefs.h"
42 #include "rza_io_regrw.h"
43 #include "usb1_host_dmacdrv.h"
46 /*******************************************************************************
48 *******************************************************************************/
51 /*******************************************************************************
53 *******************************************************************************/
54 #define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
56 /* ==== Request setting information for on-chip peripheral module ==== */
57 typedef enum dmac_peri_req_reg_type
64 } dmac_peri_req_reg_type_t;
67 /*******************************************************************************
68 Imported global variables and functions (from other files)
69 *******************************************************************************/
72 /*******************************************************************************
73 Exported global variables and functions (to be accessed by other files)
74 *******************************************************************************/
77 /*******************************************************************************
78 Private global variables and functions
79 *******************************************************************************/
80 /* ==== Prototype declaration ==== */
82 /* ==== Global variable ==== */
83 /* On-chip peripheral module request setting table */
84 static const uint8_t usb1_host_dmac_peri_req_init_table[8][5] =
86 /* MID,RID, AM,LVL,REQD */
87 { 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
88 { 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
89 { 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
90 { 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
91 { 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
92 { 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
93 { 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
94 { 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
98 /*******************************************************************************
99 * Function Name: usb1_host_DMAC3_PeriReqInit
100 * Description : Sets the register mode for DMA mode and the on-chip peripheral
101 * : module request for transfer request for DMAC channel 3.
102 * : Executes DMAC initial setting using the DMA information
103 * : specified by the argument *trans_info and the enabled/disabled
104 * : continuous transfer specified by the argument continuation.
105 * : Registers DMAC channel 3 interrupt handler function and sets
106 * : the interrupt priority level. Then enables transfer completion
108 * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
110 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
111 * : uint32_t continuation : Set continuous transfer to be valid
112 * : : after DMA transfer has been completed
113 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
114 * : DMAC_SAMPLE_SINGLE : Do not execute continuous
116 * : uint32_t request_factor : Factor for on-chip peripheral module
118 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
119 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
120 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
122 * : uint32_t req_direction : Setting value of CHCFG_n register
124 * Return Value : none
125 *******************************************************************************/
126 void usb1_host_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
127 uint32_t request_factor, uint32_t req_direction)
129 /* ==== Register mode ==== */
130 if (DMAC_MODE_REGISTER == dmamode)
132 /* ==== Next0 register set ==== */
133 DMAC3.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
134 DMAC3.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
135 DMAC3.N0TB_n = trans_info->count; /* Total transfer byte count */
137 /* DAD : Transfer destination address counting direction */
138 /* SAD : Transfer source address counting direction */
139 /* DDS : Transfer destination transfer size */
140 /* SDS : Transfer source transfer size */
141 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
142 trans_info->daddr_dir,
143 DMAC3_CHCFG_n_DAD_SHIFT,
145 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
146 trans_info->saddr_dir,
147 DMAC3_CHCFG_n_SAD_SHIFT,
149 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
150 trans_info->dst_size,
151 DMAC3_CHCFG_n_DDS_SHIFT,
153 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
154 trans_info->src_size,
155 DMAC3_CHCFG_n_SDS_SHIFT,
158 /* DMS : Register mode */
159 /* RSEL : Select Next0 register set */
160 /* SBE : No discharge of buffer data when aborted */
161 /* DEM : No DMA interrupt mask */
162 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
164 DMAC3_CHCFG_n_DMS_SHIFT,
166 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
168 DMAC3_CHCFG_n_RSEL_SHIFT,
170 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
172 DMAC3_CHCFG_n_SBE_SHIFT,
174 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
176 DMAC3_CHCFG_n_DEM_SHIFT,
179 /* ---- Continuous transfer ---- */
180 if (DMAC_SAMPLE_CONTINUATION == continuation)
182 /* REN : Execute continuous transfer */
183 /* RSW : Change register set when DMA transfer is completed. */
184 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
186 DMAC3_CHCFG_n_REN_SHIFT,
188 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
190 DMAC3_CHCFG_n_RSW_SHIFT,
193 /* ---- Single transfer ---- */
196 /* REN : Do not execute continuous transfer */
197 /* RSW : Do not change register set when DMA transfer is completed. */
198 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
200 DMAC3_CHCFG_n_REN_SHIFT,
202 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
204 DMAC3_CHCFG_n_RSW_SHIFT,
208 /* TM : Single transfer */
209 /* SEL : Channel setting */
210 /* HIEN, LOEN : On-chip peripheral module request */
211 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
213 DMAC3_CHCFG_n_TM_SHIFT,
215 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
217 DMAC3_CHCFG_n_SEL_SHIFT,
219 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
221 DMAC3_CHCFG_n_HIEN_SHIFT,
223 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
225 DMAC3_CHCFG_n_LOEN_SHIFT,
228 /* ---- Set factor by specified on-chip peripheral module request ---- */
229 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
230 usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
231 DMAC3_CHCFG_n_AM_SHIFT,
233 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
234 usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
235 DMAC3_CHCFG_n_LVL_SHIFT,
237 if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
239 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
240 usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
241 DMAC3_CHCFG_n_REQD_SHIFT,
246 RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
248 DMAC3_CHCFG_n_REQD_SHIFT,
251 RZA_IO_RegWrite_32(&DMAC23.DMARS,
252 usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
253 DMAC23_DMARS_CH3_RID_SHIFT,
254 DMAC23_DMARS_CH3_RID);
255 RZA_IO_RegWrite_32(&DMAC23.DMARS,
256 usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
257 DMAC23_DMARS_CH3_MID_SHIFT,
258 DMAC23_DMARS_CH3_MID);
260 /* PR : Round robin mode */
261 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
263 DMAC07_DCTRL_0_7_PR_SHIFT,
264 DMAC07_DCTRL_0_7_PR);
268 /*******************************************************************************
269 * Function Name: usb1_host_DMAC3_Open
270 * Description : Enables DMAC channel 3 transfer.
271 * Arguments : uint32_t req : DMAC request mode
272 * Return Value : 0 : Succeeded in enabling DMA transfer
273 * : -1 : Failed to enable DMA transfer (due to DMA operation)
274 *******************************************************************************/
275 int32_t usb1_host_DMAC3_Open (uint32_t req)
278 volatile uint8_t dummy;
281 if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
282 DMAC3_CHSTAT_n_EN_SHIFT,
283 DMAC3_CHSTAT_n_EN)) &&
284 (0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
285 DMAC3_CHSTAT_n_TACT_SHIFT,
286 DMAC3_CHSTAT_n_TACT)))
288 /* Clear Channel Status Register */
289 RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
291 DMAC3_CHCTRL_n_SWRST_SHIFT,
292 DMAC3_CHCTRL_n_SWRST);
293 dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n,
294 DMAC3_CHCTRL_n_SWRST_SHIFT,
295 DMAC3_CHCTRL_n_SWRST);
296 /* Enable DMA transfer */
297 RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
299 DMAC3_CHCTRL_n_SETEN_SHIFT,
300 DMAC3_CHCTRL_n_SETEN);
302 /* ---- Request by software ---- */
303 if (DMAC_REQ_MODE_SOFT == req)
305 /* DMA transfer Request by software */
306 RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
308 DMAC3_CHCTRL_n_STG_SHIFT,
322 /*******************************************************************************
323 * Function Name: usb1_host_DMAC3_Close
324 * Description : Aborts DMAC channel 3 transfer. Returns the remaining transfer
325 * : byte count at the time of DMA transfer abort to the argument
327 * Arguments : uint32_t * remain : Remaining transfer byte count when
328 * : : DMA transfer is aborted
329 * Return Value : none
330 *******************************************************************************/
331 void usb1_host_DMAC3_Close (uint32_t * remain)
334 /* ==== Abort transfer ==== */
335 RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
337 DMAC3_CHCTRL_n_CLREN_SHIFT,
338 DMAC3_CHCTRL_n_CLREN);
340 while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
341 DMAC3_CHSTAT_n_TACT_SHIFT,
342 DMAC3_CHSTAT_n_TACT))
344 /* Loop until transfer is aborted */
347 while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
348 DMAC3_CHSTAT_n_EN_SHIFT,
351 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
353 /* ==== Obtain remaining transfer byte count ==== */
354 *remain = DMAC3.CRTB_n;
357 /*******************************************************************************
358 * Function Name: usb1_host_DMAC3_Load_Set
359 * Description : Sets the transfer source address, transfer destination
360 * : address, and total transfer byte count respectively
361 * : specified by the argument src_addr, dst_addr, and count to
362 * : DMAC channel 3 as DMA transfer information.
363 * : Sets the register set selected by the CHCFG_n register
364 * : RSEL bit from the Next0 or Next1 register set.
365 * : This function should be called when DMA transfer of DMAC
366 * : channel 3 is aboted.
367 * Arguments : uint32_t src_addr : Transfer source address
368 * : uint32_t dst_addr : Transfer destination address
369 * : uint32_t count : Total transfer byte count
370 * Return Value : none
371 *******************************************************************************/
372 void usb1_host_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
376 /* Obtain register set in use */
377 reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
378 DMAC3_CHSTAT_n_SR_SHIFT,
384 /* ---- Next0 Register Set ---- */
385 DMAC3.N0SA_n = src_addr; /* Start address of transfer source */
386 DMAC3.N0DA_n = dst_addr; /* Start address of transfer destination */
387 DMAC3.N0TB_n = count; /* Total transfer byte count */
391 /* ---- Next1 Register Set ---- */
392 DMAC3.N1SA_n = src_addr; /* Start address of transfer source */
393 DMAC3.N1DA_n = dst_addr; /* Start address of transfer destination */
394 DMAC3.N1TB_n = count; /* Total transfer byte count */
398 /*******************************************************************************
399 * Function Name: usb1_host_DMAC4_PeriReqInit
400 * Description : Sets the register mode for DMA mode and the on-chip peripheral
401 * : module request for transfer request for DMAC channel 4.
402 * : Executes DMAC initial setting using the DMA information
403 * : specified by the argument *trans_info and the enabled/disabled
404 * : continuous transfer specified by the argument continuation.
405 * : Registers DMAC channel 4 interrupt handler function and sets
406 * : the interrupt priority level. Then enables transfer completion
408 * Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
410 * : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
411 * : uint32_t continuation : Set continuous transfer to be valid
412 * : : after DMA transfer has been completed
413 * : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
414 * : DMAC_SAMPLE_SINGLE : Do not execute continuous
416 * : uint32_t request_factor : Factor for on-chip peripheral module
418 * : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
419 * : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
420 * : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
422 * : uint32_t req_direction : Setting value of CHCFG_n register
424 * Return Value : none
425 *******************************************************************************/
426 void usb1_host_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
427 uint32_t request_factor, uint32_t req_direction)
429 /* ==== Register mode ==== */
430 if (DMAC_MODE_REGISTER == dmamode)
432 /* ==== Next0 register set ==== */
433 DMAC4.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
434 DMAC4.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
435 DMAC4.N0TB_n = trans_info->count; /* Total transfer byte count */
437 /* DAD : Transfer destination address counting direction */
438 /* SAD : Transfer source address counting direction */
439 /* DDS : Transfer destination transfer size */
440 /* SDS : Transfer source transfer size */
441 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
442 trans_info->daddr_dir,
443 DMAC4_CHCFG_n_DAD_SHIFT,
445 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
446 trans_info->saddr_dir,
447 DMAC4_CHCFG_n_SAD_SHIFT,
449 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
450 trans_info->dst_size,
451 DMAC4_CHCFG_n_DDS_SHIFT,
453 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
454 trans_info->src_size,
455 DMAC4_CHCFG_n_SDS_SHIFT,
458 /* DMS : Register mode */
459 /* RSEL : Select Next0 register set */
460 /* SBE : No discharge of buffer data when aborted */
461 /* DEM : No DMA interrupt mask */
462 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
464 DMAC4_CHCFG_n_DMS_SHIFT,
466 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
468 DMAC4_CHCFG_n_RSEL_SHIFT,
470 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
472 DMAC4_CHCFG_n_SBE_SHIFT,
474 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
476 DMAC4_CHCFG_n_DEM_SHIFT,
479 /* ---- Continuous transfer ---- */
480 if (DMAC_SAMPLE_CONTINUATION == continuation)
482 /* REN : Execute continuous transfer */
483 /* RSW : Change register set when DMA transfer is completed. */
484 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
486 DMAC4_CHCFG_n_REN_SHIFT,
488 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
490 DMAC4_CHCFG_n_RSW_SHIFT,
493 /* ---- Single transfer ---- */
496 /* REN : Do not execute continuous transfer */
497 /* RSW : Do not change register set when DMA transfer is completed. */
498 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
500 DMAC4_CHCFG_n_REN_SHIFT,
502 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
504 DMAC4_CHCFG_n_RSW_SHIFT,
508 /* TM : Single transfer */
509 /* SEL : Channel setting */
510 /* HIEN, LOEN : On-chip peripheral module request */
511 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
513 DMAC4_CHCFG_n_TM_SHIFT,
515 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
517 DMAC4_CHCFG_n_SEL_SHIFT,
519 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
521 DMAC4_CHCFG_n_HIEN_SHIFT,
523 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
525 DMAC4_CHCFG_n_LOEN_SHIFT,
528 /* ---- Set factor by specified on-chip peripheral module request ---- */
529 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
530 usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
531 DMAC4_CHCFG_n_AM_SHIFT,
533 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
534 usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
535 DMAC4_CHCFG_n_LVL_SHIFT,
537 if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
539 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
540 usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
541 DMAC4_CHCFG_n_REQD_SHIFT,
546 RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
548 DMAC4_CHCFG_n_REQD_SHIFT,
551 RZA_IO_RegWrite_32(&DMAC45.DMARS,
552 usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
553 DMAC45_DMARS_CH4_RID_SHIFT,
554 DMAC45_DMARS_CH4_RID);
555 RZA_IO_RegWrite_32(&DMAC45.DMARS,
556 usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
557 DMAC45_DMARS_CH4_MID_SHIFT,
558 DMAC45_DMARS_CH4_MID);
560 /* PR : Round robin mode */
561 RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
563 DMAC07_DCTRL_0_7_PR_SHIFT,
564 DMAC07_DCTRL_0_7_PR);
568 /*******************************************************************************
569 * Function Name: usb1_host_DMAC4_Open
570 * Description : Enables DMAC channel 4 transfer.
571 * Arguments : uint32_t req : DMAC request mode
572 * Return Value : 0 : Succeeded in enabling DMA transfer
573 * : -1 : Failed to enable DMA transfer (due to DMA operation)
574 *******************************************************************************/
575 int32_t usb1_host_DMAC4_Open (uint32_t req)
578 volatile uint8_t dummy;
581 if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
582 DMAC4_CHSTAT_n_EN_SHIFT,
583 DMAC4_CHSTAT_n_EN)) &&
584 (0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
585 DMAC4_CHSTAT_n_TACT_SHIFT,
586 DMAC4_CHSTAT_n_TACT)))
588 /* Clear Channel Status Register */
589 RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
591 DMAC4_CHCTRL_n_SWRST_SHIFT,
592 DMAC4_CHCTRL_n_SWRST);
593 dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n,
594 DMAC4_CHCTRL_n_SWRST_SHIFT,
595 DMAC4_CHCTRL_n_SWRST);
596 /* Enable DMA transfer */
597 RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
599 DMAC4_CHCTRL_n_SETEN_SHIFT,
600 DMAC4_CHCTRL_n_SETEN);
602 /* ---- Request by software ---- */
603 if (DMAC_REQ_MODE_SOFT == req)
605 /* DMA transfer Request by software */
606 RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
608 DMAC4_CHCTRL_n_STG_SHIFT,
622 /*******************************************************************************
623 * Function Name: usb1_host_DMAC4_Close
624 * Description : Aborts DMAC channel 4 transfer. Returns the remaining transfer
625 * : byte count at the time of DMA transfer abort to the argument
627 * Arguments : uint32_t * remain : Remaining transfer byte count when
628 * : : DMA transfer is aborted
629 * Return Value : none
630 *******************************************************************************/
631 void usb1_host_DMAC4_Close (uint32_t * remain)
634 /* ==== Abort transfer ==== */
635 RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
637 DMAC4_CHCTRL_n_CLREN_SHIFT,
638 DMAC4_CHCTRL_n_CLREN);
640 while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
641 DMAC4_CHSTAT_n_TACT_SHIFT,
642 DMAC4_CHSTAT_n_TACT))
644 /* Loop until transfer is aborted */
647 while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
648 DMAC4_CHSTAT_n_EN_SHIFT,
651 /* Loop until 0 is set in EN before checking the remaining transfer byte count */
653 /* ==== Obtain remaining transfer byte count ==== */
654 *remain = DMAC4.CRTB_n;
657 /*******************************************************************************
658 * Function Name: usb1_host_DMAC4_Load_Set
659 * Description : Sets the transfer source address, transfer destination
660 * : address, and total transfer byte count respectively
661 * : specified by the argument src_addr, dst_addr, and count to
662 * : DMAC channel 4 as DMA transfer information.
663 * : Sets the register set selected by the CHCFG_n register
664 * : RSEL bit from the Next0 or Next1 register set.
665 * : This function should be called when DMA transfer of DMAC
666 * : channel 4 is aboted.
667 * Arguments : uint32_t src_addr : Transfer source address
668 * : uint32_t dst_addr : Transfer destination address
669 * : uint32_t count : Total transfer byte count
670 * Return Value : none
671 *******************************************************************************/
672 void usb1_host_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
676 /* Obtain register set in use */
677 reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
678 DMAC4_CHSTAT_n_SR_SHIFT,
684 /* ---- Next0 Register Set ---- */
685 DMAC4.N0SA_n = src_addr; /* Start address of transfer source */
686 DMAC4.N0DA_n = dst_addr; /* Start address of transfer destination */
687 DMAC4.N0TB_n = count; /* Total transfer byte count */
691 /* ---- Next1 Register Set ---- */
692 DMAC4.N1SA_n = src_addr; /* Start address of transfer source */
693 DMAC4.N1DA_n = dst_addr; /* Start address of transfer destination */
694 DMAC4.N1TB_n = count; /* Total transfer byte count */