1 ;---------------------------------------------------------------------------;
2 ; Software implemented UART module ;
3 ; (C)ChaN, 2005 (http://elm-chan.org/) ;
4 ;---------------------------------------------------------------------------;
7 ; 1MHz 2MHz 4MHz 6MHz 8MHz 10MHz 12MHz 16MHz 20MHz
8 ; 2.4kbps 138 - - - - - - - -
9 ; 4.8kbps 68 138 - - - - - - -
10 ; 9.6kbps 33 68 138 208 - - - - -
11 ; 19.2kbps - 33 68 102 138 173 208 - -
12 ; 38.4kbps - - 33 50 68 85 102 138 172
13 ; 57.6kbps - - 21 33 44 56 68 91 114
14 ; 115.2kbps - - - - 21 27 33 44 56
20 #define BPS 102 /* Bit delay. (see above table) */
21 #define BIDIR 0 /* 0:Separated Tx/Rx, 1:Shared Tx/Rx */
23 #define OUT_1 sbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT /* Output 1 */
24 #define OUT_0 cbi _SFR_IO_ADDR(SUART_OUT_PORT), SUART_OUT_BIT /* Output 0 */
25 #define SKIP_IN_1 sbis _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT /* Skip if 1 */
26 #define SKIP_IN_0 sbic _SFR_IO_ADDR(SUART_IN_PIN), SUART_IN_BIT /* Skip if 0 */
34 .macro _MOVW dh,dl, sh,sl
43 .macro _MOVW dh,dl, sh,sl
51 ;---------------------------------------------------------------------------;
52 ; Transmit a byte in serial format of N81
54 ;Prototype: void xmit (uint8_t data);
61 ldi r23, BPS-1 ;Pre-idle time for bidirectional data line
65 in r0, _SFR_IO_ADDR(SREG) ;Save flags
67 com r24 ;C = start bit
68 ldi r25, 10 ;Bit counter
69 cli ;Start critical section
71 1: ldi r23, BPS-1 ;----- Bit transferring loop
72 2: dec r23 ;Wait for a bit time
74 brcs 3f ;MISO = bit to be sent
78 4: lsr r24 ;Get next bit into C
79 dec r25 ;All bits sent?
80 brne 1b ; no, coutinue
82 out _SFR_IO_ADDR(SREG), r0 ;End of critical section
88 ;---------------------------------------------------------------------------;
91 ;Prototype: uint8_t rcvr (void);
97 in r0, _SFR_IO_ADDR(SREG) ;Save flags
99 ldi r24, 0x80 ;Receiving shift reg
100 cli ;Start critical section
102 1: SKIP_IN_1 ;Wait for idle
104 2: SKIP_IN_0 ;Wait for start bit
106 ldi r25, BPS/2 ;Wait for half bit time
110 4: ldi r25, BPS ;----- Bit receiving loop
111 5: dec r25 ;Wait for a bit time
114 SKIP_IN_0 ;Get a data bit into r24.7
116 brcc 4b ;All bits received? no, continue
118 out _SFR_IO_ADDR(SREG), r0 ;End of critical section
123 ; Not wait for start bit. This should be called after detecting start bit.
127 in r0, _SFR_IO_ADDR(SREG) ;Save flags
129 ldi r24, 0x80 ;Receiving shift reg
130 cli ;Start critical section
132 ;1: SKIP_IN_1 ;Wait for idle
134 ;2: SKIP_IN_0 ;Wait for start bit
136 ldi r25, BPS/2 ;Wait for half bit time
140 4: ldi r25, BPS ;----- Bit receiving loop
141 5: dec r25 ;Wait for a bit time
144 SKIP_IN_0 ;Get a data bit into r24.7
146 brcc 4b ;All bits received? no, continue
148 ldi r25, BPS/2 ;Wait for half bit time
151 7: SKIP_IN_1 ;Wait for stop bit
154 out _SFR_IO_ADDR(SREG), r0 ;End of critical section