tmk_core/protocol/arm_atsam/d51_util.h

   1 /*
   2 Copyright 2018 Massdrop Inc.
   3
   4 This program is free software: you can redistribute it and/or modify
   5 it under the terms of the GNU General Public License as published by
   6 the Free Software Foundation, either version 2 of the License, or
   7 (at your option) any later version.
   8
   9 This program is distributed in the hope that it will be useful,
  10 but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 GNU General Public License for more details.
  13
  14 You should have received a copy of the GNU General Public License
  15 along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18 #ifndef _D51_UTIL_H_
  19 #define _D51_UTIL_H_
  20
  21 #include "samd51j18a.h"
  22
  23 //TODO: PS: Should bring these ports out to keyboard level configuration
  24
  25 //Debug LED PA27
  26 #define led_ena REG_PORT_DIRSET0 = 0x08000000 //PA27 Output
  27 #define led_on  REG_PORT_OUTSET0 = 0x08000000 //PA27 High
  28 #define led_off REG_PORT_OUTCLR0 = 0x08000000 //PA27 Low
  29
  30 //Debug Port PB30
  31 #define m15_ena REG_PORT_DIRSET1 = 0x40000000 //PB30 Output
  32 #define m15_on  REG_PORT_OUTSET1 = 0x40000000 //PB30 High
  33 #define m15_off REG_PORT_OUTCLR1 = 0x40000000 //PB30 Low
  34
  35 //Debug Port PB23
  36 #define m27_ena REG_PORT_DIRSET1 = 0x800000 //PB23 Output
  37 #define m27_on  REG_PORT_OUTSET1 = 0x800000 //PB23 High
  38 #define m27_off REG_PORT_OUTCLR1 = 0x800000 //PB23 Low
  39
  40 //Debug Port PB31
  41 #define m28_ena REG_PORT_DIRSET1 = 0x80000000 //PB31 Output
  42 #define m28_on  REG_PORT_OUTSET1 = 0x80000000 //PB31 High
  43 #define m28_off REG_PORT_OUTCLR1 = 0x80000000 //PB31 Low
  44
  45 #define m15_loop(M15X) {uint8_t M15L=M15X; while(M15L--){m15_on;CLK_delay_us(1);m15_off;}}
  46
  47 void m15_print(uint32_t x);
  48 void dled_print(uint32_t x, uint8_t long_pause);
  49
  50 void debug_code_init(void);
  51 void debug_code_disable(void);
  52
  53 #ifdef DEBUG_BOOT_TRACING
  54
  55 #define DBGC(n) debug_code = n
  56
  57 extern volatile uint32_t debug_code;
  58
  59 enum debug_code_list {
  60     DC_UNSET = 0,
  61     DC_CLK_INIT_BEGIN,
  62     DC_CLK_INIT_COMPLETE,
  63     DC_CLK_SET_I2C1_FREQ_BEGIN,
  64     DC_CLK_SET_I2C1_FREQ_COMPLETE,
  65     DC_CLK_SET_I2C0_FREQ_BEGIN,
  66     DC_CLK_SET_I2C0_FREQ_COMPLETE,
  67     DC_CLK_SET_SPI_FREQ_BEGIN,
  68     DC_CLK_SET_SPI_FREQ_COMPLETE,
  69     DC_CLK_ENABLE_TIMEBASE_BEGIN,
  70     DC_CLK_ENABLE_TIMEBASE_SYNC_ENABLE,
  71     DC_CLK_ENABLE_TIMEBASE_SYNC_SWRST_1,
  72     DC_CLK_ENABLE_TIMEBASE_SYNC_SWRST_2,
  73     DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN,
  74     DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE,
  75     DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1,
  76     DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2,
  77     DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB,
  78     DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0,
  79     DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE,
  80     DC_CLK_ENABLE_TIMEBASE_TC5_BEGIN,
  81     DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_DISABLE,
  82     DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_SWRST_1,
  83     DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_SWRST_2,
  84     DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_CLTRB,
  85     DC_CLK_ENABLE_TIMEBASE_TC5_COMPLETE,
  86     DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN,
  87     DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE,
  88     DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1,
  89     DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2,
  90     DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE,
  91     DC_CLK_ENABLE_TIMEBASE_EVSYS_BEGIN,
  92     DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE,
  93     DC_CLK_ENABLE_TIMEBASE_COMPLETE,
  94     DC_CLK_SET_GCLK_FREQ_BEGIN,
  95     DC_CLK_SET_GCLK_FREQ_SYNC_1,
  96     DC_CLK_SET_GCLK_FREQ_SYNC_2,
  97     DC_CLK_SET_GCLK_FREQ_SYNC_3,
  98     DC_CLK_SET_GCLK_FREQ_SYNC_4,
  99     DC_CLK_SET_GCLK_FREQ_SYNC_5,
 100     DC_CLK_SET_GCLK_FREQ_COMPLETE,
 101     DC_CLK_INIT_OSC_BEGIN,
 102     DC_CLK_INIT_OSC_SYNC_1,
 103     DC_CLK_INIT_OSC_SYNC_2,
 104     DC_CLK_INIT_OSC_SYNC_3,
 105     DC_CLK_INIT_OSC_SYNC_4,
 106     DC_CLK_INIT_OSC_SYNC_5,
 107     DC_CLK_INIT_OSC_COMPLETE,
 108     DC_CLK_RESET_TIME_BEGIN,
 109     DC_CLK_RESET_TIME_COMPLETE,
 110     DC_CLK_OSC_INIT_BEGIN,
 111     DC_CLK_OSC_INIT_XOSC0_SYNC,
 112     DC_CLK_OSC_INIT_DPLL_SYNC_DISABLE,
 113     DC_CLK_OSC_INIT_DPLL_SYNC_RATIO,
 114     DC_CLK_OSC_INIT_DPLL_SYNC_ENABLE,
 115     DC_CLK_OSC_INIT_DPLL_WAIT_LOCK,
 116     DC_CLK_OSC_INIT_DPLL_WAIT_CLKRDY,
 117     DC_CLK_OSC_INIT_GCLK_SYNC_GENCTRL0,
 118     DC_CLK_OSC_INIT_COMPLETE,
 119     DC_SPI_INIT_BEGIN,
 120     DC_SPI_WRITE_DRE,
 121     DC_SPI_WRITE_TXC_1,
 122     DC_SPI_WRITE_TXC_2,
 123     DC_SPI_SYNC_ENABLING,
 124     DC_SPI_INIT_COMPLETE,
 125     DC_PORT_DETECT_INIT_BEGIN,
 126     DC_PORT_DETECT_INIT_FAILED,
 127     DC_PORT_DETECT_INIT_COMPLETE,
 128     DC_USB_RESET_BEGIN,
 129     DC_USB_RESET_COMPLETE,
 130     DC_USB_SET_HOST_BY_VOLTAGE_BEGIN,
 131     DC_USB_SET_HOST_5V_LOW_WAITING,
 132     DC_USB_SET_HOST_BY_VOLTAGE_COMPLETE,
 133     DC_USB_CONFIGURE_BEGIN,
 134     DC_USB_CONFIGURE_GET_SERIAL,
 135     DC_USB_CONFIGURE_COMPLETE,
 136     DC_USB_WRITE2422_BLOCK_BEGIN,
 137     DC_USB_WRITE2422_BLOCK_SYNC_SYSOP,
 138     DC_USB_WRITE2422_BLOCK_COMPLETE,
 139     DC_ADC0_CLOCK_INIT_BEGIN,
 140     DC_ADC0_CLOCK_INIT_COMPLETE,
 141     DC_ADC0_INIT_BEGIN,
 142     DC_ADC0_SWRST_SYNCING_1,
 143     DC_ADC0_SWRST_SYNCING_2,
 144     DC_ADC0_AVGCTRL_SYNCING_1,
 145     DC_ADC0_AVGCTRL_SYNCING_2,
 146     DC_ADC0_SAMPCTRL_SYNCING_1,
 147     DC_ADC0_ENABLE_SYNCING_1,
 148     DC_ADC0_INIT_COMPLETE,
 149     DC_I2C0_INIT_BEGIN,
 150     DC_I2C0_INIT_SYNC_ENABLING,
 151     DC_I2C0_INIT_SYNC_SYSOP,
 152     DC_I2C0_INIT_WAIT_IDLE,
 153     DC_I2C0_INIT_COMPLETE,
 154     DC_I2C1_INIT_BEGIN,
 155     DC_I2C1_INIT_SYNC_ENABLING,
 156     DC_I2C1_INIT_SYNC_SYSOP,
 157     DC_I2C1_INIT_WAIT_IDLE,
 158     DC_I2C1_INIT_COMPLETE,
 159     DC_I2C3733_INIT_CONTROL_BEGIN,
 160     DC_I2C3733_INIT_CONTROL_COMPLETE,
 161     DC_I2C3733_INIT_DRIVERS_BEGIN,
 162     DC_I2C3733_INIT_DRIVERS_COMPLETE,
 163     DC_I2C_DMAC_LED_INIT_BEGIN,
 164     DC_I2C_DMAC_LED_INIT_COMPLETE,
 165     DC_I2C3733_CONTROL_SET_BEGIN,
 166     DC_I2C3733_CONTROL_SET_COMPLETE,
 167     DC_LED_MATRIX_INIT_BEGIN,
 168     DC_LED_MATRIX_INIT_COMPLETE,
 169     DC_USB2422_INIT_BEGIN,
 170     DC_USB2422_INIT_WAIT_5V_LOW,
 171     DC_USB2422_INIT_OSC_SYNC_DISABLING,
 172     DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_1,
 173     DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_2,
 174     DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_3,
 175     DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_4,
 176     DC_USB2422_INIT_OSC_SYNC_DFLLMUL,
 177     DC_USB2422_INIT_OSC_SYNC_ENABLING,
 178     DC_USB2422_INIT_USB_SYNC_SWRST,
 179     DC_USB2422_INIT_USB_WAIT_SWRST,
 180     DC_USB2422_INIT_USB_SYNC_ENABLING,
 181     DC_USB2422_INIT_COMPLETE,
 182     DC_MAIN_UDC_START_BEGIN,
 183     DC_MAIN_UDC_START_COMPLETE,
 184     DC_MAIN_CDC_INIT_BEGIN,
 185     DC_MAIN_CDC_INIT_COMPLETE,
 186     /* Never change the order of error codes! Only add codes to end! */
 187 };
 188
 189 #else
 190
 191 #define DBGC(n) {}
 192
 193 #endif //DEBUG_BOOT_TRACING
 194
 195 #endif //_D51_UTIL_H_