tmk_core/protocol/arm_atsam/d51_util.h

   1 /*
   2 Copyright 2018 Massdrop Inc.
   3
   4 This program is free software: you can redistribute it and/or modify
   5 it under the terms of the GNU General Public License as published by
   6 the Free Software Foundation, either version 2 of the License, or
   7 (at your option) any later version.
   8
   9 This program is distributed in the hope that it will be useful,
  10 but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 GNU General Public License for more details.
  13
  14 You should have received a copy of the GNU General Public License
  15 along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18 #ifndef _D51_UTIL_H_
  19 #define _D51_UTIL_H_
  20
  21 #include "samd51j18a.h"
  22
  23 /* Debug LED */
  24 #if DEBUG_LED_ENABLE == 1
  25 #define DBG_LED_ENA PORT->Group[DEBUG_LED_PORT].DIRSET.reg = (1 << DEBUG_LED_PIN)
  26 #define DBG_LED_DIS PORT->Group[DEBUG_LED_PORT].DIRCLR.reg = (1 << DEBUG_LED_PIN)
  27 #define DBG_LED_ON  PORT->Group[DEBUG_LED_PORT].OUTSET.reg = (1 << DEBUG_LED_PIN)
  28 #define DBG_LED_OFF PORT->Group[DEBUG_LED_PORT].OUTCLR.reg = (1 << DEBUG_LED_PIN)
  29 #else
  30 #define DBG_LED_ENA
  31 #define DBG_LED_DIS
  32 #define DBG_LED_ON
  33 #define DBG_LED_OFF
  34 #endif
  35
  36 /* Debug Port 1 */
  37 #if DEBUG_PORT1_ENABLE == 1
  38 #define DBG_1_ENA PORT->Group[DEBUG_PORT1_PORT].DIRSET.reg = (1 << DEBUG_PORT1_PIN)
  39 #define DBG_1_DIS PORT->Group[DEBUG_PORT1_PORT].DIRCLR.reg = (1 << DEBUG_PORT1_PIN)
  40 #define DBG_1_ON  PORT->Group[DEBUG_PORT1_PORT].OUTSET.reg = (1 << DEBUG_PORT1_PIN)
  41 #define DBG_1_OFF PORT->Group[DEBUG_PORT1_PORT].OUTCLR.reg = (1 << DEBUG_PORT1_PIN)
  42 #else
  43 #define DBG_1_ENA
  44 #define DBG_1_DIS
  45 #define DBG_1_ON
  46 #define DBG_1_OFF
  47 #endif
  48
  49 /* Debug Port 2 */
  50 #if DEBUG_PORT2_ENABLE == 1
  51 #define DBG_2_ENA PORT->Group[DEBUG_PORT2_PORT].DIRSET.reg = (1 << DEBUG_PORT2_PIN)
  52 #define DBG_2_DIS PORT->Group[DEBUG_PORT2_PORT].DIRCLR.reg = (1 << DEBUG_PORT2_PIN)
  53 #define DBG_2_ON  PORT->Group[DEBUG_PORT2_PORT].OUTSET.reg = (1 << DEBUG_PORT2_PIN)
  54 #define DBG_2_OFF PORT->Group[DEBUG_PORT2_PORT].OUTCLR.reg = (1 << DEBUG_PORT2_PIN)
  55 #else
  56 #define DBG_2_ENA
  57 #define DBG_2_DIS
  58 #define DBG_2_ON
  59 #define DBG_2_OFF
  60 #endif
  61
  62 /* Debug Port 3 */
  63 #if DEBUG_PORT3_ENABLE == 1
  64 #define DBG_3_ENA PORT->Group[DEBUG_PORT3_PORT].DIRSET.reg = (1 << DEBUG_PORT3_PIN)
  65 #define DBG_3_DIS PORT->Group[DEBUG_PORT3_PORT].DIRCLR.reg = (1 << DEBUG_PORT3_PIN)
  66 #define DBG_3_ON  PORT->Group[DEBUG_PORT3_PORT].OUTSET.reg = (1 << DEBUG_PORT3_PIN)
  67 #define DBG_3_OFF PORT->Group[DEBUG_PORT3_PORT].OUTCLR.reg = (1 << DEBUG_PORT3_PIN)
  68 #else
  69 #define DBG_3_ENA
  70 #define DBG_3_DIS
  71 #define DBG_3_ON
  72 #define DBG_3_OFF
  73 #endif
  74
  75 void dbg_print(uint32_t x);
  76 void dled_print(uint32_t x, uint8_t long_pause);
  77
  78 void debug_code_init(void);
  79 void debug_code_disable(void);
  80
  81 #ifdef DEBUG_BOOT_TRACING_ENABLE
  82
  83 #define DBGC(n) debug_code = n
  84
  85 extern volatile uint32_t debug_code;
  86
  87 enum debug_code_list {
  88     DC_UNSET = 0,
  89     DC_CLK_INIT_BEGIN,
  90     DC_CLK_INIT_COMPLETE,
  91     DC_CLK_SET_I2C1_FREQ_BEGIN,
  92     DC_CLK_SET_I2C1_FREQ_COMPLETE,
  93     DC_CLK_SET_I2C0_FREQ_BEGIN,
  94     DC_CLK_SET_I2C0_FREQ_COMPLETE,
  95     DC_CLK_SET_SPI_FREQ_BEGIN,
  96     DC_CLK_SET_SPI_FREQ_COMPLETE,
  97     DC_CLK_ENABLE_TIMEBASE_BEGIN,
  98     DC_CLK_ENABLE_TIMEBASE_SYNC_ENABLE,
  99     DC_CLK_ENABLE_TIMEBASE_SYNC_SWRST_1,
 100     DC_CLK_ENABLE_TIMEBASE_SYNC_SWRST_2,
 101     DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN,
 102     DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE,
 103     DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1,
 104     DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2,
 105     DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB,
 106     DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0,
 107     DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE,
 108     DC_CLK_ENABLE_TIMEBASE_TC5_BEGIN,
 109     DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_DISABLE,
 110     DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_SWRST_1,
 111     DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_SWRST_2,
 112     DC_CLK_ENABLE_TIMEBASE_TC5_SYNC_CLTRB,
 113     DC_CLK_ENABLE_TIMEBASE_TC5_COMPLETE,
 114     DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN,
 115     DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE,
 116     DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1,
 117     DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2,
 118     DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE,
 119     DC_CLK_ENABLE_TIMEBASE_EVSYS_BEGIN,
 120     DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE,
 121     DC_CLK_ENABLE_TIMEBASE_COMPLETE,
 122     DC_CLK_SET_GCLK_FREQ_BEGIN,
 123     DC_CLK_SET_GCLK_FREQ_SYNC_1,
 124     DC_CLK_SET_GCLK_FREQ_SYNC_2,
 125     DC_CLK_SET_GCLK_FREQ_SYNC_3,
 126     DC_CLK_SET_GCLK_FREQ_SYNC_4,
 127     DC_CLK_SET_GCLK_FREQ_SYNC_5,
 128     DC_CLK_SET_GCLK_FREQ_COMPLETE,
 129     DC_CLK_INIT_OSC_BEGIN,
 130     DC_CLK_INIT_OSC_SYNC_1,
 131     DC_CLK_INIT_OSC_SYNC_2,
 132     DC_CLK_INIT_OSC_SYNC_3,
 133     DC_CLK_INIT_OSC_SYNC_4,
 134     DC_CLK_INIT_OSC_SYNC_5,
 135     DC_CLK_INIT_OSC_COMPLETE,
 136     DC_CLK_RESET_TIME_BEGIN,
 137     DC_CLK_RESET_TIME_COMPLETE,
 138     DC_CLK_OSC_INIT_BEGIN,
 139     DC_CLK_OSC_INIT_XOSC0_SYNC,
 140     DC_CLK_OSC_INIT_DPLL_SYNC_DISABLE,
 141     DC_CLK_OSC_INIT_DPLL_SYNC_RATIO,
 142     DC_CLK_OSC_INIT_DPLL_SYNC_ENABLE,
 143     DC_CLK_OSC_INIT_DPLL_WAIT_LOCK,
 144     DC_CLK_OSC_INIT_DPLL_WAIT_CLKRDY,
 145     DC_CLK_OSC_INIT_GCLK_SYNC_GENCTRL0,
 146     DC_CLK_OSC_INIT_COMPLETE,
 147     DC_SPI_INIT_BEGIN,
 148     DC_SPI_WRITE_DRE,
 149     DC_SPI_WRITE_TXC_1,
 150     DC_SPI_WRITE_TXC_2,
 151     DC_SPI_SYNC_ENABLING,
 152     DC_SPI_INIT_COMPLETE,
 153     DC_PORT_DETECT_INIT_BEGIN,
 154     DC_PORT_DETECT_INIT_FAILED,
 155     DC_PORT_DETECT_INIT_COMPLETE,
 156     DC_USB_RESET_BEGIN,
 157     DC_USB_RESET_COMPLETE,
 158     DC_USB_SET_HOST_BY_VOLTAGE_BEGIN,
 159     DC_USB_SET_HOST_5V_LOW_WAITING,
 160     DC_USB_SET_HOST_BY_VOLTAGE_COMPLETE,
 161     DC_USB_CONFIGURE_BEGIN,
 162     DC_USB_CONFIGURE_GET_SERIAL,
 163     DC_USB_CONFIGURE_COMPLETE,
 164     DC_USB_WRITE2422_BLOCK_BEGIN,
 165     DC_USB_WRITE2422_BLOCK_SYNC_SYSOP,
 166     DC_USB_WRITE2422_BLOCK_COMPLETE,
 167     DC_ADC0_CLOCK_INIT_BEGIN,
 168     DC_ADC0_CLOCK_INIT_COMPLETE,
 169     DC_ADC0_INIT_BEGIN,
 170     DC_ADC0_SWRST_SYNCING_1,
 171     DC_ADC0_SWRST_SYNCING_2,
 172     DC_ADC0_AVGCTRL_SYNCING_1,
 173     DC_ADC0_AVGCTRL_SYNCING_2,
 174     DC_ADC0_SAMPCTRL_SYNCING_1,
 175     DC_ADC0_ENABLE_SYNCING_1,
 176     DC_ADC0_INIT_COMPLETE,
 177     DC_I2C0_INIT_BEGIN,
 178     DC_I2C0_INIT_SYNC_ENABLING,
 179     DC_I2C0_INIT_SYNC_SYSOP,
 180     DC_I2C0_INIT_WAIT_IDLE,
 181     DC_I2C0_INIT_COMPLETE,
 182     DC_I2C1_INIT_BEGIN,
 183     DC_I2C1_INIT_SYNC_ENABLING,
 184     DC_I2C1_INIT_SYNC_SYSOP,
 185     DC_I2C1_INIT_WAIT_IDLE,
 186     DC_I2C1_INIT_COMPLETE,
 187     DC_I2C3733_INIT_CONTROL_BEGIN,
 188     DC_I2C3733_INIT_CONTROL_COMPLETE,
 189     DC_I2C3733_INIT_DRIVERS_BEGIN,
 190     DC_I2C3733_INIT_DRIVERS_COMPLETE,
 191     DC_I2C_DMAC_LED_INIT_BEGIN,
 192     DC_I2C_DMAC_LED_INIT_COMPLETE,
 193     DC_I2C3733_CONTROL_SET_BEGIN,
 194     DC_I2C3733_CONTROL_SET_COMPLETE,
 195     DC_LED_MATRIX_INIT_BEGIN,
 196     DC_LED_MATRIX_INIT_COMPLETE,
 197     DC_USB2422_INIT_BEGIN,
 198     DC_USB2422_INIT_WAIT_5V_LOW,
 199     DC_USB2422_INIT_OSC_SYNC_DISABLING,
 200     DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_1,
 201     DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_2,
 202     DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_3,
 203     DC_USB2422_INIT_OSC_SYNC_DFLLCTRLB_4,
 204     DC_USB2422_INIT_OSC_SYNC_DFLLMUL,
 205     DC_USB2422_INIT_OSC_SYNC_ENABLING,
 206     DC_USB2422_INIT_USB_SYNC_SWRST,
 207     DC_USB2422_INIT_USB_WAIT_SWRST,
 208     DC_USB2422_INIT_USB_SYNC_ENABLING,
 209     DC_USB2422_INIT_COMPLETE,
 210     DC_MAIN_UDC_START_BEGIN,
 211     DC_MAIN_UDC_START_COMPLETE,
 212     DC_MAIN_CDC_INIT_BEGIN,
 213     DC_MAIN_CDC_INIT_COMPLETE,
 214     /* Never change the order of error codes! Only add codes to end! */
 215 };
 216
 217 #else
 218
 219 #define DBGC(n) {}
 220
 221 #endif //DEBUG_BOOT_TRACING_ENABLE
 222
 223 #endif //_D51_UTIL_H_