tmk_core/protocol/arm_atsam/clks.c

   1 /*
   2 Copyright 2018 Massdrop Inc.
   3
   4 This program is free software: you can redistribute it and/or modify
   5 it under the terms of the GNU General Public License as published by
   6 the Free Software Foundation, either version 2 of the License, or
   7 (at your option) any later version.
   8
   9 This program is distributed in the hope that it will be useful,
  10 but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 GNU General Public License for more details.
  13
  14 You should have received a copy of the GNU General Public License
  15 along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18 #include "arm_atsam_protocol.h"
  19
  20 #include <string.h>
  21
  22 volatile clk_t system_clks;
  23 volatile uint64_t ms_clk;
  24 uint32_t usec_delay_mult;
  25 #define USEC_DELAY_LOOP_CYCLES 3 //Sum of instruction cycles in us delay loop
  26
  27 const uint32_t sercom_apbbase[] = {(uint32_t)SERCOM0,(uint32_t)SERCOM1,(uint32_t)SERCOM2,(uint32_t)SERCOM3,(uint32_t)SERCOM4,(uint32_t)SERCOM5};
  28 const uint8_t sercom_pchan[] = {7, 8, 23, 24, 34, 35};
  29
  30 #define USE_DPLL_IND    0
  31 #define USE_DPLL_DEF    GCLK_SOURCE_DPLL0
  32
  33 void CLK_oscctrl_init(void)
  34 {
  35     Oscctrl *posctrl = OSCCTRL;
  36     Gclk *pgclk = GCLK;
  37
  38     DBGC(DC_CLK_OSC_INIT_BEGIN);
  39
  40     //default setup on por
  41     system_clks.freq_dfll = FREQ_DFLL_DEFAULT;
  42     system_clks.freq_gclk[0] = system_clks.freq_dfll;
  43
  44     //configure and startup 16MHz xosc0
  45     posctrl->XOSCCTRL[0].bit.ENABLE = 0;
  46     posctrl->XOSCCTRL[0].bit.STARTUP = 0xD;
  47     posctrl->XOSCCTRL[0].bit.ENALC = 1;
  48     posctrl->XOSCCTRL[0].bit.IMULT = 5;
  49     posctrl->XOSCCTRL[0].bit.IPTAT = 3;
  50     posctrl->XOSCCTRL[0].bit.ONDEMAND = 0;
  51     posctrl->XOSCCTRL[0].bit.XTALEN = 1;
  52     posctrl->XOSCCTRL[0].bit.ENABLE = 1;
  53     while (posctrl->STATUS.bit.XOSCRDY0 == 0) { DBGC(DC_CLK_OSC_INIT_XOSC0_SYNC); }
  54     system_clks.freq_xosc0 = FREQ_XOSC0;
  55
  56     //configure and startup DPLL
  57     posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ENABLE = 0;
  58     while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_DISABLE); }
  59     posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.REFCLK = 2;              //select XOSC0 (16MHz)
  60     posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV = 7;                 //16 MHz / (2 * (7 + 1)) = 1 MHz
  61     posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR = PLL_RATIO;         //1 MHz * (PLL_RATIO(47) + 1) = 48MHz
  62     while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.DPLLRATIO) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_RATIO); }
  63     posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ONDEMAND = 0;
  64     posctrl->Dpll[USE_DPLL_IND].DPLLCTRLA.bit.ENABLE = 1;
  65     while (posctrl->Dpll[USE_DPLL_IND].DPLLSYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_OSC_INIT_DPLL_SYNC_ENABLE); }
  66     while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.LOCK == 0) { DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_LOCK); }
  67     while (posctrl->Dpll[USE_DPLL_IND].DPLLSTATUS.bit.CLKRDY == 0) { DBGC(DC_CLK_OSC_INIT_DPLL_WAIT_CLKRDY); }
  68     system_clks.freq_dpll[0] = (system_clks.freq_xosc0 / 2 / (posctrl->Dpll[USE_DPLL_IND].DPLLCTRLB.bit.DIV + 1)) * (posctrl->Dpll[USE_DPLL_IND].DPLLRATIO.bit.LDR + 1);
  69
  70     //change gclk0 to DPLL
  71     pgclk->GENCTRL[GEN_DPLL0].bit.SRC = USE_DPLL_DEF;
  72     while (pgclk->SYNCBUSY.bit.GENCTRL0) { DBGC(DC_CLK_OSC_INIT_GCLK_SYNC_GENCTRL0); }
  73
  74     system_clks.freq_gclk[0] = system_clks.freq_dpll[0];
  75
  76     usec_delay_mult = system_clks.freq_gclk[0] / (USEC_DELAY_LOOP_CYCLES * 1000000);
  77     if (usec_delay_mult < 1) usec_delay_mult = 1; //Never allow a multiplier of zero
  78
  79     DBGC(DC_CLK_OSC_INIT_COMPLETE);
  80 }
  81
  82 //configure for 1MHz (1 usec timebase)
  83 //call CLK_set_gclk_freq(GEN_TC45, FREQ_TC45_DEFAULT);
  84 uint32_t CLK_set_gclk_freq(uint8_t gclkn, uint32_t freq)
  85 {
  86     Gclk *pgclk = GCLK;
  87
  88     DBGC(DC_CLK_SET_GCLK_FREQ_BEGIN);
  89
  90     while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_1); }
  91     pgclk->GENCTRL[gclkn].bit.SRC = USE_DPLL_DEF;
  92     while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_2); }
  93     pgclk->GENCTRL[gclkn].bit.DIV = (uint8_t)(system_clks.freq_dpll[0] / freq);
  94     while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_3); }
  95     pgclk->GENCTRL[gclkn].bit.DIVSEL = 0;
  96     while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_4); }
  97     pgclk->GENCTRL[gclkn].bit.GENEN = 1;
  98     while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_SET_GCLK_FREQ_SYNC_5); }
  99     system_clks.freq_gclk[gclkn] = system_clks.freq_dpll[0] / pgclk->GENCTRL[gclkn].bit.DIV;
 100
 101     DBGC(DC_CLK_SET_GCLK_FREQ_COMPLETE);
 102
 103     return system_clks.freq_gclk[gclkn];
 104 }
 105
 106 void CLK_init_osc(void)
 107 {
 108     uint8_t gclkn = GEN_OSC0;
 109     Gclk *pgclk = GCLK;
 110
 111     DBGC(DC_CLK_INIT_OSC_BEGIN);
 112
 113     while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_1); }
 114     pgclk->GENCTRL[gclkn].bit.SRC = GCLK_SOURCE_XOSC0;
 115     while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_2); }
 116     pgclk->GENCTRL[gclkn].bit.DIV = 1;
 117     while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_3); }
 118     pgclk->GENCTRL[gclkn].bit.DIVSEL = 0;
 119     while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_4); }
 120     pgclk->GENCTRL[gclkn].bit.GENEN = 1;
 121     while (pgclk->SYNCBUSY.vec.GENCTRL) { DBGC(DC_CLK_INIT_OSC_SYNC_5); }
 122     system_clks.freq_gclk[gclkn] = system_clks.freq_xosc0;
 123
 124     DBGC(DC_CLK_INIT_OSC_COMPLETE);
 125 }
 126
 127 void CLK_reset_time(void)
 128 {
 129     Tc *ptc4 = TC4;
 130     Tc *ptc0 = TC0;
 131
 132     ms_clk = 0;
 133
 134     DBGC(DC_CLK_RESET_TIME_BEGIN);
 135
 136     //stop counters
 137     ptc4->COUNT16.CTRLA.bit.ENABLE = 0;
 138     while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) {}
 139     ptc0->COUNT32.CTRLA.bit.ENABLE = 0;
 140     while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) {}
 141     //zero counters
 142     ptc4->COUNT16.COUNT.reg = 0;
 143     while (ptc4->COUNT16.SYNCBUSY.bit.COUNT) {}
 144     ptc0->COUNT32.COUNT.reg = 0;
 145     while (ptc0->COUNT32.SYNCBUSY.bit.COUNT) {}
 146     //start counters
 147     ptc0->COUNT32.CTRLA.bit.ENABLE = 1;
 148     while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) {}
 149     ptc4->COUNT16.CTRLA.bit.ENABLE = 1;
 150     while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) {}
 151
 152     DBGC(DC_CLK_RESET_TIME_COMPLETE);
 153 }
 154
 155 void TC4_Handler()
 156 {
 157     if (TC4->COUNT16.INTFLAG.bit.MC0)
 158     {
 159         TC4->COUNT16.INTFLAG.reg = TC_INTENCLR_MC0;
 160         ms_clk++;
 161     }
 162 }
 163
 164 uint32_t CLK_enable_timebase(void)
 165 {
 166     Gclk *pgclk = GCLK;
 167     Mclk *pmclk = MCLK;
 168     Tc *ptc4 = TC4;
 169     Tc *ptc0 = TC0;
 170     Evsys *pevsys = EVSYS;
 171
 172     DBGC(DC_CLK_ENABLE_TIMEBASE_BEGIN);
 173
 174     //gclk2  highspeed time base
 175     CLK_set_gclk_freq(GEN_TC45, FREQ_TC45_DEFAULT);
 176     CLK_init_osc();
 177
 178     //unmask TC4, sourcegclk2 to TC4
 179     pmclk->APBCMASK.bit.TC4_ = 1;
 180     pgclk->PCHCTRL[TC4_GCLK_ID].bit.GEN = GEN_TC45;
 181     pgclk->PCHCTRL[TC4_GCLK_ID].bit.CHEN = 1;
 182
 183     //configure TC4
 184     DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN);
 185     ptc4->COUNT16.CTRLA.bit.ENABLE = 0;
 186     while (ptc4->COUNT16.SYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE); }
 187     ptc4->COUNT16.CTRLA.bit.SWRST = 1;
 188     while (ptc4->COUNT16.SYNCBUSY.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1); }
 189     while (ptc4->COUNT16.CTRLA.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2); }
 190
 191     //CTRLA defaults
 192     //CTRLB as default, counting up
 193     ptc4->COUNT16.CTRLBCLR.reg = 5;
 194     while (ptc4->COUNT16.SYNCBUSY.bit.CTRLB) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB); }
 195     ptc4->COUNT16.CC[0].reg = 999;
 196     while (ptc4->COUNT16.SYNCBUSY.bit.CC0) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0); }
 197     //ptc4->COUNT16.DBGCTRL.bit.DBGRUN = 1;
 198
 199     //wave mode
 200     ptc4->COUNT16.WAVE.bit.WAVEGEN = 1; //MFRQ match frequency mode, toggle each CC match
 201     //generate event for next stage
 202     ptc4->COUNT16.EVCTRL.bit.MCEO0 = 1;
 203
 204     NVIC_EnableIRQ(TC4_IRQn);
 205     ptc4->COUNT16.INTENSET.bit.MC0 = 1;
 206
 207     DBGC(DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE);
 208
 209     //unmask TC0,1, sourcegclk2 to TC0,1
 210     pmclk->APBAMASK.bit.TC0_ = 1;
 211     pgclk->PCHCTRL[TC0_GCLK_ID].bit.GEN = GEN_TC45;
 212     pgclk->PCHCTRL[TC0_GCLK_ID].bit.CHEN = 1;
 213
 214     pmclk->APBAMASK.bit.TC1_ = 1;
 215     pgclk->PCHCTRL[TC1_GCLK_ID].bit.GEN = GEN_TC45;
 216     pgclk->PCHCTRL[TC1_GCLK_ID].bit.CHEN = 1;
 217
 218     //configure TC0
 219     DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN);
 220     ptc0->COUNT32.CTRLA.bit.ENABLE = 0;
 221     while (ptc0->COUNT32.SYNCBUSY.bit.ENABLE) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE); }
 222     ptc0->COUNT32.CTRLA.bit.SWRST = 1;
 223     while (ptc0->COUNT32.SYNCBUSY.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1); }
 224     while (ptc0->COUNT32.CTRLA.bit.SWRST) { DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2); }
 225     //CTRLA as default
 226     ptc0->COUNT32.CTRLA.bit.MODE = 2; //32 bit mode
 227     ptc0->COUNT32.EVCTRL.bit.TCEI = 1; //enable incoming events
 228     ptc0->COUNT32.EVCTRL.bit.EVACT = 2 ; //count events
 229
 230     DBGC(DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE);
 231
 232     DBGC(DC_CLK_ENABLE_TIMEBASE_EVSYS_BEGIN);
 233
 234     //configure event system
 235     pmclk->APBBMASK.bit.EVSYS_ = 1;
 236     pgclk->PCHCTRL[EVSYS_GCLK_ID_0].bit.GEN = GEN_TC45;
 237     pgclk->PCHCTRL[EVSYS_GCLK_ID_0].bit.CHEN = 1;
 238     pevsys->USER[44].reg = EVSYS_ID_USER_PORT_EV_0;                               //TC0 will get event channel 0
 239     pevsys->Channel[0].CHANNEL.bit.EDGSEL = EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val; //Rising edge
 240     pevsys->Channel[0].CHANNEL.bit.PATH = EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val;     //Synchronous
 241     pevsys->Channel[0].CHANNEL.bit.EVGEN = EVSYS_ID_GEN_TC4_MCX_0;                //TC4 MC0
 242
 243     DBGC(DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE);
 244
 245     CLK_reset_time();
 246
 247     ADC0_clock_init();
 248
 249     DBGC(DC_CLK_ENABLE_TIMEBASE_COMPLETE);
 250
 251     return 0;
 252 }
 253
 254 void CLK_delay_us(uint32_t usec)
 255 {
 256     asm (
 257         "CBZ R0, return\n\t"        //If usec == 0, branch to return label
 258     );
 259     asm (
 260         "MULS R0, %0\n\t"           //Multiply R0(usec) by usec_delay_mult and store in R0
 261         ".balign 16\n\t"            //Ensure loop is aligned for fastest performance
 262         "loop: SUBS R0, #1\n\t"     //Subtract 1 from R0 and update flags (1 cycle)
 263         "BNE loop\n\t"              //Branch if non-zero to loop label (2 cycles)  NOTE: USEC_DELAY_LOOP_CYCLES is the sum of loop cycles
 264         "return:\n\t"               //Return label
 265         : //No output registers
 266         : "r" (usec_delay_mult)     //For %0
 267     );
 268     //Note: BX LR generated
 269 }
 270
 271 void CLK_delay_ms(uint64_t msec)
 272 {
 273     msec += timer_read64();
 274     while (msec > timer_read64()) {}
 275 }
 276
 277 void clk_enable_sercom_apbmask(int sercomn)
 278 {
 279     Mclk *pmclk = MCLK;
 280     switch (sercomn)
 281     {
 282         case 0:
 283             pmclk->APBAMASK.bit.SERCOM0_ = 1;
 284             break;
 285         case 1:
 286             pmclk->APBAMASK.bit.SERCOM1_ = 1;
 287             break;
 288         case 2:
 289             pmclk->APBBMASK.bit.SERCOM2_ = 1;
 290             break;
 291         case 3:
 292             pmclk->APBBMASK.bit.SERCOM3_ = 1;
 293             break;
 294         default:
 295             break;
 296     }
 297 }
 298
 299 //call CLK_oscctrl_init first
 300 //call CLK_set_spi_freq(CHAN_SERCOM_SPI, FREQ_SPI_DEFAULT);
 301 uint32_t CLK_set_spi_freq(uint8_t sercomn, uint32_t freq)
 302 {
 303     DBGC(DC_CLK_SET_SPI_FREQ_BEGIN);
 304
 305     Gclk *pgclk = GCLK;
 306     Sercom *psercom = (Sercom *)sercom_apbbase[sercomn];
 307     clk_enable_sercom_apbmask(sercomn);
 308
 309     //all gclk0 for now
 310     pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN = 0;
 311     pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.CHEN = 1;
 312
 313     psercom->I2CM.CTRLA.bit.SWRST = 1;
 314     while (psercom->I2CM.SYNCBUSY.bit.SWRST) {}
 315     while (psercom->I2CM.CTRLA.bit.SWRST) {}
 316
 317     psercom->SPI.BAUD.reg = (uint8_t) (system_clks.freq_gclk[0]/2/freq-1);
 318     system_clks.freq_spi = system_clks.freq_gclk[0]/2/(psercom->SPI.BAUD.reg+1);
 319     system_clks.freq_sercom[sercomn] = system_clks.freq_spi;
 320
 321     DBGC(DC_CLK_SET_SPI_FREQ_COMPLETE);
 322
 323     return system_clks.freq_spi;
 324 }
 325
 326 //call CLK_oscctrl_init first
 327 //call CLK_set_i2c0_freq(CHAN_SERCOM_I2C0, FREQ_I2C0_DEFAULT);
 328 uint32_t CLK_set_i2c0_freq(uint8_t sercomn, uint32_t freq)
 329 {
 330     DBGC(DC_CLK_SET_I2C0_FREQ_BEGIN);
 331
 332     Gclk *pgclk = GCLK;
 333     Sercom *psercom = (Sercom *)sercom_apbbase[sercomn];
 334     clk_enable_sercom_apbmask(sercomn);
 335
 336     //all gclk0 for now
 337     pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN = 0;
 338     pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.CHEN = 1;
 339
 340     psercom->I2CM.CTRLA.bit.SWRST = 1;
 341     while (psercom->I2CM.SYNCBUSY.bit.SWRST) {}
 342     while (psercom->I2CM.CTRLA.bit.SWRST) {}
 343
 344     psercom->I2CM.BAUD.bit.BAUD = (uint8_t) (system_clks.freq_gclk[0]/2/freq-1);
 345     system_clks.freq_i2c0 = system_clks.freq_gclk[0]/2/(psercom->I2CM.BAUD.bit.BAUD+1);
 346     system_clks.freq_sercom[sercomn] = system_clks.freq_i2c0;
 347
 348     DBGC(DC_CLK_SET_I2C0_FREQ_COMPLETE);
 349
 350     return system_clks.freq_i2c0;
 351 }
 352
 353 //call CLK_oscctrl_init first
 354 //call CLK_set_i2c1_freq(CHAN_SERCOM_I2C1, FREQ_I2C1_DEFAULT);
 355 uint32_t CLK_set_i2c1_freq(uint8_t sercomn, uint32_t freq)
 356 {
 357     DBGC(DC_CLK_SET_I2C1_FREQ_BEGIN);
 358
 359     Gclk *pgclk = GCLK;
 360     Sercom *psercom = (Sercom *)sercom_apbbase[sercomn];
 361     clk_enable_sercom_apbmask(sercomn);
 362
 363     //all gclk0 for now
 364     pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.GEN = 0;
 365     pgclk->PCHCTRL[sercom_pchan[sercomn]].bit.CHEN = 1;
 366
 367     psercom->I2CM.CTRLA.bit.SWRST = 1;
 368     while (psercom->I2CM.SYNCBUSY.bit.SWRST) {}
 369     while (psercom->I2CM.CTRLA.bit.SWRST) {}
 370
 371     psercom->I2CM.BAUD.bit.BAUD = (uint8_t) (system_clks.freq_gclk[0]/2/freq-10);
 372     system_clks.freq_i2c1 = system_clks.freq_gclk[0]/2/(psercom->I2CM.BAUD.bit.BAUD+10);
 373     system_clks.freq_sercom[sercomn] = system_clks.freq_i2c1;
 374
 375     DBGC(DC_CLK_SET_I2C1_FREQ_COMPLETE);
 376
 377     return system_clks.freq_i2c1;
 378 }
 379
 380 void CLK_init(void)
 381 {
 382     DBGC(DC_CLK_INIT_BEGIN);
 383
 384     memset((void *)&system_clks,0,sizeof(system_clks));
 385
 386     CLK_oscctrl_init();
 387     CLK_enable_timebase();
 388
 389     DBGC(DC_CLK_INIT_COMPLETE);
 390 }
 391