2 Copyright 2018 Massdrop Inc.
4 This program is free software: you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation, either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include "arm_atsam_protocol.h"
24 uint16_t v_con_1_boot;
25 uint16_t v_con_2_boot;
27 void ADC0_clock_init(void)
29 DBGC(DC_ADC0_CLOCK_INIT_BEGIN);
31 MCLK->APBDMASK.bit.ADC0_ = 1; //ADC0 Clock Enable
33 GCLK->PCHCTRL[ADC0_GCLK_ID].bit.GEN = GEN_OSC0; //Select generator clock
34 GCLK->PCHCTRL[ADC0_GCLK_ID].bit.CHEN = 1; //Enable peripheral clock
36 DBGC(DC_ADC0_CLOCK_INIT_COMPLETE);
41 DBGC(DC_ADC0_INIT_BEGIN);
44 PORT->Group[1].DIRCLR.reg = 1 << 0; //PB00 as input 5V
45 PORT->Group[1].DIRCLR.reg = 1 << 1; //PB01 as input CON2
46 PORT->Group[1].DIRCLR.reg = 1 << 2; //PB02 as input CON1
47 PORT->Group[1].PMUX[0].bit.PMUXE = 1; //PB00 mux select B ADC 5V
48 PORT->Group[1].PMUX[0].bit.PMUXO = 1; //PB01 mux select B ADC CON2
49 PORT->Group[1].PMUX[1].bit.PMUXE = 1; //PB02 mux select B ADC CON1
50 PORT->Group[1].PINCFG[0].bit.PMUXEN = 1; //PB01 mux ADC Enable 5V
51 PORT->Group[1].PINCFG[1].bit.PMUXEN = 1; //PB01 mux ADC Enable CON2
52 PORT->Group[1].PINCFG[2].bit.PMUXEN = 1; //PB02 mux ADC Enable CON1
55 ADC0->CTRLA.bit.SWRST = 1;
56 while (ADC0->SYNCBUSY.bit.SWRST) { DBGC(DC_ADC0_SWRST_SYNCING_1); }
57 while (ADC0->CTRLA.bit.SWRST) { DBGC(DC_ADC0_SWRST_SYNCING_2); }
60 ADC0->CTRLA.bit.PRESCALER = ADC_CTRLA_PRESCALER_DIV2_Val;
63 ADC0->AVGCTRL.bit.SAMPLENUM = ADC_AVGCTRL_SAMPLENUM_4_Val;
64 while (ADC0->SYNCBUSY.bit.AVGCTRL) { DBGC(DC_ADC0_AVGCTRL_SYNCING_1); }
65 if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_1_Val) ADC0->AVGCTRL.bit.ADJRES = 0;
66 else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_2_Val) ADC0->AVGCTRL.bit.ADJRES = 1;
67 else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_4_Val) ADC0->AVGCTRL.bit.ADJRES = 2;
68 else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_8_Val) ADC0->AVGCTRL.bit.ADJRES = 3;
69 else ADC0->AVGCTRL.bit.ADJRES = 4;
70 while (ADC0->SYNCBUSY.bit.AVGCTRL) { DBGC(DC_ADC0_AVGCTRL_SYNCING_2); }
73 ADC0->SAMPCTRL.bit.SAMPLEN = 45; //Sampling Time Length: 1-63, 1 ADC CLK per
74 while (ADC0->SYNCBUSY.bit.SAMPCTRL) { DBGC(DC_ADC0_SAMPCTRL_SYNCING_1); }
76 //Load factory calibration data
77 ADC0->CALIB.bit.BIASCOMP = (ADC0_FUSES_BIASCOMP_ADDR >> ADC0_FUSES_BIASCOMP_Pos) & ADC0_FUSES_BIASCOMP_Msk;
78 ADC0->CALIB.bit.BIASR2R = (ADC0_FUSES_BIASR2R_ADDR >> ADC0_FUSES_BIASR2R_Pos) & ADC0_FUSES_BIASR2R_Msk;
79 ADC0->CALIB.bit.BIASREFBUF = (ADC0_FUSES_BIASREFBUF_ADDR >> ADC0_FUSES_BIASREFBUF_Pos) & ADC0_FUSES_BIASREFBUF_Msk;
82 ADC0->CTRLA.bit.ENABLE = 1;
83 while (ADC0->SYNCBUSY.bit.ENABLE) { DBGC(DC_ADC0_ENABLE_SYNCING_1); }
85 DBGC(DC_ADC0_INIT_COMPLETE);
88 uint16_t adc_get(uint8_t muxpos)
90 ADC0->INPUTCTRL.bit.MUXPOS = muxpos;
91 while (ADC0->SYNCBUSY.bit.INPUTCTRL) {}
93 ADC0->SWTRIG.bit.START = 1;
94 while (ADC0->SYNCBUSY.bit.SWTRIG) {}
95 while (!ADC0->INTFLAG.bit.RESRDY) {}
97 return ADC0->RESULT.reg;