4 * \brief Instance description for ICM
6 * Copyright (c) 2017 Microchip Technology Inc.
12 * SPDX-License-Identifier: Apache-2.0
14 * Licensed under the Apache License, Version 2.0 (the "License"); you may
15 * not use this file except in compliance with the License.
16 * You may obtain a copy of the Licence at
18 * http://www.apache.org/licenses/LICENSE-2.0
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
30 #ifndef _SAMD51_ICM_INSTANCE_
31 #define _SAMD51_ICM_INSTANCE_
33 /* ========== Register definition for ICM peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_ICM_CFG (0x42002C00) /**< \brief (ICM) Configuration */
36 #define REG_ICM_CTRL (0x42002C04) /**< \brief (ICM) Control */
37 #define REG_ICM_SR (0x42002C08) /**< \brief (ICM) Status */
38 #define REG_ICM_IER (0x42002C10) /**< \brief (ICM) Interrupt Enable */
39 #define REG_ICM_IDR (0x42002C14) /**< \brief (ICM) Interrupt Disable */
40 #define REG_ICM_IMR (0x42002C18) /**< \brief (ICM) Interrupt Mask */
41 #define REG_ICM_ISR (0x42002C1C) /**< \brief (ICM) Interrupt Status */
42 #define REG_ICM_UASR (0x42002C20) /**< \brief (ICM) Undefined Access Status */
43 #define REG_ICM_DSCR (0x42002C30) /**< \brief (ICM) Region Descriptor Area Start Address */
44 #define REG_ICM_HASH (0x42002C34) /**< \brief (ICM) Region Hash Area Start Address */
45 #define REG_ICM_UIHVAL0 (0x42002C38) /**< \brief (ICM) User Initial Hash Value 0 */
46 #define REG_ICM_UIHVAL1 (0x42002C3C) /**< \brief (ICM) User Initial Hash Value 1 */
47 #define REG_ICM_UIHVAL2 (0x42002C40) /**< \brief (ICM) User Initial Hash Value 2 */
48 #define REG_ICM_UIHVAL3 (0x42002C44) /**< \brief (ICM) User Initial Hash Value 3 */
49 #define REG_ICM_UIHVAL4 (0x42002C48) /**< \brief (ICM) User Initial Hash Value 4 */
50 #define REG_ICM_UIHVAL5 (0x42002C4C) /**< \brief (ICM) User Initial Hash Value 5 */
51 #define REG_ICM_UIHVAL6 (0x42002C50) /**< \brief (ICM) User Initial Hash Value 6 */
52 #define REG_ICM_UIHVAL7 (0x42002C54) /**< \brief (ICM) User Initial Hash Value 7 */
54 #define REG_ICM_CFG (*(RwReg *)0x42002C00UL) /**< \brief (ICM) Configuration */
55 #define REG_ICM_CTRL (*(WoReg *)0x42002C04UL) /**< \brief (ICM) Control */
56 #define REG_ICM_SR (*(RoReg *)0x42002C08UL) /**< \brief (ICM) Status */
57 #define REG_ICM_IER (*(WoReg *)0x42002C10UL) /**< \brief (ICM) Interrupt Enable */
58 #define REG_ICM_IDR (*(WoReg *)0x42002C14UL) /**< \brief (ICM) Interrupt Disable */
59 #define REG_ICM_IMR (*(RoReg *)0x42002C18UL) /**< \brief (ICM) Interrupt Mask */
60 #define REG_ICM_ISR (*(RoReg *)0x42002C1CUL) /**< \brief (ICM) Interrupt Status */
61 #define REG_ICM_UASR (*(RoReg *)0x42002C20UL) /**< \brief (ICM) Undefined Access Status */
62 #define REG_ICM_DSCR (*(RwReg *)0x42002C30UL) /**< \brief (ICM) Region Descriptor Area Start Address */
63 #define REG_ICM_HASH (*(RwReg *)0x42002C34UL) /**< \brief (ICM) Region Hash Area Start Address */
64 #define REG_ICM_UIHVAL0 (*(WoReg *)0x42002C38UL) /**< \brief (ICM) User Initial Hash Value 0 */
65 #define REG_ICM_UIHVAL1 (*(WoReg *)0x42002C3CUL) /**< \brief (ICM) User Initial Hash Value 1 */
66 #define REG_ICM_UIHVAL2 (*(WoReg *)0x42002C40UL) /**< \brief (ICM) User Initial Hash Value 2 */
67 #define REG_ICM_UIHVAL3 (*(WoReg *)0x42002C44UL) /**< \brief (ICM) User Initial Hash Value 3 */
68 #define REG_ICM_UIHVAL4 (*(WoReg *)0x42002C48UL) /**< \brief (ICM) User Initial Hash Value 4 */
69 #define REG_ICM_UIHVAL5 (*(WoReg *)0x42002C4CUL) /**< \brief (ICM) User Initial Hash Value 5 */
70 #define REG_ICM_UIHVAL6 (*(WoReg *)0x42002C50UL) /**< \brief (ICM) User Initial Hash Value 6 */
71 #define REG_ICM_UIHVAL7 (*(WoReg *)0x42002C54UL) /**< \brief (ICM) User Initial Hash Value 7 */
72 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
74 /* ========== Instance parameters for ICM peripheral ========== */
75 #define ICM_CLK_AHB_ID 19
77 #endif /* _SAMD51_ICM_INSTANCE_ */