4 * \brief Instance description for I2S
6 * Copyright (c) 2017 Microchip Technology Inc.
12 * SPDX-License-Identifier: Apache-2.0
14 * Licensed under the Apache License, Version 2.0 (the "License"); you may
15 * not use this file except in compliance with the License.
16 * You may obtain a copy of the Licence at
18 * http://www.apache.org/licenses/LICENSE-2.0
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
30 #ifndef _SAMD51_I2S_INSTANCE_
31 #define _SAMD51_I2S_INSTANCE_
33 /* ========== Register definition for I2S peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_I2S_CTRLA (0x43002800) /**< \brief (I2S) Control A */
36 #define REG_I2S_CLKCTRL0 (0x43002804) /**< \brief (I2S) Clock Unit 0 Control */
37 #define REG_I2S_CLKCTRL1 (0x43002808) /**< \brief (I2S) Clock Unit 1 Control */
38 #define REG_I2S_INTENCLR (0x4300280C) /**< \brief (I2S) Interrupt Enable Clear */
39 #define REG_I2S_INTENSET (0x43002810) /**< \brief (I2S) Interrupt Enable Set */
40 #define REG_I2S_INTFLAG (0x43002814) /**< \brief (I2S) Interrupt Flag Status and Clear */
41 #define REG_I2S_SYNCBUSY (0x43002818) /**< \brief (I2S) Synchronization Status */
42 #define REG_I2S_TXCTRL (0x43002820) /**< \brief (I2S) Tx Serializer Control */
43 #define REG_I2S_RXCTRL (0x43002824) /**< \brief (I2S) Rx Serializer Control */
44 #define REG_I2S_TXDATA (0x43002830) /**< \brief (I2S) Tx Data */
45 #define REG_I2S_RXDATA (0x43002834) /**< \brief (I2S) Rx Data */
47 #define REG_I2S_CTRLA (*(RwReg8 *)0x43002800UL) /**< \brief (I2S) Control A */
48 #define REG_I2S_CLKCTRL0 (*(RwReg *)0x43002804UL) /**< \brief (I2S) Clock Unit 0 Control */
49 #define REG_I2S_CLKCTRL1 (*(RwReg *)0x43002808UL) /**< \brief (I2S) Clock Unit 1 Control */
50 #define REG_I2S_INTENCLR (*(RwReg16*)0x4300280CUL) /**< \brief (I2S) Interrupt Enable Clear */
51 #define REG_I2S_INTENSET (*(RwReg16*)0x43002810UL) /**< \brief (I2S) Interrupt Enable Set */
52 #define REG_I2S_INTFLAG (*(RwReg16*)0x43002814UL) /**< \brief (I2S) Interrupt Flag Status and Clear */
53 #define REG_I2S_SYNCBUSY (*(RoReg16*)0x43002818UL) /**< \brief (I2S) Synchronization Status */
54 #define REG_I2S_TXCTRL (*(RwReg *)0x43002820UL) /**< \brief (I2S) Tx Serializer Control */
55 #define REG_I2S_RXCTRL (*(RwReg *)0x43002824UL) /**< \brief (I2S) Rx Serializer Control */
56 #define REG_I2S_TXDATA (*(WoReg *)0x43002830UL) /**< \brief (I2S) Tx Data */
57 #define REG_I2S_RXDATA (*(RoReg *)0x43002834UL) /**< \brief (I2S) Rx Data */
58 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
60 /* ========== Instance parameters for I2S peripheral ========== */
61 #define I2S_CLK_NUM 2 // Number of clock units
62 #define I2S_DMAC_ID_RX_0 76
63 #define I2S_DMAC_ID_RX_1 77
64 #define I2S_DMAC_ID_RX_LSB 76
65 #define I2S_DMAC_ID_RX_MSB 77
66 #define I2S_DMAC_ID_RX_SIZE 2
67 #define I2S_DMAC_ID_TX_0 78
68 #define I2S_DMAC_ID_TX_1 79
69 #define I2S_DMAC_ID_TX_LSB 78
70 #define I2S_DMAC_ID_TX_MSB 79
71 #define I2S_DMAC_ID_TX_SIZE 2
72 #define I2S_GCLK_ID_0 43
73 #define I2S_GCLK_ID_1 44
74 #define I2S_GCLK_ID_LSB 43
75 #define I2S_GCLK_ID_MSB 44
76 #define I2S_GCLK_ID_SIZE 2
77 #define I2S_MAX_SLOTS 8 // Max number of data slots in frame
78 #define I2S_MAX_WL_BITS 32 // Max number of bits in data samples
79 #define I2S_SER_NUM 2 // Number of serializers
81 #endif /* _SAMD51_I2S_INSTANCE_ */