4 * \brief Instance description for DAC
6 * Copyright (c) 2017 Microchip Technology Inc.
12 * SPDX-License-Identifier: Apache-2.0
14 * Licensed under the Apache License, Version 2.0 (the "License"); you may
15 * not use this file except in compliance with the License.
16 * You may obtain a copy of the Licence at
18 * http://www.apache.org/licenses/LICENSE-2.0
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
30 #ifndef _SAMD51_DAC_INSTANCE_
31 #define _SAMD51_DAC_INSTANCE_
33 /* ========== Register definition for DAC peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_DAC_CTRLA (0x43002400) /**< \brief (DAC) Control A */
36 #define REG_DAC_CTRLB (0x43002401) /**< \brief (DAC) Control B */
37 #define REG_DAC_EVCTRL (0x43002402) /**< \brief (DAC) Event Control */
38 #define REG_DAC_INTENCLR (0x43002404) /**< \brief (DAC) Interrupt Enable Clear */
39 #define REG_DAC_INTENSET (0x43002405) /**< \brief (DAC) Interrupt Enable Set */
40 #define REG_DAC_INTFLAG (0x43002406) /**< \brief (DAC) Interrupt Flag Status and Clear */
41 #define REG_DAC_STATUS (0x43002407) /**< \brief (DAC) Status */
42 #define REG_DAC_SYNCBUSY (0x43002408) /**< \brief (DAC) Synchronization Busy */
43 #define REG_DAC_DACCTRL0 (0x4300240C) /**< \brief (DAC) DAC 0 Control */
44 #define REG_DAC_DACCTRL1 (0x4300240E) /**< \brief (DAC) DAC 1 Control */
45 #define REG_DAC_DATA0 (0x43002410) /**< \brief (DAC) DAC 0 Data */
46 #define REG_DAC_DATA1 (0x43002412) /**< \brief (DAC) DAC 1 Data */
47 #define REG_DAC_DATABUF0 (0x43002414) /**< \brief (DAC) DAC 0 Data Buffer */
48 #define REG_DAC_DATABUF1 (0x43002416) /**< \brief (DAC) DAC 1 Data Buffer */
49 #define REG_DAC_DBGCTRL (0x43002418) /**< \brief (DAC) Debug Control */
50 #define REG_DAC_RESULT0 (0x4300241C) /**< \brief (DAC) Filter Result 0 */
51 #define REG_DAC_RESULT1 (0x4300241E) /**< \brief (DAC) Filter Result 1 */
53 #define REG_DAC_CTRLA (*(RwReg8 *)0x43002400UL) /**< \brief (DAC) Control A */
54 #define REG_DAC_CTRLB (*(RwReg8 *)0x43002401UL) /**< \brief (DAC) Control B */
55 #define REG_DAC_EVCTRL (*(RwReg8 *)0x43002402UL) /**< \brief (DAC) Event Control */
56 #define REG_DAC_INTENCLR (*(RwReg8 *)0x43002404UL) /**< \brief (DAC) Interrupt Enable Clear */
57 #define REG_DAC_INTENSET (*(RwReg8 *)0x43002405UL) /**< \brief (DAC) Interrupt Enable Set */
58 #define REG_DAC_INTFLAG (*(RwReg8 *)0x43002406UL) /**< \brief (DAC) Interrupt Flag Status and Clear */
59 #define REG_DAC_STATUS (*(RoReg8 *)0x43002407UL) /**< \brief (DAC) Status */
60 #define REG_DAC_SYNCBUSY (*(RoReg *)0x43002408UL) /**< \brief (DAC) Synchronization Busy */
61 #define REG_DAC_DACCTRL0 (*(RwReg16*)0x4300240CUL) /**< \brief (DAC) DAC 0 Control */
62 #define REG_DAC_DACCTRL1 (*(RwReg16*)0x4300240EUL) /**< \brief (DAC) DAC 1 Control */
63 #define REG_DAC_DATA0 (*(WoReg16*)0x43002410UL) /**< \brief (DAC) DAC 0 Data */
64 #define REG_DAC_DATA1 (*(WoReg16*)0x43002412UL) /**< \brief (DAC) DAC 1 Data */
65 #define REG_DAC_DATABUF0 (*(WoReg16*)0x43002414UL) /**< \brief (DAC) DAC 0 Data Buffer */
66 #define REG_DAC_DATABUF1 (*(WoReg16*)0x43002416UL) /**< \brief (DAC) DAC 1 Data Buffer */
67 #define REG_DAC_DBGCTRL (*(RwReg8 *)0x43002418UL) /**< \brief (DAC) Debug Control */
68 #define REG_DAC_RESULT0 (*(RoReg16*)0x4300241CUL) /**< \brief (DAC) Filter Result 0 */
69 #define REG_DAC_RESULT1 (*(RoReg16*)0x4300241EUL) /**< \brief (DAC) Filter Result 1 */
70 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
72 /* ========== Instance parameters for DAC peripheral ========== */
73 #define DAC_CHANNEL_SIZE 2 // Number of DACs
74 #define DAC_DATA_SIZE 12 // Number of bits in data
75 #define DAC_DMAC_ID_EMPTY_0 72
76 #define DAC_DMAC_ID_EMPTY_1 73
77 #define DAC_DMAC_ID_EMPTY_LSB 72
78 #define DAC_DMAC_ID_EMPTY_MSB 73
79 #define DAC_DMAC_ID_EMPTY_SIZE 2
80 #define DAC_DMAC_ID_RESRDY_0 74
81 #define DAC_DMAC_ID_RESRDY_1 75
82 #define DAC_DMAC_ID_RESRDY_LSB 74
83 #define DAC_DMAC_ID_RESRDY_MSB 75
84 #define DAC_DMAC_ID_RESRDY_SIZE 2
85 #define DAC_GCLK_ID 42 // Index of Generic Clock
86 #define DAC_STEP 7 // Number of steps to reach full scale
88 #endif /* _SAMD51_DAC_INSTANCE_ */