4 * \brief Component description for USB
6 * Copyright (c) 2017 Microchip Technology Inc.
12 * SPDX-License-Identifier: Apache-2.0
14 * Licensed under the Apache License, Version 2.0 (the "License"); you may
15 * not use this file except in compliance with the License.
16 * You may obtain a copy of the Licence at
18 * http://www.apache.org/licenses/LICENSE-2.0
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
30 #ifndef _SAMD51_USB_COMPONENT_
31 #define _SAMD51_USB_COMPONENT_
33 /* ========================================================================== */
34 /** SOFTWARE API DEFINITION FOR USB */
35 /* ========================================================================== */
36 /** \addtogroup SAMD51_USB Universal Serial Bus */
42 /* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
46 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
47 uint8_t ENABLE:1; /*!< bit: 1 Enable */
48 uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
49 uint8_t :4; /*!< bit: 3.. 6 Reserved */
50 uint8_t MODE:1; /*!< bit: 7 Operating Mode */
51 } bit; /*!< Structure used for bit access */
52 uint8_t reg; /*!< Type used for register access */
54 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
56 #define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */
57 #define USB_CTRLA_RESETVALUE _U_(0x00) /**< \brief (USB_CTRLA reset_value) Control A */
59 #define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */
60 #define USB_CTRLA_SWRST (_U_(0x1) << USB_CTRLA_SWRST_Pos)
61 #define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */
62 #define USB_CTRLA_ENABLE (_U_(0x1) << USB_CTRLA_ENABLE_Pos)
63 #define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */
64 #define USB_CTRLA_RUNSTDBY (_U_(0x1) << USB_CTRLA_RUNSTDBY_Pos)
65 #define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */
66 #define USB_CTRLA_MODE (_U_(0x1) << USB_CTRLA_MODE_Pos)
67 #define USB_CTRLA_MODE_DEVICE_Val _U_(0x0) /**< \brief (USB_CTRLA) Device Mode */
68 #define USB_CTRLA_MODE_HOST_Val _U_(0x1) /**< \brief (USB_CTRLA) Host Mode */
69 #define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos)
70 #define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos)
71 #define USB_CTRLA_MASK _U_(0x87) /**< \brief (USB_CTRLA) MASK Register */
73 /* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */
74 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
77 uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
78 uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
79 uint8_t :6; /*!< bit: 2.. 7 Reserved */
80 } bit; /*!< Structure used for bit access */
81 uint8_t reg; /*!< Type used for register access */
83 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
85 #define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */
86 #define USB_SYNCBUSY_RESETVALUE _U_(0x00) /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */
88 #define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */
89 #define USB_SYNCBUSY_SWRST (_U_(0x1) << USB_SYNCBUSY_SWRST_Pos)
90 #define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */
91 #define USB_SYNCBUSY_ENABLE (_U_(0x1) << USB_SYNCBUSY_ENABLE_Pos)
92 #define USB_SYNCBUSY_MASK _U_(0x03) /**< \brief (USB_SYNCBUSY) MASK Register */
94 /* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */
95 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
98 uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */
99 uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */
100 uint8_t :4; /*!< bit: 4.. 7 Reserved */
101 } bit; /*!< Structure used for bit access */
102 uint8_t reg; /*!< Type used for register access */
104 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
106 #define USB_QOSCTRL_OFFSET 0x003 /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */
107 #define USB_QOSCTRL_RESETVALUE _U_(0x0F) /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */
109 #define USB_QOSCTRL_CQOS_Pos 0 /**< \brief (USB_QOSCTRL) Configuration Quality of Service */
110 #define USB_QOSCTRL_CQOS_Msk (_U_(0x3) << USB_QOSCTRL_CQOS_Pos)
111 #define USB_QOSCTRL_CQOS(value) (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos))
112 #define USB_QOSCTRL_DQOS_Pos 2 /**< \brief (USB_QOSCTRL) Data Quality of Service */
113 #define USB_QOSCTRL_DQOS_Msk (_U_(0x3) << USB_QOSCTRL_DQOS_Pos)
114 #define USB_QOSCTRL_DQOS(value) (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos))
115 #define USB_QOSCTRL_MASK _U_(0x0F) /**< \brief (USB_QOSCTRL) MASK Register */
117 /* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
118 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
121 uint16_t DETACH:1; /*!< bit: 0 Detach */
122 uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
123 uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
124 uint16_t NREPLY:1; /*!< bit: 4 No Reply */
125 uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
126 uint16_t TSTK:1; /*!< bit: 6 Test mode K */
127 uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
128 uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
129 uint16_t GNAK:1; /*!< bit: 9 Global NAK */
130 uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
131 uint16_t :4; /*!< bit: 12..15 Reserved */
132 } bit; /*!< Structure used for bit access */
133 uint16_t reg; /*!< Type used for register access */
134 } USB_DEVICE_CTRLB_Type;
135 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
137 #define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */
138 #define USB_DEVICE_CTRLB_RESETVALUE _U_(0x0001) /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */
140 #define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */
141 #define USB_DEVICE_CTRLB_DETACH (_U_(0x1) << USB_DEVICE_CTRLB_DETACH_Pos)
142 #define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */
143 #define USB_DEVICE_CTRLB_UPRSM (_U_(0x1) << USB_DEVICE_CTRLB_UPRSM_Pos)
144 #define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
145 #define USB_DEVICE_CTRLB_SPDCONF_Msk (_U_(0x3) << USB_DEVICE_CTRLB_SPDCONF_Pos)
146 #define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))
147 #define USB_DEVICE_CTRLB_SPDCONF_FS_Val _U_(0x0) /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
148 #define USB_DEVICE_CTRLB_SPDCONF_LS_Val _U_(0x1) /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
149 #define USB_DEVICE_CTRLB_SPDCONF_HS_Val _U_(0x2) /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
150 #define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val _U_(0x3) /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */
151 #define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
152 #define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
153 #define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
154 #define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
155 #define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */
156 #define USB_DEVICE_CTRLB_NREPLY (_U_(0x1) << USB_DEVICE_CTRLB_NREPLY_Pos)
157 #define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */
158 #define USB_DEVICE_CTRLB_TSTJ (_U_(0x1) << USB_DEVICE_CTRLB_TSTJ_Pos)
159 #define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */
160 #define USB_DEVICE_CTRLB_TSTK (_U_(0x1) << USB_DEVICE_CTRLB_TSTK_Pos)
161 #define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */
162 #define USB_DEVICE_CTRLB_TSTPCKT (_U_(0x1) << USB_DEVICE_CTRLB_TSTPCKT_Pos)
163 #define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */
164 #define USB_DEVICE_CTRLB_OPMODE2 (_U_(0x1) << USB_DEVICE_CTRLB_OPMODE2_Pos)
165 #define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */
166 #define USB_DEVICE_CTRLB_GNAK (_U_(0x1) << USB_DEVICE_CTRLB_GNAK_Pos)
167 #define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
168 #define USB_DEVICE_CTRLB_LPMHDSK_Msk (_U_(0x3) << USB_DEVICE_CTRLB_LPMHDSK_Pos)
169 #define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))
170 #define USB_DEVICE_CTRLB_LPMHDSK_NO_Val _U_(0x0) /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
171 #define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val _U_(0x1) /**< \brief (USB_DEVICE_CTRLB) ACK */
172 #define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val _U_(0x2) /**< \brief (USB_DEVICE_CTRLB) NYET */
173 #define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val _U_(0x3) /**< \brief (USB_DEVICE_CTRLB) STALL */
174 #define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
175 #define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
176 #define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
177 #define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
178 #define USB_DEVICE_CTRLB_MASK _U_(0x0FFF) /**< \brief (USB_DEVICE_CTRLB) MASK Register */
180 /* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
181 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
184 uint16_t :1; /*!< bit: 0 Reserved */
185 uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
186 uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
187 uint16_t AUTORESUME:1; /*!< bit: 4 Auto Resume Enable */
188 uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
189 uint16_t TSTK:1; /*!< bit: 6 Test mode K */
190 uint16_t :1; /*!< bit: 7 Reserved */
191 uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
192 uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
193 uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
194 uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
195 uint16_t :4; /*!< bit: 12..15 Reserved */
196 } bit; /*!< Structure used for bit access */
197 uint16_t reg; /*!< Type used for register access */
198 } USB_HOST_CTRLB_Type;
199 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
201 #define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */
202 #define USB_HOST_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */
204 #define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */
205 #define USB_HOST_CTRLB_RESUME (_U_(0x1) << USB_HOST_CTRLB_RESUME_Pos)
206 #define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
207 #define USB_HOST_CTRLB_SPDCONF_Msk (_U_(0x3) << USB_HOST_CTRLB_SPDCONF_Pos)
208 #define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))
209 #define USB_HOST_CTRLB_SPDCONF_NORMAL_Val _U_(0x0) /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */
210 #define USB_HOST_CTRLB_SPDCONF_FS_Val _U_(0x3) /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */
211 #define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos)
212 #define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos)
213 #define USB_HOST_CTRLB_AUTORESUME_Pos 4 /**< \brief (USB_HOST_CTRLB) Auto Resume Enable */
214 #define USB_HOST_CTRLB_AUTORESUME (_U_(0x1) << USB_HOST_CTRLB_AUTORESUME_Pos)
215 #define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */
216 #define USB_HOST_CTRLB_TSTJ (_U_(0x1) << USB_HOST_CTRLB_TSTJ_Pos)
217 #define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */
218 #define USB_HOST_CTRLB_TSTK (_U_(0x1) << USB_HOST_CTRLB_TSTK_Pos)
219 #define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */
220 #define USB_HOST_CTRLB_SOFE (_U_(0x1) << USB_HOST_CTRLB_SOFE_Pos)
221 #define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */
222 #define USB_HOST_CTRLB_BUSRESET (_U_(0x1) << USB_HOST_CTRLB_BUSRESET_Pos)
223 #define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */
224 #define USB_HOST_CTRLB_VBUSOK (_U_(0x1) << USB_HOST_CTRLB_VBUSOK_Pos)
225 #define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */
226 #define USB_HOST_CTRLB_L1RESUME (_U_(0x1) << USB_HOST_CTRLB_L1RESUME_Pos)
227 #define USB_HOST_CTRLB_MASK _U_(0x0F7E) /**< \brief (USB_HOST_CTRLB) MASK Register */
229 /* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */
230 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
233 uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
234 uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
235 } bit; /*!< Structure used for bit access */
236 uint8_t reg; /*!< Type used for register access */
237 } USB_DEVICE_DADD_Type;
238 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
240 #define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */
241 #define USB_DEVICE_DADD_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */
243 #define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */
244 #define USB_DEVICE_DADD_DADD_Msk (_U_(0x7F) << USB_DEVICE_DADD_DADD_Pos)
245 #define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))
246 #define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */
247 #define USB_DEVICE_DADD_ADDEN (_U_(0x1) << USB_DEVICE_DADD_ADDEN_Pos)
248 #define USB_DEVICE_DADD_MASK _U_(0xFF) /**< \brief (USB_DEVICE_DADD) MASK Register */
250 /* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */
251 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
254 uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
255 uint8_t :3; /*!< bit: 4.. 6 Reserved */
256 uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
257 } bit; /*!< Structure used for bit access */
258 uint8_t reg; /*!< Type used for register access */
259 } USB_HOST_HSOFC_Type;
260 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
262 #define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */
263 #define USB_HOST_HSOFC_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */
265 #define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */
266 #define USB_HOST_HSOFC_FLENC_Msk (_U_(0xF) << USB_HOST_HSOFC_FLENC_Pos)
267 #define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))
268 #define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
269 #define USB_HOST_HSOFC_FLENCE (_U_(0x1) << USB_HOST_HSOFC_FLENCE_Pos)
270 #define USB_HOST_HSOFC_MASK _U_(0x8F) /**< \brief (USB_HOST_HSOFC) MASK Register */
272 /* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */
273 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
276 uint8_t :2; /*!< bit: 0.. 1 Reserved */
277 uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
278 uint8_t :2; /*!< bit: 4.. 5 Reserved */
279 uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
280 } bit; /*!< Structure used for bit access */
281 uint8_t reg; /*!< Type used for register access */
282 } USB_DEVICE_STATUS_Type;
283 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
285 #define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */
286 #define USB_DEVICE_STATUS_RESETVALUE _U_(0x40) /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */
288 #define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */
289 #define USB_DEVICE_STATUS_SPEED_Msk (_U_(0x3) << USB_DEVICE_STATUS_SPEED_Pos)
290 #define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))
291 #define USB_DEVICE_STATUS_SPEED_FS_Val _U_(0x0) /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
292 #define USB_DEVICE_STATUS_SPEED_LS_Val _U_(0x1) /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
293 #define USB_DEVICE_STATUS_SPEED_HS_Val _U_(0x2) /**< \brief (USB_DEVICE_STATUS) High-speed mode */
294 #define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos)
295 #define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos)
296 #define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos)
297 #define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
298 #define USB_DEVICE_STATUS_LINESTATE_Msk (_U_(0x3) << USB_DEVICE_STATUS_LINESTATE_Pos)
299 #define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))
300 #define USB_DEVICE_STATUS_LINESTATE_0_Val _U_(0x0) /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
301 #define USB_DEVICE_STATUS_LINESTATE_1_Val _U_(0x1) /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
302 #define USB_DEVICE_STATUS_LINESTATE_2_Val _U_(0x2) /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
303 #define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
304 #define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
305 #define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
306 #define USB_DEVICE_STATUS_MASK _U_(0xCC) /**< \brief (USB_DEVICE_STATUS) MASK Register */
308 /* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */
309 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
312 uint8_t :2; /*!< bit: 0.. 1 Reserved */
313 uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
314 uint8_t :2; /*!< bit: 4.. 5 Reserved */
315 uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
316 } bit; /*!< Structure used for bit access */
317 uint8_t reg; /*!< Type used for register access */
318 } USB_HOST_STATUS_Type;
319 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
321 #define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */
322 #define USB_HOST_STATUS_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_STATUS reset_value) HOST Status */
324 #define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */
325 #define USB_HOST_STATUS_SPEED_Msk (_U_(0x3) << USB_HOST_STATUS_SPEED_Pos)
326 #define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))
327 #define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */
328 #define USB_HOST_STATUS_LINESTATE_Msk (_U_(0x3) << USB_HOST_STATUS_LINESTATE_Pos)
329 #define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))
330 #define USB_HOST_STATUS_MASK _U_(0xCC) /**< \brief (USB_HOST_STATUS) MASK Register */
332 /* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */
333 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
336 uint8_t FSMSTATE:7; /*!< bit: 0.. 6 Fine State Machine Status */
337 uint8_t :1; /*!< bit: 7 Reserved */
338 } bit; /*!< Structure used for bit access */
339 uint8_t reg; /*!< Type used for register access */
340 } USB_FSMSTATUS_Type;
341 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
343 #define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */
344 #define USB_FSMSTATUS_RESETVALUE _U_(0x01) /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
346 #define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
347 #define USB_FSMSTATUS_FSMSTATE_Msk (_U_(0x7F) << USB_FSMSTATUS_FSMSTATE_Pos)
348 #define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))
349 #define USB_FSMSTATUS_FSMSTATE_OFF_Val _U_(0x1) /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
350 #define USB_FSMSTATUS_FSMSTATE_ON_Val _U_(0x2) /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
351 #define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val _U_(0x4) /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
352 #define USB_FSMSTATUS_FSMSTATE_SLEEP_Val _U_(0x8) /**< \brief (USB_FSMSTATUS) SLEEP (L1) */
353 #define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val _U_(0x10) /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */
354 #define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val _U_(0x20) /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */
355 #define USB_FSMSTATUS_FSMSTATE_RESET_Val _U_(0x40) /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */
356 #define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos)
357 #define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos)
358 #define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos)
359 #define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos)
360 #define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
361 #define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
362 #define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos)
363 #define USB_FSMSTATUS_MASK _U_(0x7F) /**< \brief (USB_FSMSTATUS) MASK Register */
365 /* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */
366 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
369 uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
370 uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
371 uint16_t :1; /*!< bit: 14 Reserved */
372 uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
373 } bit; /*!< Structure used for bit access */
374 uint16_t reg; /*!< Type used for register access */
375 } USB_DEVICE_FNUM_Type;
376 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
378 #define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */
379 #define USB_DEVICE_FNUM_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */
381 #define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
382 #define USB_DEVICE_FNUM_MFNUM_Msk (_U_(0x7) << USB_DEVICE_FNUM_MFNUM_Pos)
383 #define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))
384 #define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */
385 #define USB_DEVICE_FNUM_FNUM_Msk (_U_(0x7FF) << USB_DEVICE_FNUM_FNUM_Pos)
386 #define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))
387 #define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
388 #define USB_DEVICE_FNUM_FNCERR (_U_(0x1) << USB_DEVICE_FNUM_FNCERR_Pos)
389 #define USB_DEVICE_FNUM_MASK _U_(0xBFFF) /**< \brief (USB_DEVICE_FNUM) MASK Register */
391 /* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
392 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
395 uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
396 uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
397 uint16_t :2; /*!< bit: 14..15 Reserved */
398 } bit; /*!< Structure used for bit access */
399 uint16_t reg; /*!< Type used for register access */
400 } USB_HOST_FNUM_Type;
401 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
403 #define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */
404 #define USB_HOST_FNUM_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */
406 #define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */
407 #define USB_HOST_FNUM_MFNUM_Msk (_U_(0x7) << USB_HOST_FNUM_MFNUM_Pos)
408 #define USB_HOST_FNUM_MFNUM(value) (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))
409 #define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */
410 #define USB_HOST_FNUM_FNUM_Msk (_U_(0x7FF) << USB_HOST_FNUM_FNUM_Pos)
411 #define USB_HOST_FNUM_FNUM(value) (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))
412 #define USB_HOST_FNUM_MASK _U_(0x3FFF) /**< \brief (USB_HOST_FNUM) MASK Register */
414 /* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */
415 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
418 uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
419 } bit; /*!< Structure used for bit access */
420 uint8_t reg; /*!< Type used for register access */
421 } USB_HOST_FLENHIGH_Type;
422 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
424 #define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */
425 #define USB_HOST_FLENHIGH_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */
427 #define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */
428 #define USB_HOST_FLENHIGH_FLENHIGH_Msk (_U_(0xFF) << USB_HOST_FLENHIGH_FLENHIGH_Pos)
429 #define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))
430 #define USB_HOST_FLENHIGH_MASK _U_(0xFF) /**< \brief (USB_HOST_FLENHIGH) MASK Register */
432 /* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
433 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
436 uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
437 uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
438 uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
439 uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
440 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
441 uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
442 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
443 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
444 uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
445 uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
446 uint16_t :6; /*!< bit: 10..15 Reserved */
447 } bit; /*!< Structure used for bit access */
448 uint16_t reg; /*!< Type used for register access */
449 } USB_DEVICE_INTENCLR_Type;
450 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
452 #define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */
453 #define USB_DEVICE_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */
455 #define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */
456 #define USB_DEVICE_INTENCLR_SUSPEND (_U_(0x1) << USB_DEVICE_INTENCLR_SUSPEND_Pos)
457 #define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */
458 #define USB_DEVICE_INTENCLR_MSOF (_U_(0x1) << USB_DEVICE_INTENCLR_MSOF_Pos)
459 #define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */
460 #define USB_DEVICE_INTENCLR_SOF (_U_(0x1) << USB_DEVICE_INTENCLR_SOF_Pos)
461 #define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */
462 #define USB_DEVICE_INTENCLR_EORST (_U_(0x1) << USB_DEVICE_INTENCLR_EORST_Pos)
463 #define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */
464 #define USB_DEVICE_INTENCLR_WAKEUP (_U_(0x1) << USB_DEVICE_INTENCLR_WAKEUP_Pos)
465 #define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */
466 #define USB_DEVICE_INTENCLR_EORSM (_U_(0x1) << USB_DEVICE_INTENCLR_EORSM_Pos)
467 #define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */
468 #define USB_DEVICE_INTENCLR_UPRSM (_U_(0x1) << USB_DEVICE_INTENCLR_UPRSM_Pos)
469 #define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */
470 #define USB_DEVICE_INTENCLR_RAMACER (_U_(0x1) << USB_DEVICE_INTENCLR_RAMACER_Pos)
471 #define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */
472 #define USB_DEVICE_INTENCLR_LPMNYET (_U_(0x1) << USB_DEVICE_INTENCLR_LPMNYET_Pos)
473 #define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */
474 #define USB_DEVICE_INTENCLR_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
475 #define USB_DEVICE_INTENCLR_MASK _U_(0x03FF) /**< \brief (USB_DEVICE_INTENCLR) MASK Register */
477 /* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
478 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
481 uint16_t :2; /*!< bit: 0.. 1 Reserved */
482 uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
483 uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
484 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
485 uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
486 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
487 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
488 uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
489 uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
490 uint16_t :6; /*!< bit: 10..15 Reserved */
491 } bit; /*!< Structure used for bit access */
492 uint16_t reg; /*!< Type used for register access */
493 } USB_HOST_INTENCLR_Type;
494 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
496 #define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */
497 #define USB_HOST_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */
499 #define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */
500 #define USB_HOST_INTENCLR_HSOF (_U_(0x1) << USB_HOST_INTENCLR_HSOF_Pos)
501 #define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */
502 #define USB_HOST_INTENCLR_RST (_U_(0x1) << USB_HOST_INTENCLR_RST_Pos)
503 #define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */
504 #define USB_HOST_INTENCLR_WAKEUP (_U_(0x1) << USB_HOST_INTENCLR_WAKEUP_Pos)
505 #define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */
506 #define USB_HOST_INTENCLR_DNRSM (_U_(0x1) << USB_HOST_INTENCLR_DNRSM_Pos)
507 #define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */
508 #define USB_HOST_INTENCLR_UPRSM (_U_(0x1) << USB_HOST_INTENCLR_UPRSM_Pos)
509 #define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */
510 #define USB_HOST_INTENCLR_RAMACER (_U_(0x1) << USB_HOST_INTENCLR_RAMACER_Pos)
511 #define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */
512 #define USB_HOST_INTENCLR_DCONN (_U_(0x1) << USB_HOST_INTENCLR_DCONN_Pos)
513 #define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */
514 #define USB_HOST_INTENCLR_DDISC (_U_(0x1) << USB_HOST_INTENCLR_DDISC_Pos)
515 #define USB_HOST_INTENCLR_MASK _U_(0x03FC) /**< \brief (USB_HOST_INTENCLR) MASK Register */
517 /* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
518 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
521 uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
522 uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
523 uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
524 uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
525 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
526 uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
527 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
528 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
529 uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
530 uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
531 uint16_t :6; /*!< bit: 10..15 Reserved */
532 } bit; /*!< Structure used for bit access */
533 uint16_t reg; /*!< Type used for register access */
534 } USB_DEVICE_INTENSET_Type;
535 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
537 #define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */
538 #define USB_DEVICE_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */
540 #define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */
541 #define USB_DEVICE_INTENSET_SUSPEND (_U_(0x1) << USB_DEVICE_INTENSET_SUSPEND_Pos)
542 #define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */
543 #define USB_DEVICE_INTENSET_MSOF (_U_(0x1) << USB_DEVICE_INTENSET_MSOF_Pos)
544 #define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */
545 #define USB_DEVICE_INTENSET_SOF (_U_(0x1) << USB_DEVICE_INTENSET_SOF_Pos)
546 #define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */
547 #define USB_DEVICE_INTENSET_EORST (_U_(0x1) << USB_DEVICE_INTENSET_EORST_Pos)
548 #define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */
549 #define USB_DEVICE_INTENSET_WAKEUP (_U_(0x1) << USB_DEVICE_INTENSET_WAKEUP_Pos)
550 #define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */
551 #define USB_DEVICE_INTENSET_EORSM (_U_(0x1) << USB_DEVICE_INTENSET_EORSM_Pos)
552 #define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */
553 #define USB_DEVICE_INTENSET_UPRSM (_U_(0x1) << USB_DEVICE_INTENSET_UPRSM_Pos)
554 #define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */
555 #define USB_DEVICE_INTENSET_RAMACER (_U_(0x1) << USB_DEVICE_INTENSET_RAMACER_Pos)
556 #define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */
557 #define USB_DEVICE_INTENSET_LPMNYET (_U_(0x1) << USB_DEVICE_INTENSET_LPMNYET_Pos)
558 #define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */
559 #define USB_DEVICE_INTENSET_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENSET_LPMSUSP_Pos)
560 #define USB_DEVICE_INTENSET_MASK _U_(0x03FF) /**< \brief (USB_DEVICE_INTENSET) MASK Register */
562 /* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
563 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
566 uint16_t :2; /*!< bit: 0.. 1 Reserved */
567 uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
568 uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
569 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
570 uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
571 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
572 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
573 uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
574 uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
575 uint16_t :6; /*!< bit: 10..15 Reserved */
576 } bit; /*!< Structure used for bit access */
577 uint16_t reg; /*!< Type used for register access */
578 } USB_HOST_INTENSET_Type;
579 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
581 #define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */
582 #define USB_HOST_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */
584 #define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */
585 #define USB_HOST_INTENSET_HSOF (_U_(0x1) << USB_HOST_INTENSET_HSOF_Pos)
586 #define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */
587 #define USB_HOST_INTENSET_RST (_U_(0x1) << USB_HOST_INTENSET_RST_Pos)
588 #define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */
589 #define USB_HOST_INTENSET_WAKEUP (_U_(0x1) << USB_HOST_INTENSET_WAKEUP_Pos)
590 #define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */
591 #define USB_HOST_INTENSET_DNRSM (_U_(0x1) << USB_HOST_INTENSET_DNRSM_Pos)
592 #define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */
593 #define USB_HOST_INTENSET_UPRSM (_U_(0x1) << USB_HOST_INTENSET_UPRSM_Pos)
594 #define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */
595 #define USB_HOST_INTENSET_RAMACER (_U_(0x1) << USB_HOST_INTENSET_RAMACER_Pos)
596 #define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */
597 #define USB_HOST_INTENSET_DCONN (_U_(0x1) << USB_HOST_INTENSET_DCONN_Pos)
598 #define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */
599 #define USB_HOST_INTENSET_DDISC (_U_(0x1) << USB_HOST_INTENSET_DDISC_Pos)
600 #define USB_HOST_INTENSET_MASK _U_(0x03FC) /**< \brief (USB_HOST_INTENSET) MASK Register */
602 /* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
603 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
604 typedef union { // __I to avoid read-modify-write on write-to-clear register
606 __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
607 __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
608 __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
609 __I uint16_t EORST:1; /*!< bit: 3 End of Reset */
610 __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
611 __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
612 __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
613 __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
614 __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
615 __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
616 __I uint16_t :6; /*!< bit: 10..15 Reserved */
617 } bit; /*!< Structure used for bit access */
618 uint16_t reg; /*!< Type used for register access */
619 } USB_DEVICE_INTFLAG_Type;
620 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
622 #define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */
623 #define USB_DEVICE_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */
625 #define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */
626 #define USB_DEVICE_INTFLAG_SUSPEND (_U_(0x1) << USB_DEVICE_INTFLAG_SUSPEND_Pos)
627 #define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */
628 #define USB_DEVICE_INTFLAG_MSOF (_U_(0x1) << USB_DEVICE_INTFLAG_MSOF_Pos)
629 #define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */
630 #define USB_DEVICE_INTFLAG_SOF (_U_(0x1) << USB_DEVICE_INTFLAG_SOF_Pos)
631 #define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */
632 #define USB_DEVICE_INTFLAG_EORST (_U_(0x1) << USB_DEVICE_INTFLAG_EORST_Pos)
633 #define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */
634 #define USB_DEVICE_INTFLAG_WAKEUP (_U_(0x1) << USB_DEVICE_INTFLAG_WAKEUP_Pos)
635 #define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */
636 #define USB_DEVICE_INTFLAG_EORSM (_U_(0x1) << USB_DEVICE_INTFLAG_EORSM_Pos)
637 #define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */
638 #define USB_DEVICE_INTFLAG_UPRSM (_U_(0x1) << USB_DEVICE_INTFLAG_UPRSM_Pos)
639 #define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */
640 #define USB_DEVICE_INTFLAG_RAMACER (_U_(0x1) << USB_DEVICE_INTFLAG_RAMACER_Pos)
641 #define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */
642 #define USB_DEVICE_INTFLAG_LPMNYET (_U_(0x1) << USB_DEVICE_INTFLAG_LPMNYET_Pos)
643 #define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */
644 #define USB_DEVICE_INTFLAG_LPMSUSP (_U_(0x1) << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
645 #define USB_DEVICE_INTFLAG_MASK _U_(0x03FF) /**< \brief (USB_DEVICE_INTFLAG) MASK Register */
647 /* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
648 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
649 typedef union { // __I to avoid read-modify-write on write-to-clear register
651 __I uint16_t :2; /*!< bit: 0.. 1 Reserved */
652 __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
653 __I uint16_t RST:1; /*!< bit: 3 Bus Reset */
654 __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
655 __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */
656 __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
657 __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
658 __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */
659 __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
660 __I uint16_t :6; /*!< bit: 10..15 Reserved */
661 } bit; /*!< Structure used for bit access */
662 uint16_t reg; /*!< Type used for register access */
663 } USB_HOST_INTFLAG_Type;
664 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
666 #define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */
667 #define USB_HOST_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */
669 #define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */
670 #define USB_HOST_INTFLAG_HSOF (_U_(0x1) << USB_HOST_INTFLAG_HSOF_Pos)
671 #define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */
672 #define USB_HOST_INTFLAG_RST (_U_(0x1) << USB_HOST_INTFLAG_RST_Pos)
673 #define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */
674 #define USB_HOST_INTFLAG_WAKEUP (_U_(0x1) << USB_HOST_INTFLAG_WAKEUP_Pos)
675 #define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */
676 #define USB_HOST_INTFLAG_DNRSM (_U_(0x1) << USB_HOST_INTFLAG_DNRSM_Pos)
677 #define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */
678 #define USB_HOST_INTFLAG_UPRSM (_U_(0x1) << USB_HOST_INTFLAG_UPRSM_Pos)
679 #define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */
680 #define USB_HOST_INTFLAG_RAMACER (_U_(0x1) << USB_HOST_INTFLAG_RAMACER_Pos)
681 #define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */
682 #define USB_HOST_INTFLAG_DCONN (_U_(0x1) << USB_HOST_INTFLAG_DCONN_Pos)
683 #define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */
684 #define USB_HOST_INTFLAG_DDISC (_U_(0x1) << USB_HOST_INTFLAG_DDISC_Pos)
685 #define USB_HOST_INTFLAG_MASK _U_(0x03FC) /**< \brief (USB_HOST_INTFLAG) MASK Register */
687 /* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */
688 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
691 uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
692 uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
693 uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
694 uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
695 uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
696 uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
697 uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
698 uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
699 uint16_t :8; /*!< bit: 8..15 Reserved */
700 } bit; /*!< Structure used for bit access */
702 uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
703 uint16_t :8; /*!< bit: 8..15 Reserved */
704 } vec; /*!< Structure used for vec access */
705 uint16_t reg; /*!< Type used for register access */
706 } USB_DEVICE_EPINTSMRY_Type;
707 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
709 #define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */
710 #define USB_DEVICE_EPINTSMRY_RESETVALUE _U_(0x0000) /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */
712 #define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */
713 #define USB_DEVICE_EPINTSMRY_EPINT0 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
714 #define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */
715 #define USB_DEVICE_EPINTSMRY_EPINT1 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
716 #define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */
717 #define USB_DEVICE_EPINTSMRY_EPINT2 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
718 #define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */
719 #define USB_DEVICE_EPINTSMRY_EPINT3 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
720 #define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */
721 #define USB_DEVICE_EPINTSMRY_EPINT4 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
722 #define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */
723 #define USB_DEVICE_EPINTSMRY_EPINT5 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
724 #define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */
725 #define USB_DEVICE_EPINTSMRY_EPINT6 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
726 #define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */
727 #define USB_DEVICE_EPINTSMRY_EPINT7 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
728 #define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
729 #define USB_DEVICE_EPINTSMRY_EPINT_Msk (_U_(0xFF) << USB_DEVICE_EPINTSMRY_EPINT_Pos)
730 #define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))
731 #define USB_DEVICE_EPINTSMRY_MASK _U_(0x00FF) /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
733 /* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */
734 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
737 uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
738 uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
739 uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
740 uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
741 uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
742 uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
743 uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
744 uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
745 uint16_t :8; /*!< bit: 8..15 Reserved */
746 } bit; /*!< Structure used for bit access */
748 uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
749 uint16_t :8; /*!< bit: 8..15 Reserved */
750 } vec; /*!< Structure used for vec access */
751 uint16_t reg; /*!< Type used for register access */
752 } USB_HOST_PINTSMRY_Type;
753 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
755 #define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */
756 #define USB_HOST_PINTSMRY_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */
758 #define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */
759 #define USB_HOST_PINTSMRY_EPINT0 (_U_(1) << USB_HOST_PINTSMRY_EPINT0_Pos)
760 #define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */
761 #define USB_HOST_PINTSMRY_EPINT1 (_U_(1) << USB_HOST_PINTSMRY_EPINT1_Pos)
762 #define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */
763 #define USB_HOST_PINTSMRY_EPINT2 (_U_(1) << USB_HOST_PINTSMRY_EPINT2_Pos)
764 #define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */
765 #define USB_HOST_PINTSMRY_EPINT3 (_U_(1) << USB_HOST_PINTSMRY_EPINT3_Pos)
766 #define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */
767 #define USB_HOST_PINTSMRY_EPINT4 (_U_(1) << USB_HOST_PINTSMRY_EPINT4_Pos)
768 #define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */
769 #define USB_HOST_PINTSMRY_EPINT5 (_U_(1) << USB_HOST_PINTSMRY_EPINT5_Pos)
770 #define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */
771 #define USB_HOST_PINTSMRY_EPINT6 (_U_(1) << USB_HOST_PINTSMRY_EPINT6_Pos)
772 #define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */
773 #define USB_HOST_PINTSMRY_EPINT7 (_U_(1) << USB_HOST_PINTSMRY_EPINT7_Pos)
774 #define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
775 #define USB_HOST_PINTSMRY_EPINT_Msk (_U_(0xFF) << USB_HOST_PINTSMRY_EPINT_Pos)
776 #define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))
777 #define USB_HOST_PINTSMRY_MASK _U_(0x00FF) /**< \brief (USB_HOST_PINTSMRY) MASK Register */
779 /* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
780 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
783 uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
784 } bit; /*!< Structure used for bit access */
785 uint32_t reg; /*!< Type used for register access */
787 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
789 #define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */
790 #define USB_DESCADD_RESETVALUE _U_(0x00000000) /**< \brief (USB_DESCADD reset_value) Descriptor Address */
792 #define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */
793 #define USB_DESCADD_DESCADD_Msk (_U_(0xFFFFFFFF) << USB_DESCADD_DESCADD_Pos)
794 #define USB_DESCADD_DESCADD(value) (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))
795 #define USB_DESCADD_MASK _U_(0xFFFFFFFF) /**< \brief (USB_DESCADD) MASK Register */
797 /* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
798 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
801 uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
802 uint16_t :1; /*!< bit: 5 Reserved */
803 uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
804 uint16_t :1; /*!< bit: 11 Reserved */
805 uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
806 uint16_t :1; /*!< bit: 15 Reserved */
807 } bit; /*!< Structure used for bit access */
808 uint16_t reg; /*!< Type used for register access */
810 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
812 #define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */
813 #define USB_PADCAL_RESETVALUE _U_(0x0000) /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */
815 #define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */
816 #define USB_PADCAL_TRANSP_Msk (_U_(0x1F) << USB_PADCAL_TRANSP_Pos)
817 #define USB_PADCAL_TRANSP(value) (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))
818 #define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */
819 #define USB_PADCAL_TRANSN_Msk (_U_(0x1F) << USB_PADCAL_TRANSN_Pos)
820 #define USB_PADCAL_TRANSN(value) (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))
821 #define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */
822 #define USB_PADCAL_TRIM_Msk (_U_(0x7) << USB_PADCAL_TRIM_Pos)
823 #define USB_PADCAL_TRIM(value) (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))
824 #define USB_PADCAL_MASK _U_(0x77DF) /**< \brief (USB_PADCAL) MASK Register */
826 /* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
827 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
830 uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
831 uint8_t :1; /*!< bit: 3 Reserved */
832 uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
833 uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
834 } bit; /*!< Structure used for bit access */
835 uint8_t reg; /*!< Type used for register access */
836 } USB_DEVICE_EPCFG_Type;
837 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
839 #define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */
840 #define USB_DEVICE_EPCFG_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */
842 #define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
843 #define USB_DEVICE_EPCFG_EPTYPE0_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE0_Pos)
844 #define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))
845 #define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
846 #define USB_DEVICE_EPCFG_EPTYPE1_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE1_Pos)
847 #define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))
848 #define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
849 #define USB_DEVICE_EPCFG_NYETDIS (_U_(0x1) << USB_DEVICE_EPCFG_NYETDIS_Pos)
850 #define USB_DEVICE_EPCFG_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPCFG) MASK Register */
852 /* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */
853 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
856 uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
857 uint8_t BK:1; /*!< bit: 2 Pipe Bank */
858 uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
859 uint8_t :2; /*!< bit: 6.. 7 Reserved */
860 } bit; /*!< Structure used for bit access */
861 uint8_t reg; /*!< Type used for register access */
862 } USB_HOST_PCFG_Type;
863 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
865 #define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */
866 #define USB_HOST_PCFG_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */
868 #define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */
869 #define USB_HOST_PCFG_PTOKEN_Msk (_U_(0x3) << USB_HOST_PCFG_PTOKEN_Pos)
870 #define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))
871 #define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */
872 #define USB_HOST_PCFG_BK (_U_(0x1) << USB_HOST_PCFG_BK_Pos)
873 #define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */
874 #define USB_HOST_PCFG_PTYPE_Msk (_U_(0x7) << USB_HOST_PCFG_PTYPE_Pos)
875 #define USB_HOST_PCFG_PTYPE(value) (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))
876 #define USB_HOST_PCFG_MASK _U_(0x3F) /**< \brief (USB_HOST_PCFG) MASK Register */
878 /* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
879 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
882 uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
883 } bit; /*!< Structure used for bit access */
884 uint8_t reg; /*!< Type used for register access */
885 } USB_HOST_BINTERVAL_Type;
886 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
888 #define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */
889 #define USB_HOST_BINTERVAL_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */
891 #define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
892 #define USB_HOST_BINTERVAL_BITINTERVAL_Msk (_U_(0xFF) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
893 #define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))
894 #define USB_HOST_BINTERVAL_MASK _U_(0xFF) /**< \brief (USB_HOST_BINTERVAL) MASK Register */
896 /* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
897 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
900 uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
901 uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
902 uint8_t CURBK:1; /*!< bit: 2 Current Bank Clear */
903 uint8_t :1; /*!< bit: 3 Reserved */
904 uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
905 uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
906 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
907 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
908 } bit; /*!< Structure used for bit access */
910 uint8_t :4; /*!< bit: 0.. 3 Reserved */
911 uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
912 uint8_t :2; /*!< bit: 6.. 7 Reserved */
913 } vec; /*!< Structure used for vec access */
914 uint8_t reg; /*!< Type used for register access */
915 } USB_DEVICE_EPSTATUSCLR_Type;
916 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
918 #define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */
919 #define USB_DEVICE_EPSTATUSCLR_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */
921 #define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */
922 #define USB_DEVICE_EPSTATUSCLR_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
923 #define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */
924 #define USB_DEVICE_EPSTATUSCLR_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
925 #define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Current Bank Clear */
926 #define USB_DEVICE_EPSTATUSCLR_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
927 #define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */
928 #define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
929 #define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */
930 #define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
931 #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
932 #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
933 #define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))
934 #define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
935 #define USB_DEVICE_EPSTATUSCLR_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
936 #define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
937 #define USB_DEVICE_EPSTATUSCLR_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
938 #define USB_DEVICE_EPSTATUSCLR_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */
940 /* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
941 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
944 uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
945 uint8_t :1; /*!< bit: 1 Reserved */
946 uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
947 uint8_t :1; /*!< bit: 3 Reserved */
948 uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
949 uint8_t :1; /*!< bit: 5 Reserved */
950 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
951 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
952 } bit; /*!< Structure used for bit access */
953 uint8_t reg; /*!< Type used for register access */
954 } USB_HOST_PSTATUSCLR_Type;
955 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
957 #define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */
958 #define USB_HOST_PSTATUSCLR_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */
960 #define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */
961 #define USB_HOST_PSTATUSCLR_DTGL (_U_(0x1) << USB_HOST_PSTATUSCLR_DTGL_Pos)
962 #define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */
963 #define USB_HOST_PSTATUSCLR_CURBK (_U_(0x1) << USB_HOST_PSTATUSCLR_CURBK_Pos)
964 #define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */
965 #define USB_HOST_PSTATUSCLR_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
966 #define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */
967 #define USB_HOST_PSTATUSCLR_BK0RDY (_U_(0x1) << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
968 #define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */
969 #define USB_HOST_PSTATUSCLR_BK1RDY (_U_(0x1) << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
970 #define USB_HOST_PSTATUSCLR_MASK _U_(0xD5) /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */
972 /* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
973 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
976 uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
977 uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
978 uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
979 uint8_t :1; /*!< bit: 3 Reserved */
980 uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
981 uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
982 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
983 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
984 } bit; /*!< Structure used for bit access */
986 uint8_t :4; /*!< bit: 0.. 3 Reserved */
987 uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
988 uint8_t :2; /*!< bit: 6.. 7 Reserved */
989 } vec; /*!< Structure used for vec access */
990 uint8_t reg; /*!< Type used for register access */
991 } USB_DEVICE_EPSTATUSSET_Type;
992 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
994 #define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */
995 #define USB_DEVICE_EPSTATUSSET_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */
997 #define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */
998 #define USB_DEVICE_EPSTATUSSET_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
999 #define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */
1000 #define USB_DEVICE_EPSTATUSSET_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
1001 #define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */
1002 #define USB_DEVICE_EPSTATUSSET_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
1003 #define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */
1004 #define USB_DEVICE_EPSTATUSSET_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
1005 #define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */
1006 #define USB_DEVICE_EPSTATUSSET_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
1007 #define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
1008 #define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
1009 #define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))
1010 #define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
1011 #define USB_DEVICE_EPSTATUSSET_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
1012 #define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
1013 #define USB_DEVICE_EPSTATUSSET_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
1014 #define USB_DEVICE_EPSTATUSSET_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */
1016 /* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */
1017 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1020 uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
1021 uint8_t :1; /*!< bit: 1 Reserved */
1022 uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
1023 uint8_t :1; /*!< bit: 3 Reserved */
1024 uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
1025 uint8_t :1; /*!< bit: 5 Reserved */
1026 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
1027 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
1028 } bit; /*!< Structure used for bit access */
1029 uint8_t reg; /*!< Type used for register access */
1030 } USB_HOST_PSTATUSSET_Type;
1031 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1033 #define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */
1034 #define USB_HOST_PSTATUSSET_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */
1036 #define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */
1037 #define USB_HOST_PSTATUSSET_DTGL (_U_(0x1) << USB_HOST_PSTATUSSET_DTGL_Pos)
1038 #define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */
1039 #define USB_HOST_PSTATUSSET_CURBK (_U_(0x1) << USB_HOST_PSTATUSSET_CURBK_Pos)
1040 #define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */
1041 #define USB_HOST_PSTATUSSET_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSSET_PFREEZE_Pos)
1042 #define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */
1043 #define USB_HOST_PSTATUSSET_BK0RDY (_U_(0x1) << USB_HOST_PSTATUSSET_BK0RDY_Pos)
1044 #define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */
1045 #define USB_HOST_PSTATUSSET_BK1RDY (_U_(0x1) << USB_HOST_PSTATUSSET_BK1RDY_Pos)
1046 #define USB_HOST_PSTATUSSET_MASK _U_(0xD5) /**< \brief (USB_HOST_PSTATUSSET) MASK Register */
1048 /* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
1049 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1052 uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
1053 uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
1054 uint8_t CURBK:1; /*!< bit: 2 Current Bank */
1055 uint8_t :1; /*!< bit: 3 Reserved */
1056 uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
1057 uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
1058 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
1059 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
1060 } bit; /*!< Structure used for bit access */
1062 uint8_t :4; /*!< bit: 0.. 3 Reserved */
1063 uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
1064 uint8_t :2; /*!< bit: 6.. 7 Reserved */
1065 } vec; /*!< Structure used for vec access */
1066 uint8_t reg; /*!< Type used for register access */
1067 } USB_DEVICE_EPSTATUS_Type;
1068 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1070 #define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */
1071 #define USB_DEVICE_EPSTATUS_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */
1073 #define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */
1074 #define USB_DEVICE_EPSTATUS_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
1075 #define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */
1076 #define USB_DEVICE_EPSTATUS_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
1077 #define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */
1078 #define USB_DEVICE_EPSTATUS_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUS_CURBK_Pos)
1079 #define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */
1080 #define USB_DEVICE_EPSTATUS_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
1081 #define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */
1082 #define USB_DEVICE_EPSTATUS_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
1083 #define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
1084 #define USB_DEVICE_EPSTATUS_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
1085 #define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))
1086 #define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
1087 #define USB_DEVICE_EPSTATUS_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
1088 #define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
1089 #define USB_DEVICE_EPSTATUS_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
1090 #define USB_DEVICE_EPSTATUS_MASK _U_(0xF7) /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */
1092 /* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */
1093 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1096 uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
1097 uint8_t :1; /*!< bit: 1 Reserved */
1098 uint8_t CURBK:1; /*!< bit: 2 Current Bank */
1099 uint8_t :1; /*!< bit: 3 Reserved */
1100 uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
1101 uint8_t :1; /*!< bit: 5 Reserved */
1102 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
1103 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
1104 } bit; /*!< Structure used for bit access */
1105 uint8_t reg; /*!< Type used for register access */
1106 } USB_HOST_PSTATUS_Type;
1107 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1109 #define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */
1110 #define USB_HOST_PSTATUS_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */
1112 #define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */
1113 #define USB_HOST_PSTATUS_DTGL (_U_(0x1) << USB_HOST_PSTATUS_DTGL_Pos)
1114 #define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */
1115 #define USB_HOST_PSTATUS_CURBK (_U_(0x1) << USB_HOST_PSTATUS_CURBK_Pos)
1116 #define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */
1117 #define USB_HOST_PSTATUS_PFREEZE (_U_(0x1) << USB_HOST_PSTATUS_PFREEZE_Pos)
1118 #define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */
1119 #define USB_HOST_PSTATUS_BK0RDY (_U_(0x1) << USB_HOST_PSTATUS_BK0RDY_Pos)
1120 #define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */
1121 #define USB_HOST_PSTATUS_BK1RDY (_U_(0x1) << USB_HOST_PSTATUS_BK1RDY_Pos)
1122 #define USB_HOST_PSTATUS_MASK _U_(0xD5) /**< \brief (USB_HOST_PSTATUS) MASK Register */
1124 /* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
1125 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1126 typedef union { // __I to avoid read-modify-write on write-to-clear register
1128 __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
1129 __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
1130 __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
1131 __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
1132 __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
1133 __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
1134 __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
1135 __I uint8_t :1; /*!< bit: 7 Reserved */
1136 } bit; /*!< Structure used for bit access */
1138 __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
1139 __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
1140 __I uint8_t :1; /*!< bit: 4 Reserved */
1141 __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
1142 __I uint8_t :1; /*!< bit: 7 Reserved */
1143 } vec; /*!< Structure used for vec access */
1144 uint8_t reg; /*!< Type used for register access */
1145 } USB_DEVICE_EPINTFLAG_Type;
1146 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1148 #define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */
1149 #define USB_DEVICE_EPINTFLAG_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */
1151 #define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */
1152 #define USB_DEVICE_EPINTFLAG_TRCPT0 (_U_(1) << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
1153 #define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */
1154 #define USB_DEVICE_EPINTFLAG_TRCPT1 (_U_(1) << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
1155 #define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
1156 #define USB_DEVICE_EPINTFLAG_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
1157 #define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))
1158 #define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
1159 #define USB_DEVICE_EPINTFLAG_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
1160 #define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
1161 #define USB_DEVICE_EPINTFLAG_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
1162 #define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
1163 #define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
1164 #define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))
1165 #define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
1166 #define USB_DEVICE_EPINTFLAG_RXSTP (_U_(0x1) << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
1167 #define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
1168 #define USB_DEVICE_EPINTFLAG_STALL0 (_U_(1) << USB_DEVICE_EPINTFLAG_STALL0_Pos)
1169 #define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */
1170 #define USB_DEVICE_EPINTFLAG_STALL1 (_U_(1) << USB_DEVICE_EPINTFLAG_STALL1_Pos)
1171 #define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
1172 #define USB_DEVICE_EPINTFLAG_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_STALL_Pos)
1173 #define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))
1174 #define USB_DEVICE_EPINTFLAG_MASK _U_(0x7F) /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
1176 /* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
1177 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1178 typedef union { // __I to avoid read-modify-write on write-to-clear register
1180 __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
1181 __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
1182 __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
1183 __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
1184 __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
1185 __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
1186 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
1187 } bit; /*!< Structure used for bit access */
1189 __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
1190 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
1191 } vec; /*!< Structure used for vec access */
1192 uint8_t reg; /*!< Type used for register access */
1193 } USB_HOST_PINTFLAG_Type;
1194 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1196 #define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */
1197 #define USB_HOST_PINTFLAG_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */
1199 #define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */
1200 #define USB_HOST_PINTFLAG_TRCPT0 (_U_(1) << USB_HOST_PINTFLAG_TRCPT0_Pos)
1201 #define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */
1202 #define USB_HOST_PINTFLAG_TRCPT1 (_U_(1) << USB_HOST_PINTFLAG_TRCPT1_Pos)
1203 #define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
1204 #define USB_HOST_PINTFLAG_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTFLAG_TRCPT_Pos)
1205 #define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))
1206 #define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
1207 #define USB_HOST_PINTFLAG_TRFAIL (_U_(0x1) << USB_HOST_PINTFLAG_TRFAIL_Pos)
1208 #define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
1209 #define USB_HOST_PINTFLAG_PERR (_U_(0x1) << USB_HOST_PINTFLAG_PERR_Pos)
1210 #define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */
1211 #define USB_HOST_PINTFLAG_TXSTP (_U_(0x1) << USB_HOST_PINTFLAG_TXSTP_Pos)
1212 #define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */
1213 #define USB_HOST_PINTFLAG_STALL (_U_(0x1) << USB_HOST_PINTFLAG_STALL_Pos)
1214 #define USB_HOST_PINTFLAG_MASK _U_(0x3F) /**< \brief (USB_HOST_PINTFLAG) MASK Register */
1216 /* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
1217 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1220 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
1221 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
1222 uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
1223 uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
1224 uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
1225 uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
1226 uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
1227 uint8_t :1; /*!< bit: 7 Reserved */
1228 } bit; /*!< Structure used for bit access */
1230 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
1231 uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
1232 uint8_t :1; /*!< bit: 4 Reserved */
1233 uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
1234 uint8_t :1; /*!< bit: 7 Reserved */
1235 } vec; /*!< Structure used for vec access */
1236 uint8_t reg; /*!< Type used for register access */
1237 } USB_DEVICE_EPINTENCLR_Type;
1238 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1240 #define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
1241 #define USB_DEVICE_EPINTENCLR_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
1243 #define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */
1244 #define USB_DEVICE_EPINTENCLR_TRCPT0 (_U_(1) << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
1245 #define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */
1246 #define USB_DEVICE_EPINTENCLR_TRCPT1 (_U_(1) << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
1247 #define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
1248 #define USB_DEVICE_EPINTENCLR_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
1249 #define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))
1250 #define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
1251 #define USB_DEVICE_EPINTENCLR_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
1252 #define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
1253 #define USB_DEVICE_EPINTENCLR_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
1254 #define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
1255 #define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
1256 #define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))
1257 #define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
1258 #define USB_DEVICE_EPINTENCLR_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
1259 #define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
1260 #define USB_DEVICE_EPINTENCLR_STALL0 (_U_(1) << USB_DEVICE_EPINTENCLR_STALL0_Pos)
1261 #define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */
1262 #define USB_DEVICE_EPINTENCLR_STALL1 (_U_(1) << USB_DEVICE_EPINTENCLR_STALL1_Pos)
1263 #define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
1264 #define USB_DEVICE_EPINTENCLR_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_STALL_Pos)
1265 #define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))
1266 #define USB_DEVICE_EPINTENCLR_MASK _U_(0x7F) /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
1268 /* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
1269 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1272 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
1273 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
1274 uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
1275 uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
1276 uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
1277 uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */
1278 uint8_t :2; /*!< bit: 6.. 7 Reserved */
1279 } bit; /*!< Structure used for bit access */
1281 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
1282 uint8_t :6; /*!< bit: 2.. 7 Reserved */
1283 } vec; /*!< Structure used for vec access */
1284 uint8_t reg; /*!< Type used for register access */
1285 } USB_HOST_PINTENCLR_Type;
1286 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1288 #define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */
1289 #define USB_HOST_PINTENCLR_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */
1291 #define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */
1292 #define USB_HOST_PINTENCLR_TRCPT0 (_U_(1) << USB_HOST_PINTENCLR_TRCPT0_Pos)
1293 #define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */
1294 #define USB_HOST_PINTENCLR_TRCPT1 (_U_(1) << USB_HOST_PINTENCLR_TRCPT1_Pos)
1295 #define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
1296 #define USB_HOST_PINTENCLR_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENCLR_TRCPT_Pos)
1297 #define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))
1298 #define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
1299 #define USB_HOST_PINTENCLR_TRFAIL (_U_(0x1) << USB_HOST_PINTENCLR_TRFAIL_Pos)
1300 #define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
1301 #define USB_HOST_PINTENCLR_PERR (_U_(0x1) << USB_HOST_PINTENCLR_PERR_Pos)
1302 #define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */
1303 #define USB_HOST_PINTENCLR_TXSTP (_U_(0x1) << USB_HOST_PINTENCLR_TXSTP_Pos)
1304 #define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */
1305 #define USB_HOST_PINTENCLR_STALL (_U_(0x1) << USB_HOST_PINTENCLR_STALL_Pos)
1306 #define USB_HOST_PINTENCLR_MASK _U_(0x3F) /**< \brief (USB_HOST_PINTENCLR) MASK Register */
1308 /* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
1309 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1312 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
1313 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
1314 uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
1315 uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
1316 uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
1317 uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
1318 uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
1319 uint8_t :1; /*!< bit: 7 Reserved */
1320 } bit; /*!< Structure used for bit access */
1322 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
1323 uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
1324 uint8_t :1; /*!< bit: 4 Reserved */
1325 uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
1326 uint8_t :1; /*!< bit: 7 Reserved */
1327 } vec; /*!< Structure used for vec access */
1328 uint8_t reg; /*!< Type used for register access */
1329 } USB_DEVICE_EPINTENSET_Type;
1330 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1332 #define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */
1333 #define USB_DEVICE_EPINTENSET_RESETVALUE _U_(0x00) /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */
1335 #define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */
1336 #define USB_DEVICE_EPINTENSET_TRCPT0 (_U_(1) << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
1337 #define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */
1338 #define USB_DEVICE_EPINTENSET_TRCPT1 (_U_(1) << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
1339 #define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
1340 #define USB_DEVICE_EPINTENSET_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRCPT_Pos)
1341 #define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))
1342 #define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
1343 #define USB_DEVICE_EPINTENSET_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
1344 #define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
1345 #define USB_DEVICE_EPINTENSET_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
1346 #define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
1347 #define USB_DEVICE_EPINTENSET_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
1348 #define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))
1349 #define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
1350 #define USB_DEVICE_EPINTENSET_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENSET_RXSTP_Pos)
1351 #define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
1352 #define USB_DEVICE_EPINTENSET_STALL0 (_U_(1) << USB_DEVICE_EPINTENSET_STALL0_Pos)
1353 #define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */
1354 #define USB_DEVICE_EPINTENSET_STALL1 (_U_(1) << USB_DEVICE_EPINTENSET_STALL1_Pos)
1355 #define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
1356 #define USB_DEVICE_EPINTENSET_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_STALL_Pos)
1357 #define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))
1358 #define USB_DEVICE_EPINTENSET_MASK _U_(0x7F) /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
1360 /* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
1361 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1364 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
1365 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
1366 uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
1367 uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
1368 uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
1369 uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
1370 uint8_t :2; /*!< bit: 6.. 7 Reserved */
1371 } bit; /*!< Structure used for bit access */
1373 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
1374 uint8_t :6; /*!< bit: 2.. 7 Reserved */
1375 } vec; /*!< Structure used for vec access */
1376 uint8_t reg; /*!< Type used for register access */
1377 } USB_HOST_PINTENSET_Type;
1378 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1380 #define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */
1381 #define USB_HOST_PINTENSET_RESETVALUE _U_(0x00) /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */
1383 #define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */
1384 #define USB_HOST_PINTENSET_TRCPT0 (_U_(1) << USB_HOST_PINTENSET_TRCPT0_Pos)
1385 #define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */
1386 #define USB_HOST_PINTENSET_TRCPT1 (_U_(1) << USB_HOST_PINTENSET_TRCPT1_Pos)
1387 #define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
1388 #define USB_HOST_PINTENSET_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENSET_TRCPT_Pos)
1389 #define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))
1390 #define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
1391 #define USB_HOST_PINTENSET_TRFAIL (_U_(0x1) << USB_HOST_PINTENSET_TRFAIL_Pos)
1392 #define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
1393 #define USB_HOST_PINTENSET_PERR (_U_(0x1) << USB_HOST_PINTENSET_PERR_Pos)
1394 #define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */
1395 #define USB_HOST_PINTENSET_TXSTP (_U_(0x1) << USB_HOST_PINTENSET_TXSTP_Pos)
1396 #define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */
1397 #define USB_HOST_PINTENSET_STALL (_U_(0x1) << USB_HOST_PINTENSET_STALL_Pos)
1398 #define USB_HOST_PINTENSET_MASK _U_(0x3F) /**< \brief (USB_HOST_PINTENSET) MASK Register */
1400 /* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
1401 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1404 uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
1405 } bit; /*!< Structure used for bit access */
1406 uint32_t reg; /*!< Type used for register access */
1407 } USB_DEVICE_ADDR_Type;
1408 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1410 #define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
1412 #define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
1413 #define USB_DEVICE_ADDR_ADDR_Msk (_U_(0xFFFFFFFF) << USB_DEVICE_ADDR_ADDR_Pos)
1414 #define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))
1415 #define USB_DEVICE_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (USB_DEVICE_ADDR) MASK Register */
1417 /* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
1418 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1421 uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
1422 } bit; /*!< Structure used for bit access */
1423 uint32_t reg; /*!< Type used for register access */
1424 } USB_HOST_ADDR_Type;
1425 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1427 #define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
1429 #define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */
1430 #define USB_HOST_ADDR_ADDR_Msk (_U_(0xFFFFFFFF) << USB_HOST_ADDR_ADDR_Pos)
1431 #define USB_HOST_ADDR_ADDR(value) (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))
1432 #define USB_HOST_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (USB_HOST_ADDR) MASK Register */
1434 /* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
1435 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1438 uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
1439 uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
1440 uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
1441 uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
1442 } bit; /*!< Structure used for bit access */
1443 uint32_t reg; /*!< Type used for register access */
1444 } USB_DEVICE_PCKSIZE_Type;
1445 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1447 #define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
1449 #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
1450 #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
1451 #define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))
1452 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
1453 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
1454 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))
1455 #define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
1456 #define USB_DEVICE_PCKSIZE_SIZE_Msk (_U_(0x7) << USB_DEVICE_PCKSIZE_SIZE_Pos)
1457 #define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))
1458 #define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
1459 #define USB_DEVICE_PCKSIZE_AUTO_ZLP (_U_(0x1) << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
1460 #define USB_DEVICE_PCKSIZE_MASK _U_(0xFFFFFFFF) /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
1462 /* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
1463 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1466 uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
1467 uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
1468 uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
1469 uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
1470 } bit; /*!< Structure used for bit access */
1471 uint32_t reg; /*!< Type used for register access */
1472 } USB_HOST_PCKSIZE_Type;
1473 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1475 #define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */
1477 #define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */
1478 #define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
1479 #define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))
1480 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
1481 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
1482 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))
1483 #define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */
1484 #define USB_HOST_PCKSIZE_SIZE_Msk (_U_(0x7) << USB_HOST_PCKSIZE_SIZE_Pos)
1485 #define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))
1486 #define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
1487 #define USB_HOST_PCKSIZE_AUTO_ZLP (_U_(0x1) << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
1488 #define USB_HOST_PCKSIZE_MASK _U_(0xFFFFFFFF) /**< \brief (USB_HOST_PCKSIZE) MASK Register */
1490 /* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
1491 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1494 uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
1495 uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
1496 uint16_t :1; /*!< bit: 15 Reserved */
1497 } bit; /*!< Structure used for bit access */
1498 uint16_t reg; /*!< Type used for register access */
1499 } USB_DEVICE_EXTREG_Type;
1500 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1502 #define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */
1504 #define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
1505 #define USB_DEVICE_EXTREG_SUBPID_Msk (_U_(0xF) << USB_DEVICE_EXTREG_SUBPID_Pos)
1506 #define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))
1507 #define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
1508 #define USB_DEVICE_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_DEVICE_EXTREG_VARIABLE_Pos)
1509 #define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))
1510 #define USB_DEVICE_EXTREG_MASK _U_(0x7FFF) /**< \brief (USB_DEVICE_EXTREG) MASK Register */
1512 /* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
1513 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1516 uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
1517 uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
1518 uint16_t :1; /*!< bit: 15 Reserved */
1519 } bit; /*!< Structure used for bit access */
1520 uint16_t reg; /*!< Type used for register access */
1521 } USB_HOST_EXTREG_Type;
1522 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1524 #define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */
1526 #define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
1527 #define USB_HOST_EXTREG_SUBPID_Msk (_U_(0xF) << USB_HOST_EXTREG_SUBPID_Pos)
1528 #define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))
1529 #define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
1530 #define USB_HOST_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_HOST_EXTREG_VARIABLE_Pos)
1531 #define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))
1532 #define USB_HOST_EXTREG_MASK _U_(0x7FFF) /**< \brief (USB_HOST_EXTREG) MASK Register */
1534 /* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
1535 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1538 uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
1539 uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
1540 uint8_t :6; /*!< bit: 2.. 7 Reserved */
1541 } bit; /*!< Structure used for bit access */
1542 uint8_t reg; /*!< Type used for register access */
1543 } USB_DEVICE_STATUS_BK_Type;
1544 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1546 #define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
1548 #define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */
1549 #define USB_DEVICE_STATUS_BK_CRCERR (_U_(0x1) << USB_DEVICE_STATUS_BK_CRCERR_Pos)
1550 #define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */
1551 #define USB_DEVICE_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
1552 #define USB_DEVICE_STATUS_BK_MASK _U_(0x03) /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */
1554 /* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
1555 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1558 uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
1559 uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
1560 uint8_t :6; /*!< bit: 2.. 7 Reserved */
1561 } bit; /*!< Structure used for bit access */
1562 uint8_t reg; /*!< Type used for register access */
1563 } USB_HOST_STATUS_BK_Type;
1564 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1566 #define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */
1568 #define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */
1569 #define USB_HOST_STATUS_BK_CRCERR (_U_(0x1) << USB_HOST_STATUS_BK_CRCERR_Pos)
1570 #define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */
1571 #define USB_HOST_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
1572 #define USB_HOST_STATUS_BK_MASK _U_(0x03) /**< \brief (USB_HOST_STATUS_BK) MASK Register */
1574 /* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
1575 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1578 uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
1579 uint16_t :1; /*!< bit: 7 Reserved */
1580 uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
1581 uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
1582 } bit; /*!< Structure used for bit access */
1583 uint16_t reg; /*!< Type used for register access */
1584 } USB_HOST_CTRL_PIPE_Type;
1585 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1587 #define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */
1588 #define USB_HOST_CTRL_PIPE_RESETVALUE _U_(0x0000) /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */
1590 #define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
1591 #define USB_HOST_CTRL_PIPE_PDADDR_Msk (_U_(0x7F) << USB_HOST_CTRL_PIPE_PDADDR_Pos)
1592 #define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))
1593 #define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
1594 #define USB_HOST_CTRL_PIPE_PEPNUM_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
1595 #define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))
1596 #define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
1597 #define USB_HOST_CTRL_PIPE_PERMAX_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PERMAX_Pos)
1598 #define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))
1599 #define USB_HOST_CTRL_PIPE_MASK _U_(0xFF7F) /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
1601 /* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
1602 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1605 uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
1606 uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
1607 uint16_t PIDER:1; /*!< bit: 2 PID Error */
1608 uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
1609 uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
1610 uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
1611 uint16_t :8; /*!< bit: 8..15 Reserved */
1612 } bit; /*!< Structure used for bit access */
1613 uint16_t reg; /*!< Type used for register access */
1614 } USB_HOST_STATUS_PIPE_Type;
1615 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1617 #define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */
1619 #define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */
1620 #define USB_HOST_STATUS_PIPE_DTGLER (_U_(0x1) << USB_HOST_STATUS_PIPE_DTGLER_Pos)
1621 #define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */
1622 #define USB_HOST_STATUS_PIPE_DAPIDER (_U_(0x1) << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
1623 #define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */
1624 #define USB_HOST_STATUS_PIPE_PIDER (_U_(0x1) << USB_HOST_STATUS_PIPE_PIDER_Pos)
1625 #define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */
1626 #define USB_HOST_STATUS_PIPE_TOUTER (_U_(0x1) << USB_HOST_STATUS_PIPE_TOUTER_Pos)
1627 #define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */
1628 #define USB_HOST_STATUS_PIPE_CRC16ER (_U_(0x1) << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
1629 #define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
1630 #define USB_HOST_STATUS_PIPE_ERCNT_Msk (_U_(0x7) << USB_HOST_STATUS_PIPE_ERCNT_Pos)
1631 #define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))
1632 #define USB_HOST_STATUS_PIPE_MASK _U_(0x00FF) /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
1634 /** \brief UsbDeviceDescBank SRAM registers */
1635 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1637 __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
1638 __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
1639 __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
1640 __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
1641 RoReg8 Reserved1[0x5];
1642 } UsbDeviceDescBank;
1643 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1645 /** \brief UsbHostDescBank SRAM registers */
1646 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1648 __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
1649 __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
1650 __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
1651 __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
1652 RoReg8 Reserved1[0x1];
1653 __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
1654 __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
1656 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1658 /** \brief UsbDeviceEndpoint hardware registers */
1659 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1661 __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
1662 RoReg8 Reserved1[0x3];
1663 __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
1664 __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
1665 __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
1666 __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
1667 __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
1668 __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
1669 RoReg8 Reserved2[0x16];
1670 } UsbDeviceEndpoint;
1671 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1673 /** \brief UsbHostPipe hardware registers */
1674 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1676 __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
1677 RoReg8 Reserved1[0x2];
1678 __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
1679 __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
1680 __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
1681 __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
1682 __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
1683 __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
1684 __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
1685 RoReg8 Reserved2[0x16];
1687 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1689 /** \brief USB_DEVICE APB hardware registers */
1690 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1691 typedef struct { /* USB is Device */
1692 __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
1693 RoReg8 Reserved1[0x1];
1694 __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
1695 __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
1696 RoReg8 Reserved2[0x4];
1697 __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
1698 __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
1699 RoReg8 Reserved3[0x1];
1700 __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
1701 __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
1702 RoReg8 Reserved4[0x2];
1703 __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
1704 RoReg8 Reserved5[0x2];
1705 __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
1706 RoReg8 Reserved6[0x2];
1707 __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
1708 RoReg8 Reserved7[0x2];
1709 __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
1710 RoReg8 Reserved8[0x2];
1711 __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
1712 RoReg8 Reserved9[0x2];
1713 __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
1714 __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
1715 RoReg8 Reserved10[0xD6];
1716 UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
1718 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1720 /** \brief USB_HOST hardware registers */
1721 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1722 typedef struct { /* USB is Host */
1723 __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
1724 RoReg8 Reserved1[0x1];
1725 __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
1726 __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
1727 RoReg8 Reserved2[0x4];
1728 __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
1729 __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
1730 RoReg8 Reserved3[0x1];
1731 __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
1732 __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
1733 RoReg8 Reserved4[0x2];
1734 __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
1735 __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
1736 RoReg8 Reserved5[0x1];
1737 __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
1738 RoReg8 Reserved6[0x2];
1739 __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
1740 RoReg8 Reserved7[0x2];
1741 __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
1742 RoReg8 Reserved8[0x2];
1743 __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
1744 RoReg8 Reserved9[0x2];
1745 __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
1746 __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
1747 RoReg8 Reserved10[0xD6];
1748 UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [PIPE_NUM*HOST_IMPLEMENTED] */
1750 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1752 /** \brief USB_DEVICE Descriptor SRAM registers */
1753 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1754 typedef struct { /* USB is Device */
1755 UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
1756 } UsbDeviceDescriptor;
1757 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1759 /** \brief USB_HOST Descriptor SRAM registers */
1760 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1761 typedef struct { /* USB is Host */
1762 UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
1763 } UsbHostDescriptor;
1764 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1766 #define SECTION_USB_DESCRIPTOR
1768 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1770 UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
1771 UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
1773 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1777 #endif /* _SAMD51_USB_COMPONENT_ */