1 flabbergast's TMK/ChibiOS port
2 ==============================
8 $ git clone -b chibios https://github.com/flabbergast/tmk_keyboard.git
11 $ git submodule add -f -b kinetis https://github.com/flabbergast/ChibiOS.git tmk_core/tool/chibios/chibios
13 $ cd tmk_keyboard/tmk_core/tool/chibios
14 $ git clone -b kinetis https://github.com/flabbergast/ChibiOS.git tmk_core/tool/chibios/chibios
16 $ cd tmk_keyboard/keyboard/infinity_chibios
24 halconf.h: for HAL configuration
25 placed in project directory
26 read in chibios/os/hal/hal.mk
27 included in chibios/os/hal/include/hal.h
28 mcuconf.h: for MCU configuration
29 placed in project directory
35 PAL = Port Abstraction Layer
39 chibios/os/hal/include/pal.h
41 LLD = Low Level Driver
46 # <chibios>/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)
50 # - it should exist either in <chibios>/os/common/ports/ARMCMx/compilers/GCC/ld/
52 MCU_LDSCRIPT = MKL26Z64
54 # - it should exist in <chibios>/os/common/ports/ARMCMx/compilers/GCC/mk/
57 # Board: it should exist either in <chibios>/os/hal/boards/
58 # or <this_dir>/boards
59 BOARD = PJRC_TEENSY_LC
63 # ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7
81 --- ../../tmk_core/tool/chibios/chibios/os/common/ports/ARMCMx/compilers/GCC/ld/MKL26Z64.ld 2015-10-15 09:08:58.732904304 +0900
82 +++ ld/MKL26Z64.ld 2015-10-15 08:48:06.430215496 +0900
85 flash0 : org = 0x00000000, len = 0xc0
86 flashcfg : org = 0x00000400, len = 0x10
87 - flash : org = 0x00000410, len = 64k - 0x410
88 + flash : org = 0x00000410, len = 62k - 0x410
89 + eeprom_emu : org = 0x0000F800, len = 2k
90 ram : org = 0x1FFFF800, len = 8k
94 __ram_size__ = LENGTH(ram);
95 __ram_end__ = __ram_start__ + __ram_size__;
97 +__eeprom_workarea_start__ = ORIGIN(eeprom_emu);
98 +__eeprom_workarea_size__ = LENGTH(eeprom_emu);
99 +__eeprom_workarea_end__ = __eeprom_workarea_start__ + __eeprom_workarea_size__;
107 Configuration/Startup for Infinity 60%
108 --------------------------------------
114 FEI(FLL Engaged Internal) mode with core clock:48MHz, bus clock:48MHz, flash clock:24MHz
116 SIM_CLKDIV1[OUTDIV1] = 0 divide-by-1 for core clock
117 SIM_CLKDIV1[OUTDIV2] = 0 divide-by-1 for bus clock
118 SIM_CLKDIV1[OUTDIV4] = 1 divide-by-2 for flash clock
119 Internal reference clock:
120 MCG_C1[IREFS] = 1 Internal Reference Select for clock source for FLL
121 MCG_C1[IRCLKEN] = 1 Internal Reference Clock Enable
124 MCG_C4[DRST_DRS] = 01 FLL factor 1464 * 32.768kHz = 48MHz
126 chibios/os/hal/ports/KINETIS/K20x/hal_lld.c
127 k20x_clock_init(): called in __early_init() defined in board.c
128 disable watchdog and configure clock
131 KINETIS_NO_INIT: whether init or not
132 KINETIS_MCG_MODE: clock mode
135 hal/ports/KINETIS/K20x/hal_lld.h
138 chibios/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h
139 PALConfig pal_default_config
142 macro definitions for board infos, freq and mcu type
144 chibios/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c
151 common/ports/ARMCMx/GCC/crt0_v[67]m.s
152 Reset_Handler: startup code
153 common/ports/ARMCMx/GCC/crt1.c
157 __default_exit(): weak
158 called from Reset_Handler of crt0
159 common/ports/ARMCMx/GCC/vector.c
160 common/ports/ARMCMx/GCC/ld/*.ld
162 chibios/os/common/ports/ARMCMx/compilers/GCC/
167 │ ├── MK20DX128BLDR3.ld
168 │ ├── MK20DX128BLDR4.ld
176 │ ├── startup_k20x5.mk
177 │ ├── startup_k20x7.mk
178 │ ├── startup_k20x.mk
179 │ ├── startup_kl2x.mk
180 │ └── startup_stm32l4xx.mk
187 │ ├── FREESCALE_FREEDOM_K20D50M
199 │ ├── PJRC_TEENSY_3_1
212 │ ├── ST_NUCLEO_F030R8
281 │ │ │ ├── kinetis_registry.h
282 │ │ │ ├── platform.dox
283 │ │ │ ├── platform.mk
291 │ │ │ ├── kinetis_registry.h
292 │ │ │ ├── platform.mk
306 │ │ │ ├── serial_lld.c
307 │ │ │ ├── serial_lld.h