1 /* Copyright 2018 Jack Humbert
2 * Copyright 2018 Yiancar
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 /* This library is only valid for STM32 processors.
19 * This library follows the convention of the AVR i2c_master library.
20 * As a result addresses are expected to be already shifted (addr << 1).
21 * I2CD1 is the default driver which corresponds to pins B6 and B7. This
23 * Please ensure that HAL_USE_I2C is TRUE in the halconf.h file and that
24 * STM32_I2C_USE_I2C1 is TRUE in the mcuconf.h file. Pins B6 and B7 are used
25 * but using any other I2C pins should be trivial.
28 #include "i2c_master.h"
33 static uint8_t i2c_address;
35 static const I2CConfig i2cconfig = {
41 STM32_TIMINGR_PRESC(I2C1_TIMINGR_PRESC) |
42 STM32_TIMINGR_SCLDEL(I2C1_TIMINGR_SCLDEL) | STM32_TIMINGR_SDADEL(I2C1_TIMINGR_SDADEL) |
43 STM32_TIMINGR_SCLH(I2C1_TIMINGR_SCLH) | STM32_TIMINGR_SCLL(I2C1_TIMINGR_SCLL),
49 static i2c_status_t chibios_to_qmk(const msg_t* status) {
52 return I2C_STATUS_SUCCESS;
54 return I2C_STATUS_TIMEOUT;
55 // I2C_BUS_ERROR, I2C_ARBITRATION_LOST, I2C_ACK_FAILURE, I2C_OVERRUN, I2C_PEC_ERROR, I2C_SMB_ALERT
57 return I2C_STATUS_ERROR;
61 __attribute__ ((weak))
64 // Try releasing special pins for a short time
65 palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_INPUT);
66 palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_INPUT);
68 chThdSleepMilliseconds(10);
71 palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
72 palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);
74 palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_ALTERNATE(I2C1_SCL_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
75 palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_ALTERNATE(I2C1_SDA_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN);
78 //i2cInit(); //This is invoked by halInit() so no need to redo it.
81 i2c_status_t i2c_start(uint8_t address)
83 i2c_address = address;
84 i2cStart(&I2C_DRIVER, &i2cconfig);
85 return I2C_STATUS_SUCCESS;
88 i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout)
90 i2c_address = address;
91 i2cStart(&I2C_DRIVER, &i2cconfig);
92 msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, 0, 0, MS2ST(timeout));
93 return chibios_to_qmk(&status);
96 i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout)
98 i2c_address = address;
99 i2cStart(&I2C_DRIVER, &i2cconfig);
100 msg_t status = i2cMasterReceiveTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, MS2ST(timeout));
101 return chibios_to_qmk(&status);
104 i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout)
106 i2c_address = devaddr;
107 i2cStart(&I2C_DRIVER, &i2cconfig);
109 uint8_t complete_packet[length + 1];
110 for(uint8_t i = 0; i < length; i++)
112 complete_packet[i+1] = data[i];
114 complete_packet[0] = regaddr;
116 msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), complete_packet, length + 1, 0, 0, MS2ST(timeout));
117 return chibios_to_qmk(&status);
120 i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t regaddr, uint8_t* data, uint16_t length, uint16_t timeout)
122 i2c_address = devaddr;
123 i2cStart(&I2C_DRIVER, &i2cconfig);
124 msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), ®addr, 1, data, length, MS2ST(timeout));
125 return chibios_to_qmk(&status);
130 i2cStop(&I2C_DRIVER);