1 /* Copyright 2018 Jack Humbert
2 * Copyright 2018 Yiancar
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 /* This library is only valid for STM32 processors.
19 * This library follows the convention of the AVR i2c_master library.
20 * As a result addresses are expected to be already shifted (addr << 1).
21 * I2CD1 is the default driver which corresponds to pins B6 and B7. This
23 * Please ensure that HAL_USE_I2C is TRUE in the halconf.h file and that
24 * STM32_I2C_USE_I2C1 is TRUE in the mcuconf.h file. Pins B6 and B7 are used
25 * but using any other I2C pins should be trivial.
28 #include "i2c_master.h"
33 static uint8_t i2c_address;
35 // This configures the I2C clock to 400khz assuming a 72Mhz clock
36 // For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
37 static const I2CConfig i2cconfig = {
38 STM32_TIMINGR_PRESC(15U) |
39 STM32_TIMINGR_SCLDEL(4U) | STM32_TIMINGR_SDADEL(2U) |
40 STM32_TIMINGR_SCLH(15U) | STM32_TIMINGR_SCLL(21U),
45 static i2c_status_t chibios_to_qmk(const msg_t* status) {
48 return I2C_STATUS_SUCCESS;
50 return I2C_STATUS_TIMEOUT;
51 // I2C_BUS_ERROR, I2C_ARBITRATION_LOST, I2C_ACK_FAILURE, I2C_OVERRUN, I2C_PEC_ERROR, I2C_SMB_ALERT
53 return I2C_STATUS_ERROR;
57 __attribute__ ((weak))
60 // Try releasing special pins for a short time
61 palSetPadMode(I2C1_BANK, I2C1_SCL, PAL_MODE_INPUT);
62 palSetPadMode(I2C1_BANK, I2C1_SDA, PAL_MODE_INPUT);
64 chThdSleepMilliseconds(10);
66 palSetPadMode(I2C1_BANK, I2C1_SCL, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN);
67 palSetPadMode(I2C1_BANK, I2C1_SDA, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN);
69 //i2cInit(); //This is invoked by halInit() so no need to redo it.
72 i2c_status_t i2c_start(uint8_t address)
74 i2c_address = address;
75 i2cStart(&I2C_DRIVER, &i2cconfig);
76 return I2C_STATUS_SUCCESS;
79 i2c_status_t i2c_transmit(uint8_t address, const uint8_t* data, uint16_t length, uint16_t timeout)
81 i2c_address = address;
82 i2cStart(&I2C_DRIVER, &i2cconfig);
83 msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, 0, 0, MS2ST(timeout));
84 return chibios_to_qmk(&status);
87 i2c_status_t i2c_receive(uint8_t address, uint8_t* data, uint16_t length, uint16_t timeout)
89 i2c_address = address;
90 i2cStart(&I2C_DRIVER, &i2cconfig);
91 msg_t status = i2cMasterReceiveTimeout(&I2C_DRIVER, (i2c_address >> 1), data, length, MS2ST(timeout));
92 return chibios_to_qmk(&status);
95 i2c_status_t i2c_writeReg(uint8_t devaddr, uint8_t regaddr, const uint8_t* data, uint16_t length, uint16_t timeout)
97 i2c_address = devaddr;
98 i2cStart(&I2C_DRIVER, &i2cconfig);
100 uint8_t complete_packet[length + 1];
101 for(uint8_t i = 0; i < length; i++)
103 complete_packet[i+1] = data[i];
105 complete_packet[0] = regaddr;
107 msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), complete_packet, length + 1, 0, 0, MS2ST(timeout));
108 return chibios_to_qmk(&status);
111 i2c_status_t i2c_readReg(uint8_t devaddr, uint8_t* regaddr, uint8_t* data, uint16_t length, uint16_t timeout)
113 i2c_address = devaddr;
114 i2cStart(&I2C_DRIVER, &i2cconfig);
115 msg_t status = i2cMasterTransmitTimeout(&I2C_DRIVER, (i2c_address >> 1), regaddr, 1, data, length, MS2ST(timeout));
116 return chibios_to_qmk(&status);
121 i2cStop(&I2C_DRIVER);