X-Git-Url: https://git.donarmstrong.com/?a=blobdiff_plain;f=Lib%2Fmk20dx.h;h=ae69dd4e7ded50760977b6f51c73ab95d036f88a;hb=7e68e81f4757ffff2261ab4a887d4114318aa5b6;hp=67c94c715b8374b67813318fb9842434ed7f7727;hpb=96e785b571a231265d64fbe5083371480cd3a549;p=kiibohd-controller.git diff --git a/Lib/mk20dx.h b/Lib/mk20dx.h index 67c94c7..ae69dd4 100644 --- a/Lib/mk20dx.h +++ b/Lib/mk20dx.h @@ -1,7 +1,7 @@ /* Teensyduino Core Library * http://www.pjrc.com/teensy/ * Copyright (c) 2013 PJRC.COM, LLC. - * Modified by Jacob Alexander 2014 + * Modified by Jacob Alexander 2014-2015 * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the @@ -29,20 +29,22 @@ * SOFTWARE. */ -#ifndef _mk20dx_h_ -#define _mk20dx_h_ +#pragma once // ----- Defines ----- #if (F_CPU == 96000000) - #define F_BUS 48000000 - #define F_MEM 24000000 + #define F_BUS 48000000 + #define F_MEM 24000000 +#elif (F_CPU == 72000000) + #define F_BUS 36000000 + #define F_MEM 24000000 #elif (F_CPU == 48000000) - #define F_BUS 48000000 - #define F_MEM 24000000 + #define F_BUS 48000000 + #define F_MEM 24000000 #elif (F_CPU == 24000000) - #define F_BUS 24000000 - #define F_MEM 24000000 + #define F_BUS 24000000 + #define F_MEM 24000000 #endif @@ -509,11 +511,37 @@ #define DMA_ERQ_ERQ1 ((uint32_t)1<<1) // Enable DMA Request 1 #define DMA_ERQ_ERQ2 ((uint32_t)1<<2) // Enable DMA Request 2 #define DMA_ERQ_ERQ3 ((uint32_t)1<<3) // Enable DMA Request 3 +#define DMA_ERQ_ERQ4 ((uint32_t)1<<4) // Enable DMA Request 4 +#define DMA_ERQ_ERQ5 ((uint32_t)1<<5) // Enable DMA Request 5 +#define DMA_ERQ_ERQ6 ((uint32_t)1<<6) // Enable DMA Request 6 +#define DMA_ERQ_ERQ7 ((uint32_t)1<<7) // Enable DMA Request 7 +#define DMA_ERQ_ERQ8 ((uint32_t)1<<8) // Enable DMA Request 8 +#define DMA_ERQ_ERQ9 ((uint32_t)1<<9) // Enable DMA Request 9 +#define DMA_ERQ_ERQ10 ((uint32_t)1<<10) // Enable DMA Request 10 +#define DMA_ERQ_ERQ11 ((uint32_t)1<<11) // Enable DMA Request 11 +#define DMA_ERQ_ERQ12 ((uint32_t)1<<12) // Enable DMA Request 12 +#define DMA_ERQ_ERQ13 ((uint32_t)1<<13) // Enable DMA Request 13 +#define DMA_ERQ_ERQ14 ((uint32_t)1<<14) // Enable DMA Request 14 +#define DMA_ERQ_ERQ15 ((uint32_t)1<<15) // Enable DMA Request 15 +#define DMA_ERQ_ERQ16 ((uint32_t)1<<16) // Enable DMA Request 16 #define DMA_EEI *(volatile uint32_t *)0x40008014 // Enable Error Interrupt Register #define DMA_EEI_EEI0 ((uint32_t)1<<0) // Enable Error Interrupt 0 #define DMA_EEI_EEI1 ((uint32_t)1<<1) // Enable Error Interrupt 1 #define DMA_EEI_EEI2 ((uint32_t)1<<2) // Enable Error Interrupt 2 #define DMA_EEI_EEI3 ((uint32_t)1<<3) // Enable Error Interrupt 3 +#define DMA_EEI_EEI4 ((uint32_t)1<<4) // Enable Error Interrupt 4 +#define DMA_EEI_EEI5 ((uint32_t)1<<5) // Enable Error Interrupt 5 +#define DMA_EEI_EEI6 ((uint32_t)1<<6) // Enable Error Interrupt 6 +#define DMA_EEI_EEI7 ((uint32_t)1<<7) // Enable Error Interrupt 7 +#define DMA_EEI_EEI8 ((uint32_t)1<<8) // Enable Error Interrupt 8 +#define DMA_EEI_EEI9 ((uint32_t)1<<9) // Enable Error Interrupt 9 +#define DMA_EEI_EEI10 ((uint32_t)1<<10) // Enable Error Interrupt 10 +#define DMA_EEI_EEI11 ((uint32_t)1<<11) // Enable Error Interrupt 11 +#define DMA_EEI_EEI12 ((uint32_t)1<<12) // Enable Error Interrupt 12 +#define DMA_EEI_EEI13 ((uint32_t)1<<13) // Enable Error Interrupt 13 +#define DMA_EEI_EEI14 ((uint32_t)1<<14) // Enable Error Interrupt 14 +#define DMA_EEI_EEI15 ((uint32_t)1<<15) // Enable Error Interrupt 15 +#define DMA_EEI_EEI16 ((uint32_t)1<<16) // Enable Error Interrupt 16 #define DMA_CEEI *(volatile uint8_t *)0x40008018 // Clear Enable Error Interrupt Register #define DMA_CEEI_CEEI(n) ((uint8_t)(n & 3)<<0) // Clear Enable Error Interrupt #define DMA_CEEI_CAEE ((uint8_t)1<<6) // Clear All Enable Error Interrupts @@ -1343,6 +1371,10 @@ #define SPI_SR_TFFF (uint32_t)0x02000000 // Transmit FIFO Fill Flag #define SPI_SR_RFOF (uint32_t)0x00080000 // Receive FIFO Overflow Flag #define SPI_SR_RFDF (uint32_t)0x00020000 // Receive FIFO Drain Flag +#define SPI_SR_TXCTR (uint32_t)0x0000F000 // Transmit FIFO Counter +#define SPI_SR_TXNXTPTR (uint32_t)0x00000F00 // Transmit Next, Pointer +#define SPI_SR_RXCTR (uint32_t)0x000000F0 // Receive FIFO Counter +#define SPI_SR_POPNXTPTR (uint32_t)0x0000000F // Pop Next, Pointer #define SPI0_RSER *(volatile uint32_t *)0x4002C030 // DSPI DMA/Interrupt Request Select and Enable Register #define SPI_RSER_TCF_RE (uint32_t)0x80000000 // Transmission Complete Request Enable #define SPI_RSER_EOQF_RE (uint32_t)0x10000000 // DSPI Finished Request Request Enable @@ -1462,6 +1494,8 @@ typedef struct { #define UART0_MA2 *(volatile uint8_t *)0x4006A009 // UART Match Address Registers 2 #define UART0_C4 *(volatile uint8_t *)0x4006A00A // UART Control Register 4 #define UART0_C5 *(volatile uint8_t *)0x4006A00B // UART Control Register 5 +#define UART_C5_TDMAS 0x80 +#define UART_C5_RDMAS 0x20 #define UART0_ED *(volatile uint8_t *)0x4006A00C // UART Extended Data Register #define UART0_MODEM *(volatile uint8_t *)0x4006A00D // UART Modem Register #define UART0_IR *(volatile uint8_t *)0x4006A00E // UART Infrared Register @@ -1945,7 +1979,9 @@ typedef struct { #define SCB_CFSR *(volatile uint32_t *)0xE000ED28 // Configurable Fault Status Register #define SCB_HFSR *(volatile uint32_t *)0xE000ED2C // HardFault Status #define SCB_DFSR *(volatile uint32_t *)0xE000ED30 // Debug Fault Status -#define SCB_MMFAR *(volatile uint32_t *)0xE000ED34 // MemManage Fault Address +#define SCB_MMAR *(volatile uint32_t *)0xE000ED34 // MemManage Fault Address +#define SCB_BFAR *(volatile uint32_t *)0xE000ED38 // BusFault Addreses Register +#define SCB_AFSR *(volatile uint32_t *)0xE000ED3C // Auxilary Fault Status Register #define SYST_CSR *(volatile uint32_t *)0xE000E010 // SysTick Control and Status #define SYST_CSR_COUNTFLAG (uint32_t)0x00010000 @@ -2083,5 +2119,3 @@ extern void portd_isr(void); extern void porte_isr(void); extern void software_isr(void); -#endif -