1 /* Copyright 2018 ishtob
2 * Driver for DRV2605L written for QMK
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "i2c_master.h"
21 /* Initialization settings
23 * Feedback Control Settings */
25 #define FB_ERM_LRA 1 /* For ERM:0 or LRA:1*/
27 #ifndef FB_BRAKEFACTOR
28 #define FB_BRAKEFACTOR 3 /* For 1x:0, 2x:1, 3x:2, 4x:3, 6x:4, 8x:5, 16x:6, Disable Braking:7 */
31 #define FB_LOOPGAIN 1 /* For Low:0, Medium:1, High:2, Very High:3 */
34 /* LRA specific settings */
46 #define RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */
51 #define RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */
57 /* Library Selection */
60 #define LIB_SELECTION 6 /* For Empty:0' TS2200 library A to D:1-5, LRA Library: 6 */
62 #define LIB_SELECTION 1
67 #define DRV_GREETING alert_750ms
69 #ifndef DRV_MODE_DEFAULT
70 #define DRV_MODE_DEFAULT strong_click1
73 /* Control 1 register settings */
81 #define STARTUP_BOOST 1
84 /* Control 2 Settings */
89 #define BRAKE_STAB 1 /* Loopgain is reduced when braking is almost complete to improve stability */
95 #define BLANKING_TIME 1
101 /* Control 3 settings */
105 #ifndef ERM_OPEN_LOOP
106 #define ERM_OPEN_LOOP 1
108 #ifndef SUPPLY_COMP_DIS
109 #define SUPPLY_COMP_DIS 0
111 #ifndef DATA_FORMAT_RTO
112 #define DATA_FORMAT_RTO 0
114 #ifndef LRA_DRIVE_MODE
115 #define LRA_DRIVE_MODE 0
118 #define N_PWM_ANALOG 0
120 #ifndef LRA_OPEN_LOOP
121 #define LRA_OPEN_LOOP 0
124 /* Control 4 settings */
126 #define ZC_DET_TIME 0
128 #ifndef AUTO_CAL_TIME
129 #define AUTO_CAL_TIME 3
132 /* register defines -------------------------------------------------------- */
133 #define DRV2605L_BASE_ADDRESS 0x5A /* DRV2605L Base address */
134 #define DRV_STATUS 0x00
135 #define DRV_MODE 0x01
136 #define DRV_RTP_INPUT 0x02
137 #define DRV_LIB_SELECTION 0x03
138 #define DRV_WAVEFORM_SEQ_1 0x04
139 #define DRV_WAVEFORM_SEQ_2 0x05
140 #define DRV_WAVEFORM_SEQ_3 0x06
141 #define DRV_WAVEFORM_SEQ_4 0x07
142 #define DRV_WAVEFORM_SEQ_5 0x08
143 #define DRV_WAVEFORM_SEQ_6 0x09
144 #define DRV_WAVEFORM_SEQ_7 0x0A
145 #define DRV_WAVEFORM_SEQ_8 0x0B
147 #define DRV_OVERDRIVE_TIME_OFFSET 0x0D
148 #define DRV_SUSTAIN_TIME_OFFSET_P 0x0E
149 #define DRV_SUSTAIN_TIME_OFFSET_N 0x0F
150 #define DRV_BRAKE_TIME_OFFSET 0x10
151 #define DRV_AUDIO_2_VIBE_CTRL 0x11
152 #define DRV_AUDIO_2_VIBE_MIN_IN 0x12
153 #define DRV_AUDIO_2_VIBE_MAX_IN 0x13
154 #define DRV_AUDIO_2_VIBE_MIN_OUTDRV 0x14
155 #define DRV_AUDIO_2_VIBE_MAX_OUTDRV 0x15
156 #define DRV_RATED_VOLT 0x16
157 #define DRV_OVERDRIVE_CLAMP_VOLT 0x17
158 #define DRV_AUTO_CALIB_COMP_RESULT 0x18
159 #define DRV_AUTO_CALIB_BEMF_RESULT 0x19
160 #define DRV_FEEDBACK_CTRL 0x1A
161 #define DRV_CTRL_1 0x1B
162 #define DRV_CTRL_2 0x1C
163 #define DRV_CTRL_3 0x1D
164 #define DRV_CTRL_4 0x1E
165 #define DRV_CTRL_5 0x1F
166 #define DRV_OPEN_LOOP_PERIOD 0x20
167 #define DRV_VBAT_VOLT_MONITOR 0x21
168 #define DRV_LRA_RESONANCE_PERIOD 0x22
171 void DRV_write(const uint8_t drv_register, const uint8_t settings);
172 uint8_t DRV_read(const uint8_t regaddress);
173 void DRV_pulse(const uint8_t sequence);
175 typedef enum DRV_EFFECT{
194 strong_click2_80 = 18,
195 strong_click3_60 = 19,
196 strong_click4_30 = 20,
198 medium_click2_80 = 22,
199 medium_click3_60 = 23,
203 sh_dblclick_str = 27,
204 sh_dblclick_str_80 = 28,
205 sh_dblclick_str_60 = 29,
206 sh_dblclick_str_30 = 30,
207 sh_dblclick_med = 31,
208 sh_dblclick_med_80 = 32,
209 sh_dblclick_med_60 = 33,
210 sh_dblsharp_tick = 34,
211 sh_dblsharp_tick_80 = 35,
212 sh_dblsharp_tick_60 = 36,
213 lg_dblclick_str = 37,
214 lg_dblclick_str_80 = 38,
215 lg_dblclick_str_60 = 39,
216 lg_dblclick_str_30 = 40,
217 lg_dblclick_med = 41,
218 lg_dblclick_med_80 = 42,
219 lg_dblclick_med_60 = 43,
220 lg_dblsharp_tick = 44,
221 lg_dblsharp_tick_80 = 45,
222 lg_dblsharp_tick_60 = 46,
229 pulsing_strong_80 = 53,
231 pulsing_medium_80 = 55,
233 pulsing_sharp_80 = 57,
234 transition_click = 58,
235 transition_click_80 = 59,
236 transition_click_60 = 60,
237 transition_click_40 = 61,
238 transition_click_20 = 62,
239 transition_click_10 = 63,
241 transition_hum_80 = 65,
242 transition_hum_60 = 66,
243 transition_hum_40 = 67,
244 transition_hum_20 = 68,
245 transition_hum_10 = 69,
246 transition_rampdown_long_smooth1 = 70,
247 transition_rampdown_long_smooth2 = 71,
248 transition_rampdown_med_smooth1 = 72,
249 transition_rampdown_med_smooth2 = 73,
250 transition_rampdown_short_smooth1 = 74,
251 transition_rampdown_short_smooth2 = 75,
252 transition_rampdown_long_sharp1 = 76,
253 transition_rampdown_long_sharp2 = 77,
254 transition_rampdown_med_sharp1 = 78,
255 transition_rampdown_med_sharp2 = 79,
256 transition_rampdown_short_sharp1 = 80,
257 transition_rampdown_short_sharp2 = 81,
258 transition_rampup_long_smooth1 = 82,
259 transition_rampup_long_smooth2 = 83,
260 transition_rampup_med_smooth1 = 84,
261 transition_rampup_med_smooth2 = 85,
262 transition_rampup_short_smooth1 = 86,
263 transition_rampup_short_smooth2 = 87,
264 transition_rampup_long_sharp1 = 88,
265 transition_rampup_long_sharp2 = 89,
266 transition_rampup_med_sharp1 = 90,
267 transition_rampup_med_sharp2 = 91,
268 transition_rampup_short_sharp1 = 92,
269 transition_rampup_short_sharp2 = 93,
270 transition_rampdown_long_smooth1_50 = 94,
271 transition_rampdown_long_smooth2_50 = 95,
272 transition_rampdown_med_smooth1_50 = 96,
273 transition_rampdown_med_smooth2_50 = 97,
274 transition_rampdown_short_smooth1_50 = 98,
275 transition_rampdown_short_smooth2_50 = 99,
276 transition_rampdown_long_sharp1_50 = 100,
277 transition_rampdown_long_sharp2_50 = 101,
278 transition_rampdown_med_sharp1_50 = 102,
279 transition_rampdown_med_sharp2_50 = 103,
280 transition_rampdown_short_sharp1_50 = 104,
281 transition_rampdown_short_sharp2_50 = 105,
282 transition_rampup_long_smooth1_50 = 106,
283 transition_rampup_long_smooth2_50 = 107,
284 transition_rampup_med_smooth1_50 = 108,
285 transition_rampup_med_smooth2_50 = 109,
286 transition_rampup_short_smooth1_50 = 110,
287 transition_rampup_short_smooth2_50 = 111,
288 transition_rampup_long_sharp1_50 = 112,
289 transition_rampup_long_sharp2_50 = 113,
290 transition_rampup_med_sharp1_50 = 114,
291 transition_rampup_med_sharp2_50 = 115,
292 transition_rampup_short_sharp1_50 = 116,
293 transition_rampup_short_sharp2_50 = 117,
294 long_buzz_for_programmatic_stopping = 118,
295 smooth_hum1_50 = 119,
296 smooth_hum2_40 = 120,
297 smooth_hum3_30 = 121,
298 smooth_hum4_20 = 122,
299 smooth_hum5_10 = 123,
300 drv_effect_max = 124,
303 /* Register bit array unions */
305 typedef union DRVREG_STATUS { /* register 0x00 */
308 uint8_t OC_DETECT :1; /* set to 1 when overcurrent event is detected */
309 uint8_t OVER_TEMP :1; /* set to 1 when device exceeds temp threshold */
310 uint8_t FB_STS :1; /* set to 1 when feedback controller has timed out */
311 /* auto-calibration routine and diagnostic result
312 * result | auto-calibation | diagnostic |
313 * 0 | passed | actuator func normal |
314 * 1 | failed | actuator func fault* |
315 * * actuator is not present or is shorted, timing out, or giving out–of-range back-EMF */
316 uint8_t DIAG_RESULT :1;
318 uint8_t DEVICE_ID :3; /* Device IDs 3: DRV2605 4: DRV2604 5: DRV2604L 6: DRV2605L */
322 typedef union DRVREG_MODE { /* register 0x01 */
325 uint8_t MODE :3; /* Mode setting */
327 uint8_t STANDBY :1; /* 0:standby 1:ready */
331 typedef union DRVREG_WAIT {
334 uint8_t WAIT_MODE :1; /* Set to 1 to interpret as wait for next 7 bits x10ms */
335 uint8_t WAIT_TIME :7;
339 typedef union DRVREG_FBR{ /* register 0x1A */
342 uint8_t BEMF_GAIN :2;
343 uint8_t LOOP_GAIN :2;
344 uint8_t BRAKE_FACTOR :3;
349 typedef union DRVREG_CTRL1{ /* register 0x1B */
352 uint8_t C1_DRIVE_TIME :5;
353 uint8_t C1_AC_COUPLE :1;
355 uint8_t C1_STARTUP_BOOST :1;
359 typedef union DRVREG_CTRL2{ /* register 0x1C */
362 uint8_t C2_IDISS_TIME :2;
363 uint8_t C2_BLANKING_TIME :2;
364 uint8_t C2_SAMPLE_TIME :2;
365 uint8_t C2_BRAKE_STAB :1;
366 uint8_t C2_BIDIR_INPUT :1;
370 typedef union DRVREG_CTRL3{ /* register 0x1D */
373 uint8_t C3_LRA_OPEN_LOOP :1;
374 uint8_t C3_N_PWM_ANALOG :1;
375 uint8_t C3_LRA_DRIVE_MODE :1;
376 uint8_t C3_DATA_FORMAT_RTO :1;
377 uint8_t C3_SUPPLY_COMP_DIS :1;
378 uint8_t C3_ERM_OPEN_LOOP :1;
379 uint8_t C3_NG_THRESH :2;
383 typedef union DRVREG_CTRL4{ /* register 0x1E */
386 uint8_t C4_OTP_PROGRAM :1;
388 uint8_t C4_OTP_STATUS :1;
390 uint8_t C4_AUTO_CAL_TIME :2;
391 uint8_t C4_ZC_DET_TIME :2;
395 typedef union DRVREG_CTRL5{ /* register 0x1F */
398 uint8_t C5_IDISS_TIME :2;
399 uint8_t C5_BLANKING_TIME :2;
400 uint8_t C5_PLAYBACK_INTERVAL :1;
401 uint8_t C5_LRA_AUTO_OPEN_LOOP :1;
402 uint8_t C5_AUTO_OL_CNT :2;